PHILIPS SAA7125HZ

INTEGRATED CIRCUITS
DATA SHEET
SAA7124; SAA7125
Digital Video Encoder
(ECO-DENC)
Preliminary specification
File under Integrated Circuits, IC22
1996 Nov 07
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
FEATURES
• Monolithic CMOS 5 V device
• Digital PAL/NTSC encoder
• System pixel frequency 13.5 MHz
• Accepts MPEG decoded data on 8-bit wide input port.
Input data format Cb, Y, Cr etc. “(CCIR 656)”
• Controlled rise and fall times of output syncs and
blanking
• Four DACs for CVBS (10-bit resolution), RGB (9-bit
resolution) operating at 27 MHz; RGB sync on CVBS
• Down-mode of DACs
• Optionally 2 times CVBS and Y, C (all 10-bit resolution)
available simultaneously
• LQFP64 (V1 devices only), QFP80 or PLCC84
package.
• Closed captioning encoding
• On-chip YUV to RGB dematrix optionally to be
by-passed for Cr, Y, Cb output on RGB DACs
GENERAL DESCRIPTION
• Fast I2C-bus control port (400 kHz)
The SAA7124; SAA7125 encodes digital YUV video data
to an NTSC or PAL CVBS plus RGB or alternatively to
S-Video and CVBS output.
• Encoder can be master or slave
• Programmable horizontal and vertical input
synchronization phase, via input pins or auxiliary codes
at MP data port
Optionally, the YUV to RGB dematrix can be by-passed
providing the digital-to-analog converted Cb, Y, Cr signals
instead of RGB.
• Programmable horizontal sync output phase
The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 : 2 : 2 multiplexed formats,
for example MPEG decoded data.
• Internal 100/75 Colour Bar Generator (CBG)
• Macrovision Pay-per-View copy protection system as
option, also partly used for RGB output.
It includes a sync/clock generator and on-chip
Digital-to-Analog Converters (DACs).
This applies to SAA7124 only. The device is protected
by USA patent numbers 4631603, 4577216 and
4819098 and other intellectual property rights. Use of
the Macrovision anti-copy process in the device is
licensed for non-commercial home use only.
Reverse engineering or disassembly is prohibited.
Please contact your nearest Philips Semiconductor
sales office for more information
ORDERING INFORMATION
TYPE
NUMBER
PACKAGE(1)
NAME
DESCRIPTION
VERSION
SAA7124WP;
SAA7125WP
PLCC84
plastic leaded chip carrier; 84 leads
SOT189-2
SAA7124HZ;
SAA7125HZ
LQFP64
plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4 mm
SOT314-2
SAA7124H;
SAA7125H
QFP80
plastic quad flat package; 80 leads (lead length 2.35 mm);
body 14 × 20 × 2.8 mm
SOT318-3
Note
1. LQFP64 package for V1 devices only.
1996 Nov 07
2
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
QUICK REFERENCE DATA
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
VDDA
analog supply voltage
4.75
5.0
5.25
V
VDDD
digital supply voltage
4.75
5.0
5.25
V
IDDA
analog supply current
−
tbf
60
mA
IDDD
digital supply current
−
tbf
100
mA
Vi
input signal voltage levels
Vo(p-p)
analog output signal voltages Y, C, CVBS and RGB without load −
(peak-to-peak value)
2.0
−
V
RL
load resistance
80
−
−
Ω
ILE
LF integral linearity error
−
−
±4
LSB
DLE
LF differential linearity error
−
−
±1
LSB
Tamb
operating ambient temperature
0
−
+70
°C
1996 Nov 07
TTL compatible
3
1996 Nov 07
(1)
(2)
(3)
(4)
(5)
4
CbCr
Y
to
VDDD9
VSSD9
5, 14, 22,
29, 38, 41,
49, 80, 82
VDDD1
3, 15, 24,
30, 39, 42,
51, 79, 81
SAA7124
SAA7125
I2C-bus
control
to
8
DATA
MANAGER
I2C-bus
control
VSSD1
25 to 28,
31 to 34
8
4
8
n.c.
CbCr
Y
46
45
I2C-bus
control
8
8
I2C-bus
control
I2C-bus
control
OUTPUT
INTERFACE
8
78
AP
77
RGB
PROCESSOR
SP
internal
control bus
C
Y
36
SYNC CLOCK
35
clock
and timing
50
(5)
48
LLC
res
69, 71
I2C-bus
control
44
XTALI
RCV1 VDDDO
XTALO
RCV2
Fig.1 Block diagram; PLCC84.
2, 16 to 21, 23,
40, 43, 47, 66,
70, 72
I2C-bus
control
ENCODER
37
CDIR
A
VrefL2
63, 68
CUR1
CUR2
52, 76
2
VrefL1
2
MODE
D
55
58
61
65
56
59
62
67
73
53, 75
54, 57, 60,
64, 74
VDDA1 to VDDA5
2
MGG550
BLUE(4)
GREEN(3)
RED(2)
res
res
res
res
VSSA1
CVBS(1)
VrefH1
VrefH2
Digital Video Encoder (ECO-DENC)
Alternatively Y or CVBS.
Alternatively CHROMA or Cr.
Alternatively CVBS or Yin.
Alternatively CVBS or Cb.
V1 devices only.
MP7
to
MP0
83
I2C-BUS
INTERFACE
84
RTCI
full pagewidth
1
RESET SDA SCL SA
Philips Semiconductors
Preliminary specification
SAA7124; SAA7125
BLOCK DIAGRAM
1996 Nov 07
(1)
(2)
(3)
(4)
5
CbCr
Y
to
VDDD9
VSSD8
I2C-bus
control
8
Y
28
27
I2C-bus
control
8
8
I2C-bus
control
I2C-bus
control
OUTPUT
INTERFACE
8
50
AP
49
RGB
PROCESSOR
SP
internal
control bus
C
Y
20
SYNC CLOCK
19
clock
and timing
31
CbCr
ENCODER
21
29
LLC
I2C-bus
control
26
XTALI
RCV1 VDDDO
XTALO
RCV2
Fig.2 Block diagram; TQFP64, V1 devices only.
5, 7, 13,
22, 24, 30,
52, 54, 60
VDDD1
6, 8, 14,
23, 25, 51,
53, 58
SAA7124
SAA7125
I2C-bus
control
to
8
DATA
MANAGER
I2C-bus
control
VSSD1
9 to 12,
15 to 18
8
59
CDIR
A
VrefL2
40, 44
CUR1
CUR2
32, 48
2
VrefL1
2
MODE
D
2
35
37
39
42,
43 2
45
33, 47
34, 36, 38,
41, 46
VDDA1 to VDDA5
MGG551
BLUE(4)
GREEN(3)
RED(2)
VSSA2
CVBS(1)
VrefH1
VrefH2
Digital Video Encoder (ECO-DENC)
Alternatively Y or CVBS.
Alternatively CHROMA or Cr.
Alternatively CVBS or Yin.
Alternatively CVBS or Cb.
MP7
to
MP0
55
I2C-BUS
INTERFACE
56
RTCI
full pagewidth
57
RESET SDA SCL SA
Philips Semiconductors
Preliminary specification
SAA7124; SAA7125
1996 Nov 07
(1)
(2)
(3)
(4)
(5)
6
CbCr
Y
to
VDDD9
VSSD9
5, 13, 19,
28, 30, 37,
68, 70, 76
VDDD1
6, 14, 20,
29, 31, 39,
67, 69, 74
SAA7124
SAA7125
I2C-bus
control
to
8
DATA
MANAGER
I2C-bus
control
VSSD1
15 to 18,
21 to 24
8
75
8
n.c.
CbCr
Y
34
33
control
8
8
I2C-bus
control
I2C-bus
control
OUTPUT
INTERFACE
8
I2C-bus
66
AP
65
RGB
PROCESSOR
SP
internal
control bus
C
Y
26
SYNC CLOCK
25
clock
and timing
38
(5)
36
LLC
res
57, 59
I2C-bus
control
32
XTALI
RCV1 VDDDO
XTALO
RCV2
Fig.3 Block diagram; QFP80.
7 to 12, 35, 40
58, 60
I2C-bus
control
ENCODER
27
CDIR
A
VrefL2
52, 56
CUR1
CUR2
41, 64
2
VrefL1
2
MODE
D
44
47
50
45
48
51
54
55
61
53, 75
54, 57, 60,
64, 74
VDDA1 to VDDA5
2
MGG552
BLUE(4)
GREEN(3)
RED(2)
res
res
res
res
VSSA1
CVBS(1)
VrefH1
VrefH2
Digital Video Encoder (ECO-DENC)
Alternatively Y or CVBS.
Alternatively CHROMA or Cr.
Alternatively CVBS or Yin.
Alternatively CVBS or Cb.
V1 devices only.
MP7
to
MP0
71
I2C-BUS
INTERFACE
72
RTCI
agewidth
73
RESET SDA SCL SA
Philips Semiconductors
Preliminary specification
SAA7124; SAA7125
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
PINNING
PIN
SYMBOL
TYPE
DESCRIPTION
PLCC84 LQFP64
QFP80
RESET
I
1
57
73
Reset input, active LOW. After reset is applied, all digital I/Os
are in input mode. The I2C-bus receiver waits for the START
condition.
n.c.
−
2
−
−
not connected
VSSD1
I
3
6
6
digital ground 1
SA
I
4
59
75
The I2C-bus slave address select input pin. LOW: slave
address = 88H, HIGH = 8CH.
VDDD1
I
5
5
5
digital supply voltage 1
TP1
O
6
61
77
TP2
O
7
62
78
TP3
O
8
63
79
TP4
O
9
64
80
TP5
O
10
1
1
TP6
O
11
2
2
TP7
O
12
3
3
TP8
O
13
4
4
VDDD2
I
14
7
13
digital supply voltage 2
VSSD2
I
15
8
14
digital ground 2
n.c.
−
16
−
7
n.c.
−
17
−
8
n.c.
−
18
−
9
n.c.
−
19
−
10
n.c.
−
20
−
11
n.c.
−
21
−
12
Test pin outputs. Leave open for normal operation.
not connected
VDDD3
I
22
13
19
digital supply voltage 3
n.c.
−
23
−
−
not connected
VSSD3
I
24
14
20
digital ground 3
MP7
I
25
9
15
MP6
I
26
10
16
MP5
I
27
11
17
MP4
I
28
12
18
VDDD4
I
29
22
28
digital supply voltage 4
VSSD4
I
30
23
29
digital ground 4
MP3
I
31
15
21
MP2
I
32
16
22
MP1
I
33
17
23
I
34
18
24
I/O
35
19
25
MP0
RCV1
1996 Nov 07
Upper 4 bits of MPEG port. It is an input for “CCIR 656” style
multiplexed Cb, Y, Cr data.
Lower 4 bits of MPEG port. It is an input for “CCIR 656” style
multiplexed Cb, Y, Cr data.
Raster Control 1 for video port. This pin receives/provides a
VS/FS/FSEQ signal.
7
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
PIN
SYMBOL
TYPE
DESCRIPTION
PLCC84 LQFP64
QFP80
RCV2
I/O
36
20
26
Raster Control 2 for video port. This pin provides an HS pulse
of programmable length or receives an HS pulse.
RTCI
I
37
21
27
Real Time Control input. If the LLC clock is provided by an
SAA7111 or SAA7151B, RTCI should be connected to the
RTCO pin of the respective decoder to improve the signal
quality.
VDDD5
I
38
24
30
digital supply voltage 5
VSSD5
I
39
25
31
digital ground 5
n.c.
−
40
−
35
not connected
VDDD6
I
41
30
37
digital supply voltage 6
VSSD6
I
42
51
39
digital ground 6
n.c.
−
43
−
40
not connected
XTALI
I
44
26
32
Crystal oscillator input (from crystal). If the oscillator is not
used, this pin should be connected to ground.
XTALO
O
45
27
33
Crystal oscillator output (to crystal).
VDDDO
I
46
28
34
digital supply voltage for the internal oscillator; note 1
n.c.
−
47
−
−
not connected
LLC
I/O
48
29
36
Line-Locked Clock. This is the 27 MHz master clock for the
encoder. The I/O direction is set by the CDIR pin.
VDDD7
I
49
52
68
digital supply voltage 7
CDIR
I
50
31
38
Clock direction. If CDIR input is HIGH, the circuit receives a
clock signal, otherwise if CDIR is LOW, LLC is generated by
the internal crystal oscillator.
VSSD7
I
51
53
67
digital ground 7
VrefL1
I
52
32
41
Lower reference voltage 1 input for DACs; connect to analog
ground.
VrefH1
I
53
33
42
Upper reference voltage 1 input for DACs; connect via 100 nF
capacitor to analog ground.
VDDA1
I
54
34
43
Analog supply voltage 1 for DACs.
BLUE
O
55
35
44
Analog output of the BLUE component.
res
I
56
−
45
reserved
VDDA2
I
57
36
46
Analog supply voltage 2 for DACs.
GREEN
O
58
37
47
Analog output of GREEN component.
res
I
59
−
48
reserved
VDDA3
I
60
38
49
Analog supply voltage 3 for DACs.
RED
O
61
39
50
Analog output of RED component.
res
I
62
−
51
reserved
CUR1
I
63
40
52
Current input 1 for RGB amplifiers; connect via 15 kΩ resistor
to VDDA.
VDDA4
I
64
41
53
Analog supply voltage 4 for DACs.
res
I
65
−
54
reserved
n.c.
−
66
−
−
not connected
1996 Nov 07
8
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
PIN
SYMBOL
TYPE
DESCRIPTION
PLCC84 LQFP64
QFP80
VSSA1
I
67
42
55
Analog ground 1 for the DACs.
VSSA2
I
−
43
−
Analog ground 2 for the DACs.
CUR2
I
68
44
56
Current input 2 for RGB amplifiers; connect via 15 kΩ resistor
to VDDA.
res
O
69
−
57
reserved
n.c.
−
70
−
58
not connected
res
O
71
−
59
reserved
n.c.
−
72
−
60
not connected
CVBS
O
73
45
61
Analog output of the CVBS signal.
VDDA5
I
74
46
62
Analog supply voltage 5 for DACs.
VrefH2
I
75
47
63
Upper reference voltage 2 input for DACs; connect via 100 nF
capacitor to analog ground.
VrefL2
I
76
48
64
Lower reference voltage 2 input for DACs; connect to analog
ground.
AP
I
77
49
65
Test pin. Connected to digital ground for normal operation.
SP
I
78
50
66
Test pin. Connected to digital ground for normal operation.
VSSD8
I
79
58
69
digital ground 8
VDDD8
I
80
54
70
digital supply voltage 8
VSSD9
I
81
−
74
digital ground 9
VDDD9
I
82
60
76
digital supply voltage 9
SCL
I
83
55
71
I2C-bus serial clock input.
SDA
I/O
84
56
72
I2C-bus serial data input/output.
Note
1. V1 devices only.
1996 Nov 07
9
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
TP6
TP5
TP4
TP3
TP2
TP1
VDDD1
SA
VSSD1
n.c.
RESET
SDA
SCL
VDDD9
VSSD9
VDDD8
VSSD8
SP
AP
VrefL2
VrefH2
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
handbook, full pagewidth
TP7 12
74 VDDA5
TP8 13
73 CVBS
VDDD2 14
72 n.c.
VSSD2 15
71 res
n.c. 16
70 n.c.
n.c. 17
69 res
n.c. 18
68 CUR2
n.c. 19
67 VSSA1
n.c. 20
66 n.c.
n.c. 21
65 res
VDDD3 22
64 VDDA4
SAA7124
SAA7125
n.c. 23
63 CUR1
VSSD3 24
62 res
MP7 25
61 RED
MP6 26
60 VDDA3
MP5 27
59 res
MP4 28
58 GREEN
VDDD4 29
57 VDDA2
VSSD4 30
56 res
(1) V1 devices only.
Fig.4 Pin configuration; PLCC84.
1996 Nov 07
10
Vref H1 53
VrefL1 52
VSSD7 51
CDIR 50
VDDD7 49
LLC 48
n.c. 47
VDDDO(1) 46
XTALO 45
XTALI 44
n.c. 43
VSSD6 42
VDDD6 41
n.c. 40
VSSD5 39
VDDD5 38
RTCI 37
RCV2 36
54 VDDA1
RCV1 35
MP2 32
MP0 34
55 BLUE
MP1 33
MP3 31
MGG548
Philips Semiconductors
Preliminary specification
TP5
1
48 VrefL2
TP6
2
47 VrefH2
TP7
3
46 VDDA5
TP8
4
45 CVBS
VDDD1
5
44 CUR2
VSSD1
6
43 VSSA2
VDDD2
7
42 VSSA1
VSSD2
8
MP7
9
MP6
10
39 RED
MP5
11
38 VDDA3
MP4
12
37 GREEN
VDDD3
13
36 VDDA2
VSSD3
14
35 BLUE
MP3
15
34 VDDA1
MP2
16
33 VrefH1
41 VDDA4
25
26
27
28
29
VSSD5
XTALI
XTALO
VDDDO
LLC
32
24
VDDD5
VrefL1
23
VSSD4
31
22
VDDD4
CDIR
21
RTCI
VDDD6 30
20
40 CUR1
RCV2
RCV1 19
MP0 18
MP1 17
SAA7124
SAA7125
Fig.5 Pin configuration; LQFP64 (V1 devices only).
1996 Nov 07
49 AP
50 SP
51 VSSD6
52 VDDD7
53 VSSD7
54 VDDD8
56 SDA
55 SCL
SAA7124; SAA7125
57 RESET
58 VSSD8
59 SA
61 TP1
62 TP2
63 TP3
64 TP4
handbook, full pagewidth
60 VDDD9
Digital Video Encoder (ECO-DENC)
11
MGG547
Philips Semiconductors
Preliminary specification
65 AP
66 SP
67 VSSD7
68 VDDD7
69 VSSD8
70 VDDD8
71 SCL
72 SDA
SAA7124; SAA7125
73 RESET
74 VSSD9
75 SA
77 TP1
78 TP2
79 TP3
80 TP4
handbook, full pagewidth
76 VDDD9
Digital Video Encoder (ECO-DENC)
TP5
1
64
VrefL2
TP6
2
63
VrefH2
TP7
3
62
VDDA5
TP8
4
61
CVBS
VDDD1
5
60
n.c.
VSSD1
6
59
res
n.c.
7
58
n.c.
n.c.
8
57
res
n.c.
9
56
CUR2
n.c. 10
55
VSSA1
n.c. 11
54
res
53
VDDA4
52
CUR1
VSSD2 14
51
res
MP7 15
50
RED
MP6 16
49
VDDA3
MP5 17
48
res
MP4 18
47
GREEN
VDDD3 19
46
VDDA2
VSSD3 20
45
res
MP3 21
44
BLUE
MP2 22
43
VDDA1
MP1 23
42
VrefH1
MP0 24
41
VrefL1
n.c. 12
(1) V1 devices only.
Fig.6 Pin configuration; QFP80.
1996 Nov 07
12
n.c. 40
VSSD6 39
CDIR 38
VDDD6 37
LLC 36
n.c. 35
34
VDDDO
(1)
XTALO 33
VSSD5 31
VDDD5 30
VSSD4 29
VDDD4 28
RTCI 27
RCV2 26
RCV1 25
VDDD2 13
XTALI 32
SAA7124
SAA7125
MGG549
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
The encoder can be configured as slave with respect to
RCV trigger inputs or auxiliary “CCIR 656” codes, or can
be master to output horizontal and vertical trigger pulses.
FUNCTIONAL DESCRIPTION
The digital video encoder (ECO-DENC) encodes digital
luminance and colour difference signals into analog CVBS
and simultaneously RGB signals. NTSC-M, PAL B/G
standards and sub-standards are supported.
The IC also contains Closed Caption and Extended Data
Services Encoding (Line 21), and supports anti-taping
signal generation in accordance with Macrovision.
Both interlaced and non-interlaced operation is possible
for all standards.
A number of possibilities are provided for setting different
video parameters such as:
Optionally, the input Y, Cb and Cr data, digital-to-analog
converted, is available at the analog RGB outputs.
Black and blanking level control
Colour subcarrier frequency
For applications that do not require RGB output, the device
can be configured in such a way that S-Video and twice
CVBS is available (Y at CVBS-DAC, C at R-DAC, and
CVBS at G-DAC and B-DAC).
Variable burst amplitude etc.
During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to input mode. A reset forces
the I2C-bus interface to abort any running bus transfer and
sets register 3A to 03H, register 61 to 06H and
registers 6BH and 6EH to 00H. All other control registers
are not influenced by a reset.
The basic encoder function consists of subcarrier
generation, colour modulation and insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of “RS-170-A” and “CCIR 624”.
Data manager
For ease of analog post filtering the signals are twice
oversampled with respect to the pixel clock before
digital-to-analog conversion.
In the data manager, real time arbitration on the data
stream to be encoded is performed.
Optionally, the device can operate as a 100/75 colour bar
test pattern generator without need for an external data
source.
For total filter transfer characteristics see
Figs 7, 8, 9, 10, 11 and 12. The DACs for Y, C, and CVBS
are realized with full 10-bit resolution, DACs for RGB with
9-bit resolution.
Encoder
The MPEG port (MP) accepts 8 line multiplexed Cb, Y, Cr
data.
VIDEO PATH
The 8-bit multiplexed Cb-Y-Cr formats are “CCIR 656”
(D1 format) compatible, but auxiliary codes such as SAV
and EAV are decoded optionally for trigger purposes.
The encoder generates out of Y, U and V baseband
signals luminance and colour subcarrier output signals,
suitable for use as CVBS or separate Y and C signals.
A crystal-stable master clock (LLC) of 27 MHz, which is
twice the CCIR line-locked pixel clock of 13.5 MHz, needs
to be supplied externally. Optionally, a crystal oscillator
input/output pair of pins and an on-chip clock driver is
provided.
Luminance is modified in gain and in offset (latter
programmable in a certain range to enable different black
level set-ups). After having been inserted a fixed
synchronization level, in accordance with standard
composite synchronization schemes, and blanking level,
programmable also in a certain range to allow for
manipulations with Macrovision anti-taping, additional
insertion of AGC super-white pulses, programmable in
height, is supported.
It is also possible to connect a Philips Digital Video
Decoder (SAA7111 or SAA7151B) in conjunction with a
CREF clock qualifier to ECO-DENC. Via the RTCI pin,
connected to RTCO of a decoder, information concerning
actual subcarrier, PAL-ID, and if connected to SAA7111,
definite subcarrier phase can be inserted.
In order to enable easy analog post filtering, luminance is
interpolated from 13.5 MHz data rate to 27 MHz data rate,
providing luminance in 10-bit resolution. This filter is also
used to define smoothed transients for synchronization
pulses and blanking period. For transfer characteristic of
the luminance interpolation filter see Figs 9 and 10.
The ECO-DENC synthesizes all necessary internal
signals, colour subcarrier frequency, and synchronization
signals, from that clock.
1996 Nov 07
13
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
Chrominance is modified in gain (programmable
separately for U and V), standard dependent burst is
inserted, before baseband colour signals are interpolated
from 6.75 MHz data rate to 27 MHz data rate. One of the
interpolation stages can be bypassed, thus providing a
higher colour bandwidth, which can be made use of for
Y and C output. For transfer characteristics of the
chrominance interpolation filter see Figs 7 and 8.
Output interface/DACs
In the output interface encoded both Y and C signals are
converted from digital-to-analog in 10-bit resolution.
Y and C signals are also combined to a 10-bit CVBS
signal.
RED, GREEN and BLUE signals (optionally Cr, Y, Cb) are
also converted from digital-to-analog, each providing a
9-bit resolution.
The amplitude of inserted burst is programmable in a
certain range, suitable for standard signals and for special
effects. Behind the succeeding quadrature modulator,
colour in 10-bit resolution is provided on subcarrier.
All output occurs with the same processing delay.
Absolute amplitudes at the input of the DAC for CVBS is
reduced by 15⁄16 with respect to Y and C DACs to make
maximum use of conversion ranges.
The numeric ratio between Y and C outputs is in
accordance with set standards.
Depending on control bits YC_EN and DEMOFF, different
signal combinations are available at DACs #1 to #4.
YC_EN = DEMOFF = LOW is the default configuration
after reset.
CLOSED CAPTION ENCODER
Using this circuit, data in accordance with the specification
of Closed Caption or Extended Data Service, delivered by
the control interface, can be encoded (Line 21).
Two dedicated pairs of bytes (two bytes per field), each
pair preceded by run-in clocks and framing code, are
possible.
Table 1
The actual line number where data is to be encoded in, can
be modified in a certain range.
Data clock frequency is in accordance with definition for
NTSC-M standard 32 times horizontal line frequency.
Control of DAC signals
YC_EN
DEMOFF
DAC1
DAC2
DAC3
0
0
0
1
1
1
DAC4
CVBS
R
G
B
CVBS
Cr
Y
Cb
0
VBS
C
CVBS
CVBS
1
VBS
C
CVBS
CVBS
Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.
Outputs of the DACs can be set together in two groups
(#1 and #2 by DOWNB, #3 and #4 by DOWNA) via
software control to minimum output voltage for either
purpose.
It is also possible to encode Closed Caption Data for 50 Hz
field frequencies at 32 times horizontal line frequency.
Synchronization
ANTI-TAPING (SAA7124 ONLY)
Synchronization of the ECO-DENC is able to operate in
two modes; slave mode and master mode.
For more information contact your nearest Philips
Semiconductors sales office.
In the slave mode, the circuit accepts synchronization
pulses at the bidirectional RCV1 port (or equivalently as
frame synchronization from “CCIR 656” data stream).
The timing and trigger behaviour related to RCV1 can be
influenced by programming the polarity and on-chip delay
of RCV1. Active slope of RCV1 defines the vertical phase
and optionally the odd/even and colour frame phase to be
initialized, it can be also used to set the horizontal phase.
RGB processor
This block contains a dematrix in order to produce RED,
GREEN and BLUE signals to be fed to a SCART plug.
Before Y, Cb and Cr signals are de-matrixed, 2 times
oversampling for luminance and 4 times oversampling for
colour difference signals is performed. For transfer curves
of luminance and colour difference components of RGB
see Figs 11 and 12.
1996 Nov 07
If the horizontal phase is not to be influenced by RCV1, a
horizontal pulse needs to be supplied at the RCV2 pin
(or a horizontal synchronization from “CCIR 656” data
stream). Timing and trigger behaviour can also be
influenced for RCV2.
14
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
If there are missing pulses at RCV1 and/or RCV2, the time
base of ECO-DENC runs free, thus an arbitrary number of
synchronization slopes may miss, but no additional pulses
(with the incorrect phase) must occur.
I2C-bus interface
The I2C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write only,
except one readable status byte.
If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.
Two I2C-bus slave addresses are selected:
Alternatively, the device can be triggered by auxiliary
codes in a “CCIR 656” data stream at the MP port.
88H: LOW at pin SA
8CH: HIGH at pin SA.
In the master mode, the time base of the circuit
continuously runs free. On the RCV1 port, the IC can
output:
Input levels and formats
• A Vertical Sync signal (VS) with 3 or 2.5 lines duration,
or;
ECO-DENC expects digital Y, Cb, Cr data with levels
(digital codes) in accordance with “CCIR 601”.
• An ODD/EVEN signal which is LOW in odd fields, or;
For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated by
independent gain control setting, while gain for luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.
• A field sequence signal (FSEQ) which is HIGH in the first
of 4, 8 fields respectively.
On the RCV2 port, the IC can provide a horizontal pulse
with programmable start and stop phase; this pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.
For RGB (or Y, Cb and Cr) outputs fixed amplification in
accordance with “CCIR 601” is provided.
Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.
The polarity of both RCV1 and RCV2 is selectable by
software control.
TRANSFORMATION
Field length is in accordance with to 50 Hz or 60 Hz
standards, including non-interlaced options; start and end
of its active part can be programmed. The active part of a
field always starts at the beginning of a line, If the standard
blanking option SBLBN is not set.
R = Y + 1.3707 × (Cr − 128)
G = Y − 0.3365 × (Cb − 128) − 0.6982 × (Cr − 128)
B = Y + 1.7324 × (Cb − 128).
Representation of R, G and B at the output is 9 bits at
27 MHz.
Table 2
8-bit multiplexed format (similar to “CCIR 656” )
BITS
TIME
Sample
Luminance pixel number
Colour pixel number
1996 Nov 07
0
1
2
2
4
5
6
7
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
0
1
0
2
3
2
15
1996 Nov 07
16
6C
6D
6E
Trigger control
Trigger control
Multi control
Line 21 odd 1
6B
68
Line 21 odd 0
RCV port control
67
Subcarrier 3
69
66
Subcarrier 2
6A
65
Subcarrier 1
Line 21 even 1
64
Subcarrier 0
SBLBN
HTRIG10
HTRIG7
SRCV11
L21E17
L21E07
L21O17
L21O07
FSC31
FSC23
FSC15
FSC07
RTCE
DOWNB
0
0
GAINV8
GAINU8
GAINV7
GAINU7
CHPS7
0
0
CBENB
0
0
D7
0
HTRIG9
HTRIG6
SRCV10
L21E16
L21E06
L21O16
L21O06
FSC30
FSC22
FSC14
FSC06
BSTA6
DOWNA
0
0
DECTYP
0
GAINV6
GAINU6
CHPS6
0
0
0
0
0
D6
CHPS5
0
0
YC_EN
0
0
PHRES1
HTRIG8
HTRIG5
TRCV2
L21E15
L21E05
L21O15
L21O05
FSC29
FSC21
FSC13
FSC05
BSTA5
INPI
0
BLNVB5
BLNNL5
BLCKL5
GAINV5
GAINU5
↓
↓
D5
PHRES0
VTRIG4
HTRIG4
ORCV1
L21E14
L21E04
L21O14
L21O04
FSC28
FSC20
FSC12
FSC04
BSTA4
YGS
0
BLNVB4
BLNNL4
BLCKL4
GAINV4
GAINU4
CHPS4
0
0
SYMP
0
0
D4
0
VTRIG3
HTRIG3
PRCV1
L21E13
L21E03
L21O13
L21O03
FSC27
FSC19
FSC11
FSC03
BSTA3
0
0
BLNVB3
BLNNL3
BLCKL3
GAINV3
GAINU3
CHPS3
0
0
DEMOFF
0
0
D3
DATA BYTE(1)
0
VTRIG2
HTRIG2
CBLF
L21E12
L21E02
L21O12
L21O02
FSC26
FSC18
FSC10
FSC02
BSTA2
SCBW
0
BLNVB2
BLNNL2
BLCKL2
GAINV2
GAINU2
CHPS2
0
0
0
0
0
D2
FLC1
VTRIG1
HTRIG1
ORCV2
L21E11
L21E01
L21O11
L21O01
FSC25
FSC17
FSC09
FSC01
BSTA1
PAL
0
BLNVB1
BLNNL1
BLCKL1
GAINV1
GAINU1
CHPS1
0
0
Y2C
0
0
D1
FLCO
VTRIG0
HTRIG0
PRCV2
L21E10
L21E00
L21O10
L21O00
FSC24
FSC16
FSC08
FSC00
BSTA0
FISE
0
BLNVB0
BLNNL0
BLCKL0
GAINV0
GAINU0
CHPS0
0
0
UV2C
0
0
D0
Digital Video Encoder (ECO-DENC)
Line 21 even 0
62
63
RTC enable burst amplitude
61
Standard control
5E
Gain V MSB, blanking level,
decoder type
60
5D
Gain U MSB, black level
5F
5C
Gain V
Null
5B
Gain U
Blanking level VBI
59
42
Null
5A
3A
I/O port control
Chrominance phase
39
Null
Null
00
Null
SUB
ADDRESS
Slave receiver (slave address 88H or 8CH)
REGISTER FUNCTION
Table 3
Bit allocation map
Philips Semiconductors
Preliminary specification
SAA7124; SAA7125
1996 Nov 07
75
76
77
78
79
7A
7B
7C
Null
Null
Null
Null
Null
First active line
Last active line
MSBs vertical
17
CCEN1
D7
0
0
0
0
LAL7
FAL7
0
0
0
0
0
0
0
0
RCV2E7
RCV2S7
1. All bits marked 0 must be programmed to zero.
Note
7F
74
Null
Null
73
Null
7E
72
MSBs RCV2 output
Null
71
RCV2 output end
7D
70
Null
6F
RCV2 output start
SUB
ADDRESS
Closed caption
REGISTER FUNCTION
0
0
0
LAL8
LAL6
FAL6
0
0
0
0
0
0
0
RCV2E10
RCV2E6
RCV2S6
CCEN0
D6
0
0
0
0
LAL5
FAL5
0
0
0
0
0
0
0
RCV2E9
RCV2E5
RCV2S5
0
D5
0
0
0
FAL8
LAL4
FAL4
0
0
0
0
0
0
0
RCV2E8
RCV2E4
RCV2S4
SCCLN4
D4
0
0
0
0
LAL3
FAL3
0
0
0
0
0
0
0
0
RCV2E3
RCV2S3
SCCLN3
D3
DATA BYTE(1)
0
0
0
0
LAL2
FAL2
0
0
0
0
0
0
0
RCV2S10
RCV2E2
RCV2S2
SCCLN2
D2
0
0
0
0
LAL1
FAL1
0
0
0
0
0
0
0
RCV2S9
RCV2E1
RCV2S1
SCCLN1
D1
0
0
0
0
LAL0
FAL0
0
0
0
0
0
0
0
RCV2S8
RCV2E0
RCV2S0
SCCLN0
D0
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
I2C-bus format
I2C-bus address; see Table 5
Table 4
S
SLAVE ADDRESS
Table 5
ACK
SUBADDRESS
ACK
DATA 0
ACK
--------
DATA n
ACK
P
Explanation of Table 4
PART
DESCRIPTION
S
START condition
Slave address
1 0 0 0 1 0 0 X or 1 0 0 0 1 1 0 X (note 1)
ACK
acknowledge, generated by the slave
Subaddress (note 2)
subaddress byte
DATA
data byte
--------
continued data bytes and ACKs
P
STOP condition
Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read, no subaddressing with read.
2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.
Slave Receiver
Table 6
Subaddress 3A
DATA
BYTE
UV2C
Y2C
DEMOFF
SYMP
YC_EN
CBENB
1996 Nov 07
LOGIC
LEVEL
DESCRIPTION
0
Cb, Cr data are two’s complement.
1
Cb, Cr data are straight binary. Default after reset.
0
Y data is two’s complement.
1
Y data is straight binary. Default after reset.
0
Y, Cb and Cr for RGB dematrix is active. Default after reset.
1
Y, Cb and Cr for RGB dematrix is bypassed.
0
Horizontal and vertical trigger is taken from RCV2 and RCV1 respectively. Default after reset.
1
Horizontal and vertical trigger is decoded out of “CCIR 656” compatible data at MP port.
0
Output of CVBS and RGB signals. Default after reset.
1
Output of Y, C, and CVBS, CVBS signals.
0
Data from input ports is encoded. Default after reset.
1
Colour bar with fixed colours is encoded. The LUTs are read in upward order from
index 0 to index 7.
18
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
Table 7
Subaddress 5A
DATA BYTE
CHPS
Table 8
SAA7124; SAA7125
DESCRIPTION
VALUE
RESULT
phase of encoded colour
subcarrier (including burst)
relative to horizontal sync.
Can be adjusted in steps
of 360/256 degrees
tbf
PAL-B/G and data from input ports
tbf
PAL-B/G and data from look-up table
tbf
NTSC-M and data from input ports
tbf
NTSC-M and data from look-up table
Subaddress 5B and 5D
DATA BYTE
DESCRIPTION
CONDITIONS
REMARKS
variable gain for Cb signal; white-to-black = 92.5 IRE(1)
input representation
GAINU = 0
accordance with
GAINU = 118 (76H)
“CCIR 601”
white-to-black = 100 IRE(2)
GAINU
output subcarrier of U contribution = 0
output subcarrier of U contribution = nominal
GAINU = 0
output subcarrier of U contribution = 0
GAINU = 125 (7DH)
output subcarrier of U contribution = nominal
Notes
1. GAINU = −2.17 × nominal to +2.16 × nominal.
2. GAINU = −2.05 × nominal to +2.04 × nominal.
Table 9
Subaddress 5C and 5E
DATA BYTE
GAINV
DESCRIPTION
variable gain for Cr signal;
input representation
accordance with
“CCIR 601”
CONDITIONS
white-to-black = 92.5
GAINV = 0
output subcarrier of V contribution = 0
GAINV = 165 (A5H)
white-to-black = 100
output subcarrier of V contribution = nominal
IRE(2)
GAINV = 0
output subcarrier of V contribution = 0
GAINV = 175 (AFH)
output subcarrier of V contribution = nominal
Notes
1. GAINV = −1.55 × nominal to +1.55 × nominal.
2. GAINV = −1.46 × nominal to +1.46 × nominal.
1996 Nov 07
REMARKS
IRE(1)
19
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
Table 10 Subaddress 5D
DATA BYTE
BLCKL
DESCRIPTION
CONDITIONS
variable black level; input white-to-sync = 140 IRE(1)
representation accordance
BLCKL = 0
with “CCIR 601”
BLCKL = 63 (3FH)
white-to-sync = 143
REMARKS
output black level = 24 IRE
output black level = 49 IRE
IRE(2)
BLCKL = 0
output black level = 24 IRE
BLCKL = 63 (3FH)
output black level = 50 IRE
Notes
1. Output black level/IRE = BLCKL × 25/63 + 24; recommended value: BLCKL = 60 (3CH) normal.
2. Output black level/IRE = BLCKL × 26/63 + 24; recommended value: BLCKL = 45 (2DH) normal.
Table 11 Subaddress 5E
DATA BYTE
BLNNL
DESCRIPTION
variable blanking level
CONDITIONS
REMARKS
white-to-sync = 140 IRE(1)
BLNNL = 0
output blanking level = 17 IRE
BLNNL = 63 (3FH)
output blanking level = 42 IRE
white-to-sync = 143 IRE(2)
DECTYP
RTCI
BLNNL = 0
output blanking level = 17 IRE
BLNNL = 63 (3FH)
output blanking level = 43 IRE
logic 0
real time control input from SAA7151B
logic 1
real time control input from SAA7111
Notes
1. Output black level/IRE = BLNNL × 25/63 + 17; recommended value: BLNNL = 58 (3AH) normal.
2. Output black level/IRE = BLNNL × 26/63 + 17; recommended value: BLNNL = 63 (3FH) normal.
Table 12 Subaddress 5F
DATA BYTE
BLNVB
1996 Nov 07
DESCRIPTION
variable blanking level during vertical blanking interval is typically identical to value of BLNNL
20
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
Table 13 Subaddress 61
DATA BYTE
FISE
PAL
SCBW
YGS
INPI
DOWNA
DOWNB
LOGIC LEVEL
DESCRIPTION
0
864 total pixel clocks per line; default after reset
1
858 total pixel clocks per line
0
NTSC encoding (non-alternating V component)
1
PAL encoding (alternating V component); default after reset
0
enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 7 and 8)
1
standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 7 and 8); default after reset
0
luminance gain for white − black 100 IRE; default after reset
1
luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black
0
PAL switch phase is nominal; default after reset
1
PAL switch phase is inverted compared to nominal
0
DACs for G and B (Y and Cb or CVBS and CVBS) in normal operational mode;
default after reset
1
DACs for G and B (Y and Cb or CVBS and CVBS) forced to lowest output voltage
0
DACs for CVBS and R (CVBS and Cr or VBS and C) in normal operational mode;
default after reset
1
DACs for CVBS and R (CVBS and Cr or VBS and C) forced to lowest output
voltage
Table 14 Subaddress 62A
DATA BYTE
BSTA
DESCRIPTION
amplitude of colour burst;
input representation in
accordance with
“CCIR 601”
CONDITIONS
white-to-black = 92.5 IRE;
burst = 40 IRE; NTSC encoding
REMARKS
recommended value:
BSTA = 102 (66H
BSTA = 0 to 1.25 × nominal
white-to-black = 92.5 IRE;
burst = 40 IRE; PAL encoding
recommended value:
BSTA = 72 (48H)
BSTA = 0 to 1.76 × nominal
white-to-black = 100 IRE;
burst = 43 IRE; NTSC encoding
recommended value:
BSTA = 106 (6AH)
BSTA = 0 to 1.20 × nominal
white-to-black = 100 IRE;
burst = 43 IRE; PAL encoding
recommended value:
BSTA = 75 (4BH)
BSTA = 0 to 1.67 × nominal
Table 15 Subaddress 62B
DATA BYTE
RTCE
1996 Nov 07
LOGIC LEVEL
DESCRIPTION
0
no real time control of generated subcarrier frequency
1
real time control of generated subcarrier frequency through SAA7151B or SAA7111
(timing see Fig.15)
21
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
Table 16 Subaddress 63 to 66 (four bytes to program subcarrier frequency)
DATA BYTE
DESCRIPTION
FSC0 to FSC3 ffsc = subcarrier frequency
(in multiples of line
frequency);
fllc = clock frequency (in
multiples of line
frequency)
CONDITIONS
 f fsc
32 
FSC = round  -------- × 2 
 f llc

REMARKS
FSC3 = most significant byte
FSC0 = least significant byte
see note 1
Note
1. Examples:
a) NTSC-M: ffsc = 227.5, fllc = 1716 → FSC = 569408543 (21F07C1FH).
b) PAL-B/G: ffsc = 283.7516, fllc = 1728 → FSC = 705268427 (2A098ACBH).
Table 17 Subaddress 67 to 6A
DATA BYTE
DESCRIPTION
REMARK
L21O0
first byte of captioning data, odd field
L21O1
second byte of captioning data, odd field
L21E0
first byte of extended data, even field
L21E1
second byte of extended data, even field
1996 Nov 07
22
LSB of the respective bytes are encoded immediately
after run-in and framing code, the MSBs of the
respective bytes have to carry the parity bit, in
accordance with the definition of Line 21 encoding
format
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
Table 18 Subaddress 6B
DATA BYTE
LOGIC LEVEL
PRCV2
ORCV2
CBLF
DESCRIPTION
0
polarity of RCV2 as output is active HIGH, rising edge is taken when input,
respectively; default after reset
1
polarity of RCV2 as output is active LOW, falling edge is taken when input,
respectively
0
pin RCV2 is switched to input; default after reset
1
pin RCV2 is switched to output
0
if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference pulse
that is defined by RCV2S and RCV2E, also during vertical blanking Interval); default
after reset
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = HIGH); default after reset
1
if ORCV2 = HIGH, pin RCV2 provides a ‘Composite-Blanking-Not’ signal, this is a
reference pulse that is defined by RCV2S and RCV2E, excluding Vertical Blanking
Interval, which is defined by FAL and LAL
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization (if TRCV2 = HIGH) and as an internal blanking signal
PRCV1
ORCV1
TRCV2
SRCV1
0
polarity of RCV1 as output is active HIGH, rising edge is taken when input; default
after reset
1
polarity of RCV1 as output is active LOW, falling edge is taken when input
0
pin RCV1 is switched to input; default after reset
1
pin RCV1 is switched to output
0
horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from
decoded frame sync of “CCIR 656” input (at bit SYMP = HIGH); default after reset
1
horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)
−
defines signal type on pin RCV1; see Table 19
Table 19 Logic levels and function of SRCV1
DATA BYTE
AS OUTPUT
AS INPUT
0
VS
VS
vertical sync each field; default after reset
1
FS
FS
frame sync (odd/even)
1
0
FSEQ
FSEQ
1
1
not applicable
not applicable
SRCV11
SRCV10
0
0
1996 Nov 07
23
FUNCTION
field sequence, vertical sync every fourth field
(PAL = 0) or eighth field (PAL = 1)
−
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
Table 20 Subaddress 6C and 6D
DATA BYTE
DESCRIPTION
sets the horizontal trigger phase related to signal on RCV1 or RCV2 input (or to decoded “CCIR 656”
data)
HTRIG
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
increasing HTRIG decreases delays of all internally generated timing signals
reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV
used for triggering at HTRIG = tbfH (tbfH)
Table 21 Subaddress 6D
DATA BYTE
DESCRIPTION
sets the vertical trigger phase related to signal on RCV1 input (or to decoded “CCIR 656” data)
VTRIG
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines
variation range of VTRIG = 0 to 31 (1FH)
Table 22 Subaddress 6E
DATA BYTE
LOGIC LEVEL
SBLBN
DESCRIPTION
0
vertical blanking is defined by programming of FAL and LAL; default after reset
1
vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or “RS170A”
(60 Hz)
PHRES
−
selects the phase reset mode of the colour subcarrier generator; see Table 23
FLC
−
field length control; see Table 24
Table 23 Logic levels and function of PHRES
DATA BYTE
FUNCTION
PHRES1
PHRES0
0
0
no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset
0
1
reset every two lines
1
0
reset every eight fields
1
1
reset every four fields
Table 24 Logic levels and function of FLC
DATA BYTE
FUNCTION
FLC1
FLC0
0
0
interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
0
1
non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
1
0
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
1
1
non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
1996 Nov 07
24
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
Table 25 Subaddress 6F
DATA BYTE
DESCRIPTION
CCEN
enables individual Line 21 encoding; see Table 26
SCCLN
selects the actual line, where closed caption or extended data are encoded
line = (SCCLN + 4) for M-systems
line = (SCCLN + 1) for other systems
Table 26 Logic levels and function of CCEN
DATA BYTE
FUNCTION
CCEN1
CCEN0
0
0
line 21 encoding off
0
1
enables encoding in field 1 (odd)
1
0
enables encoding in field 2 (even)
1
1
enables encoding in both fields
Table 27 Subaddress 70 to 72
DATA BYTE
RCV2S
DESCRIPTION
start of output signal on RCV2 pin
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at
RCV2S = tbfH (tbfH)
RCV2E
end of output signal on RCV2 pin
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed
last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at
RCV2E = tbfH (tbfH)
Table 28 Subaddress 7A to 7C
DATA BYTE
FAL
DESCRIPTION
first active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines
FAL = 0 coincides with the first field synchronization pulse
LAL
last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines
LAL = 0 coincides with the first field synchronization pulse
SUBADDRESSES
In subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up.
1996 Nov 07
25
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
Slave Transmitter
Table 29 Slave transmitter (slave address 89H or 8DH)
REGISTER
FUNCTION
DATA BYTE
SUBADDRESS
−
Status byte
D7
D6
D5
VER2
VER1
VER0
D4
D3
D2
D1
D0
0
FSEQ
O_E
CCRDO CCRDE
Table 30 No subaddress
DATA BYTE
LOGIC LEVEL
DESCRIPTION
VER
−
Version identification of the device. It will be changed with all versions of the IC that
have different programming models. Current Version is 100 binary.
CCRDO
1
Closed caption bytes of the odd field have been encoded.
0
The bit is reset after information has been written to the subaddresses 67 and 68.
It is set immediately after the data has been encoded.
1
Closed caption bytes of the even field have been encoded.
0
The bit is reset after information has been written to the subaddresses 69 and 6A. It
is set immediately after the data has been encoded.
1
During first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields.
0
Not first field of a sequence.
1
During even field.
0
During odd field.
CCRDE
FSEQ
O_E
1996 Nov 07
26
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
MBE737
handbook, full
6 pagewidth
Gv
(dB)
0
−6
−12
−18
−24
(1)
(2)
−30
−36
−42
−48
−54
0
2
4
6
8
10
(1) SCBW = 1.
(2) SCBW = 0.
Fig.7 Chrominance transfer characteristic 1.
MBE735
handbook, halfpage
2
Gv
(dB)
0
(1)
(2)
−2
−4
−6
0
0.4
0.8
1.2 f (MHz) 1.6
(1) SCBW = 1.
(2) SCBW = 0.
Fig.8 Chrominance transfer characteristic 2.
1996 Nov 07
27
12
f (MHz)
14
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
MGG556
handbook, full
6 pagewidth
Gv
(dB)
0
(1)
−6
−12
−18
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
14
f (MHz)
(1) Total luminance of Y and CVBS.
Fig.9 Luminance transfer characteristic 1.
MBE736
handbook, halfpage
1
Gv
(dB)
(1)
0
−1
−2
−3
−4
−5
0
2
4
f (MHz)
6
(1) Detailed luminance of Y and CVBS.
Fig.10 Luminance transfer characteristic 2.
1996 Nov 07
28
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
MGB708
handbook, full pagewidth
Gv 6
(dB)
0
−6
−12
−18
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
12
f (MHz)
14
Fig.11 Luminance transfer characteristic in RGB.
MGB706
handbook, full pagewidth
Gv 6
(dB)
0
−6
−12
−18
−24
−30
−36
−42
−48
−54
0
2
4
6
8
10
Fig.12 Colour difference transfer characteristic in RGB.
1996 Nov 07
29
12
f (MHz)
14
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
CHARACTERISTICS
VDDD = 4.75 to 5.25 V; Tamb = 0 to +70 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Supplies
VDDA
analog supply voltage
4.75
5.25
V
VDDD
digital supply voltage
4.75
5.25
V
IDDA
analog supply current
note 1
−
60
mA
IDDD
digital supply current
note 1
−
100
mA
Inputs
VIL
LOW level input voltage
(except SDA, SCL, AP, SP and XTALI)
−0.5
+0.8
V
VIH
HIGH level input voltage
(except LLC, SDA, SCL, AP, SP and XTALI)
2.0
VDDD + 0.5
V
HIGH level input voltage (LLC)
2.4
VDDD + 0.5
V
ILI
input leakage current
−
1
µA
Ci
input capacitance
clocks
−
10
pF
data
−
8
pF
I/Os at high
impedance
−
8
pF
Outputs
VOL
LOW level output voltage
(except SDA and XTALO)
note 2
0
0.6
V
VOH
HIGH level output voltage
(except LLC, SDA, and XTALO)
note 2
2.4
VDDD + 0.5
V
HIGH level output voltage (LLC)
note 2
2.6
VDDD + 0.5
V
−0.5
+1.5
V
I2C-bus; SDA and SCL
VIL
LOW level input voltage
VIH
HIGH level input voltage
3.0
VDDD + 0.5
V
Ii
input current
Vi = LOW or HIGH
−10
+10
µA
VOL
LOW level output voltage (SDA)
IOL = 3 mA
−
0.4
V
Io
output current
during acknowledge
3
−
mA
Clock timing (LLC)
TLLC
cycle time
note 3
34
41
ns
δ
duty factor tHIGH/TLLC
note 4
40
60
%
tr
rise time
note 3
−
5
ns
tf
fall time
note 3
−
6
ns
Input timing
tSU;DAT
input data set-up time (any other except
CDIR, SCL, SDA, RESET, AP and SP)
6
−
ns
tHD;DAT
input data hold time (any other except
CDIR, SCL, SDA, RESET, AP and SP)
3
−
ns
1996 Nov 07
30
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SYMBOL
SAA7124; SAA7125
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Crystal oscillator
fn
nominal frequency (usually 27 MHz)
3rd harmonic
−
30
MHz
∆f/fn
permissible deviation of nominal frequency
note 5
−50
+50
10−6
CRYSTAL SPECIFICATION
Tamb
operating ambient temperature
0
70
°C
CL
load capacitance
8
−
pF
RS
series resistance
−
80
Ω
C1
motional capacitance (typical)
1.5 − 20%
1.5 + 20%
fF
C0
parallel capacitance (typical)
3.5 − 20%
3.5 + 20%
pF
Data and reference signal output timing
CL
output load capacitance
7.5
40
pF
th
output hold time
4
−
ns
td
output delay time
−
25
ns
1.9
2.1
V
18
35
Ω
CHROMA, Y, CVBS and RGB outputs
Vo(p-p)
output signal voltage (peak-to-peak value)
Rint
internal serial resistance
note 6
80
−
Ω
10
−
MHz
LF integral linearity error of DACs
−
±4
LSB
LF differential linearity error of DACs
−
±1
LSB
RL
output load resistance
B
output signal bandwidth of DACs
ILE
DLE
−3 dB
Notes
1. At maximum supply voltage with highly active input signals.
2. The levels have to be measured with load circuits of 1.2 kΩ to 3.0 V (standard TTL load) and CL = 25 pF.
3. The data is for both input and output direction.
4. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%.
5. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of
subcarrier frequency and line/field frequency.
6. For full digital range, without load, VDDA = 5.0 V. The typical voltage swing is 2.0 V, the typical minimum output
voltage (digital zero at DAC) is 0.2 V.
1996 Nov 07
31
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
handbook, full pagewidth
SAA7124; SAA7125
TLLC
tHIGH
2.6 V
1.5 V
0.6 V
LLC clock output
tHD; DAT
tf
tr
TLLC
tHIGH
2.4 V
1.5 V
0.8 V
LLC clock input
tSU; DAT
tHD; DAT
tf
tr
2.0 V
input data
valid
valid
not valid
0.8 V
td
tHD; DAT
2.4 V
output data
valid
valid
not valid
0.6 V
MBE742
Fig.13 Clock data timing.
handbook, full pagewidth
LLC
MP(n)
Cb(0)
Y(0)
Cr(0)
Y(1)
Cb(2)
RCV2
MGB699
The data demultiplexing phase is coupled to the internal horizontal phase.
The phase of the RCV2 signal is programmed to 0F2H (110H for 50 Hz) in this example in output mode (RCV2S).
Fig.14 Functional timing.
1996 Nov 07
32
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
sequence reserved (2)
5 bits bit (1) reset
reserved
bit (3)
handbook, full pagewidth
H/L transition
count start
LOW
128
13
4 bits
reserved
HPLL
increment
FSCPLL increment (4)
0
21
0
RTCI
time slot: 0 1
14
19
67 68
not used in
SAA7124/25
valid
sample
(1) Sequence bit:
PAL = logic 0 then (R − Y) line normal; PAL = logic 1 then (R − Y) line inverted.
NTSC = logic 0 then no change.
(2) Reserved bits: 235 with 50 Hz systems; 232 with 60 Hz systems.
(3) Only from SAA7111 decoder.
(4) SAAA7111 provides (22 : 0) bits, resulting in 3 reserved bits before sequence bit.
Fig.15 RTCI timing.
1996 Nov 07
33
invalid
sample
8/LLC
MGG557
1996 Nov 07
34
VDDD9 82
+5 V digital
0.1 µF
VDDD8 80
VDDD7 49
VDDD6 41
VDDD5 38
VDDD4 29
VDDD3 22
VDDD2 14
46
VDDDO
VDDA4
64
VSSA
0.1 µF
VSSA
3, 15, 24, 30, 39,
42, 51, 79, 81
VSSD1 to VSSD9
SAA7124
SAA7125
XTALO
45
(4)
VSSD
0.1 µF
+5 V digital
VDDA3
60
VSSA
Fig.16 Application environment of the ECO-DENC; PLCC84.
61
35 Ω(1) 55
35 Ω(1) 58
35
Ω(1)
35 Ω(1) 73
VDDA5
74
VSSA1
VDDA2
57
67
VDDA1
54
VSSA
VSSA
VSSA
VSSA
VrefL
CUR
63, 68
0.1 µF
0.1 µF
0.1 µF
0.1 µF
52, 76
DAC4
DAC3
DAC2
DAC1
VrefH
53, 75
0.1 µF
(1) Typical value. (2) For 100⁄100 colour bar. (3) Philips 12NC ordering code: 9922 520 30003. (4) V1 devices only.
VSSD
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
VDDD1 5
XTALI
44
3rd
harmonic
(3)
X1
27.0 MHz
10 pF
15 kΩ
MGG553
75 Ω
74 Ω
75 Ω
74 Ω
75 Ω
74 Ω
75 Ω
12 Ω
VSSA
BLUE
0.7 V (p-p)(2)
VSSA
GREEN
0.7 V (p-p)(2)
VSSA
RED
0.7 V (p-p)(2)
VSSA
CVBS
1.23 V (p-p)(2)
Digital Video Encoder (ECO-DENC)
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
0.1 µF
digital inputs
and outputs
1 nF
10 pF
+5 V analog
andbook, full pagewidth
10 µH
VSSD
Philips Semiconductors
Preliminary specification
SAA7124; SAA7125
APPLICATION INFORMATION
1996 Nov 07
35
VDDD9 60
VDDD8 54
VDDD7 52
VDDD6 30
VDDD5 24
VDDD4 22
VDDD3 13
VDDD2 7
VDDDO
28
VDDA4
41
VSSA
0.1 µF
VSSA
6, 8, 14, 23, 25,
51, 53, 58
VSSD1 to VSSD8
SAA7124
SAA7125
XTALO
27
VSSD
0.1 µF
+5 V digital
VDDA3
38
35
Ω(1)
VSSA
35
35 Ω(1) 37
35 Ω(1) 39
35 Ω(1) 45
VDDA5
46
42, 43
VDDA2
36
VSSA1
VDDA1
34
VSSA
VSSA
VSSA
VSSA
VrefL
CUR
40, 44
0.1 µF
0.1 µF
0.1 µF
32, 48
DAC4
DAC3
DAC2
DAC1
VrefH
33, 47
0.1 µF
0.1 µF
Fig.17 Application environment of the ECO-DENC; LQFP64 (V1 devices only).
(1) Typical value. (2) For 100⁄100 colour bar. (3) Philips 12NC ordering code: 9922 520 30003.
+5 V digital
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
VDDD1 5
XTALI
20
3rd
harmonic
(3)
X1
27.0 MHz
10 pF
15 kΩ
MGG554
75 Ω
74 Ω
75 Ω
74 Ω
75 Ω
74 Ω
75 Ω
12 Ω
VSSA
BLUE
0.7 V (p-p)(2)
VSSA
GREEN
0.7 V (p-p)(2)
VSSA
RED
0.7 V (p-p)(2)
VSSA
CVBS
1.23 V (p-p)(2)
Digital Video Encoder (ECO-DENC)
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
0.1 µF
digital inputs
and outputs
1 nF
10 pF
+5 V analog
dbook, full pagewidth
10 µH
VSSD
Philips Semiconductors
Preliminary specification
SAA7124; SAA7125
1996 Nov 07
36
VDDD9 76
VDDD8 70
VDDD7 68
VDDD6 37
VDDD5 30
VDDD4 28
VDDD3 19
VDDD2 13
VDDDO(4)
34
VDDA4
53
VSSA
0.1 µF
VSSA
6, 14, 20, 29, 31
39, 67, 69, 74
VSSD1 to VSSD8
SAA7124
SAA7125
XTALO
33
VSSD
0.1 µF
+5 V digital
VDDA3
49
35 Ω(1) 44
35 Ω(1) 47
35 Ω(1) 50
35 Ω(1) 61
VDDA5
62
VSSA
55
VDDA2
46
VSSA1
VDDA1
43
VSSA
VSSA
VSSA
VSSA
VrefL
CUR
52, 56
0.1 µF
0.1 µF
0.1 µF
0.1 µF
41, 64
DAC4
DAC3
DAC2
DAC1
VrefH
42, 63
0.1 µF
Fig.18 Application environment of the ECO-DENC; QFP80.
(1) Typical value. (2) For 100⁄100 colour bar. (3) Philips 12NC ordering code: 9922 520 30003. (4) V1 devices only.
+5 V digital
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
VDDD1 5
XTALI
32
3rd
harmonic
(3)
X1
27.0 MHz
10 pF
15 kΩ
MGG555
75 Ω
74 Ω
75 Ω
74 Ω
75 Ω
74 Ω
75 Ω
12 Ω
VSSA
BLUE
0.7 V (p-p)(2)
VSSA
GREEN
0.7 V (p-p)(2)
VSSA
RED
0.7 V (p-p)(2)
VSSA
CVBS
1.23 V (p-p)(2)
Digital Video Encoder (ECO-DENC)
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
0.1 µF
digital inputs
and outputs
1 nF
10 pF
+5 V analog
dbook, full pagewidth
10 µH
VSSD
Philips Semiconductors
Preliminary specification
SAA7124; SAA7125
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
PACKAGE OUTLINES
PLCC84: plastic leaded chip carrier; 84 leads
SOT189-2
eD
eE
y
X
74
A
54
53 Z E
75
bp
b1
w M
84
1
HE
E
pin 1 index
e
A
A4 A1
(A 3)
β
11
k1
33
Lp
k
detail X
12
32
e
v M A
ZD
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (millimetre dimensions are derived from the original inch dimensions)
UNIT
A
A1
min.
A3
A4
max.
bp
b1
mm
4.57
4.19
0.51
0.25
3.30
0.53
0.33
0.81
0.66
0.180
inches
0.020 0.01
0.165
D (1)
E (1)
e
eD
eE
HD
HE
k
29.41 29.41
28.70 28.70 30.35 30.35 1.22
1.27
29.21 29.21
27.69 27.69 30.10 30.10 1.07
k1
max.
Lp
v
w
y
0.51
1.44
1.02
0.18
0.18
0.10
Z D(1) Z E (1)
max. max.
2.16
β
2.16
45 o
1.130 1.130 1.195 1.195 0.048
0.057
0.021 0.032 1.158 1.158
0.020
0.05
0.007 0.007 0.004 0.085 0.085
0.13
1.090 1.090 1.185 1.185 0.042
0.040
0.013 0.026 1.150 1.150
Note
1. Plastic or metal protrusions of 0.01 inches maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
92-11-17
95-03-11
SOT189-2
1996 Nov 07
EUROPEAN
PROJECTION
37
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm
SOT314-2
c
y
X
A
48
33
49
32
ZE
e
Q
E HE
A
A2
(A 3)
A1
wM
θ
bp
pin 1 index
64
Lp
L
17
detail X
16
1
ZD
e
v M A
wM
bp
D
B
HD
v M B
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.60
0.20
0.05
1.45
1.35
0.25
0.27
0.17
0.18
0.12
10.1
9.9
10.1
9.9
0.5
HD
HE
12.15 12.15
11.85 11.85
L
Lp
Q
v
w
y
1.0
0.75
0.45
0.69
0.59
0.2
0.12
0.1
Z D (1) Z E (1)
θ
1.45
1.05
7
0o
1.45
1.05
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
94-01-07
95-12-19
SOT314-2
1996 Nov 07
EUROPEAN
PROJECTION
38
o
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
QFP80: plastic quad flat package; 80 leads (lead length 2.35 mm); body 14 x 20 x 2.8 mm
SOT318-3
c
y
X
64
A
41
65
40
ZE
e
Q
E HE
A
A2
(A 3)
A1
θ
wM
pin 1 index
Lp
bp
80
L
25
detail X
24
1
wM
bp
e
ZD
v M A
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HD
HE
L
Lp
Q
v
w
y
mm
3.25
0.30
0.10
2.90
2.65
0.25
0.45
0.30
0.25
0.14
20.1
19.9
14.1
13.9
0.8
25.0
24.4
19.0
18.4
2.35
1.4
1.0
1.4
1.2
0.2
0.2
0.1
Z D (1) Z E (1)
1.0
0.6
1.2
0.8
θ
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
95-02-04
95-04-25
SOT318-3
1996 Nov 07
EUROPEAN
PROJECTION
39
o
7
0o
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
• The longitudinal axis of the package footprint must be
parallel to the solder flow.
SOLDERING
Introduction
• The package footprint must incorporate solder thieves at
the downstream corners.
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
QFP
Wave soldering is not recommended for QFP packages.
This is because of the likelihood of solder bridging due to
closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “IC Package Databook” (order code 9398 652 90011).
If wave soldering cannot be avoided, the following
conditions must be observed:
Reflow soldering
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave)
soldering technique should be used.
Reflow soldering techniques are suitable for all PLCC and
QFP packages.
• The footprint must be at an angle of 45° to the board
direction and must incorporate solder thieves
downstream and at the side corners.
The choice of heating method may be influenced by larger
PLCC or QFP packages (44 leads, or more). If infrared or
vapour phase heating is used and the large packages are
not absolutely dry (less than 0.1% moisture content by
weight), vaporization of the small amount of moisture in
them can cause cracking of the plastic body. For more
information, refer to the Drypack chapter in our “Quality
Reference Handbook” (order code 9397 750 00192).
Even with these conditions, do not consider wave
soldering the following packages: QFP52 (SOT379-1),
QFP100 (SOT317-1), QFP100 (SOT317-2),
QFP100 (SOT382-1) or QFP160 (SOT322-1).
METHOD (PLCC AND QFP)
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method. Typical reflow temperatures range from
215 to 250 °C.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
Repairing soldered joints
Wave soldering
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
PLCC
Wave soldering techniques can be used for all PLCC
packages if the following conditions are observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
1996 Nov 07
40
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1996 Nov 07
41
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
NOTES
1996 Nov 07
42
Philips Semiconductors
Preliminary specification
Digital Video Encoder (ECO-DENC)
SAA7124; SAA7125
NOTES
1996 Nov 07
43
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Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1996
SCA52
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
657021/1200/01/pp44
Date of release: 1996 Nov 07
Document order number:
9397 750 01467