INTEGRATED CIRCUITS DATA SHEET SAA7120; SAA7121 Digital Video Encoder (ConDENC) Preliminary specification File under Integrated Circuits, IC22 1997 Jan 06 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 FEATURES • Monolithic CMOS 3.3 V (5 V) device • Digital PAL/NTSC encoder • System pixel frequency 13.5 MHz • Accepts MPEG decoded data on 8-bit wide input port; input data format Cb-Y-Cr (CCIR 656), SAV and EAV • Macrovision Pay-per-View copy protection system rev.7 and rev.6.1 as option. • Three DACs for Y, C and CVBS, two times oversampled with 10 bit resolution This applies to SAA7120 only. The device is protected by USA patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. Use of the Macrovision anti-copy process in the device is licensed for non-commercial home use only. Reverse engineering or disassembly is prohibited. Please contact your nearest Philips Semiconductors sales office for more information. • Real time control of subcarrier • Cross colour reduction filter • Closed captioning encoding and WST- and NABTS-Teletext encoding including sequencer and filter • Line 23 wide screen signalling encoding • Fast I2C-bus control port (400 kHz) • Encoder can be master or slave • QFP44 package. • Programmable horizontal and vertical input synchronization phase GENERAL DESCRIPTION • Programmable horizontal sync output phase The SAA7120; SAA7121 encodes digital YUV video data to an NTSC or PAL CVBS or S-Video signal. • Internal colour bar generator (CBG) • 2 × 2 bytes in lines 20 (NTSC) for copy guard management system can be loaded via I2C-bus The circuit accepts CCIR compatible YUV data with 720 active pixels per line in 4 : 2 : 2 multiplexed formats, for example MPEG decoded data. It includes a sync/clock generator and on-chip DACs. • Down-mode of DACs • Controlled rise/fall times of synchronization and blanking output signals QUICK REFERENCE DATA SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDA analog supply voltage 3.1 VDDD digital supply voltage 3.0 3.3 3.6 V IDDA analog supply current − − 62 mA IDDD digital supply current − − 38 mA Vi input signal voltage levels Vo(p-p) analog output signal voltages Y, C, and CVBS without load (peak-to-peak value) 1.2 1.35 1.45 V RL load resistance 75 − 300 Ω ILE LF integral linearity error − − ±3 LSB DLE LF differential linearity error − − ±1 LSB Tamb operating ambient temperature 0 − +70 °C 1997 Jan 06 3.3 3.5 V TTL compatible 2 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME SAA7120; SAA7121 DESCRIPTION QFP44 VERSION plastic quad flat package; 44 leads (lead length 2.35 mm); body 10 × 10 × 1.75 mm SOT307-2 BLOCK DIAGRAM VDDA1, handbook, full pagewidth RCV1 RCV2 RESET SDA SCL SA 40 42 41 21 DATA MANAGER CbCr C VDDD1, VSSD2, VDDD2, VSSD3 VDDD3 36 D 27 A 24 32, 33 CVBS Y C 1, 20, 22, 23, 26, 29 res. VSSA1 VSSA2 19 2 3 MBH787 RTCI SP Fig.1 Block diagram. 1997 Jan 06 25, 28, 31 I2C-bus control I2C-bus control VSSD1, VDDA4 30 OUTPUT INTERFACE ENCODER 6, 17, 39 VDDA3 Y 44 5, 18, 38 VDDA2, I2C-bus control I2C-bus control TTX XTALI 43 37 34 35 4 clock and timing Y 9 to 16 LLC SYNC CLOCK SAA7120 SAA7121 I2C-bus control XCLK 8 7 I2C-BUS INTERFACE MP7 to MP0 TTXRQ XTALO 3 AP Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 PINNING SYMBOL PIN I/O DESCRIPTION res. 1 − reserved SP 2 I test pin; connected to digital ground for normal operation AP 3 I test pin; connected to digital ground for normal operation LLC 4 I line-locked clock; this is the 27 MHz master clock for the encoder VSSD1 5 I digital ground 1 VDDD1 6 I digital supply voltage 1 RCV1 7 I/O raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal RCV2 8 I/O raster control 2 for video port; this pin provides an HS pulse of programmable length or receives an HS pulse MP7 9 I MP6 10 I MP5 11 I MP4 12 I MP3 13 I MP2 14 I MP1 15 I MP0 16 I VDDD2 17 I digital supply voltage 2 VSSD2 18 I digital ground 2 RTCI 19 I Real Time Control input; if the LLC clock is provided by an SAA7111 or SAA7151B, RTCI should be connected to pin RTCO of the decoder to improve the signal quality MPEG port; it is an input for “CCIR 656” style multiplexed Cb Y, Cr data res. 20 − reserved SA 21 I the I2C-bus slave address select input pin; LOW: slave address = 88H, HIGH = 8CH res. 22 − reserved res. 23 − reserved C 24 O analog output of the chrominance signal VDDA1 25 I analog supply voltage 1 for the C DAC res. 26 − reserved Y 27 O analog output of VBS signal VDDA2 28 I analog supply voltage 2 for the Y DAC res. 29 − reserved CVBS 30 O analog output of the CVBS signal VDDA3 31 I analog supply voltage 3 for the CVBS DAC VSSA1 32 I analog ground 1 for the DACs VSSA2 33 I analog ground 2 for the oscillator and reference voltage XTALO 34 O crystal oscillator output (to crystal) XTALI 35 I crystal oscillator input (from crystal); if the oscillator is not used, this pin should be connected to ground VDDA4 36 I analog supply voltage 4 for the oscillator and reference voltage XCLK 37 O clock output of the crystal oscillator 1997 Jan 06 4 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 I digital supply voltage 3 40 I reset input, active LOW; after reset is applied, all digital I/Os are in input mode; the I2C-bus receiver waits for the START condition SCL 41 I I2C-bus serial clock input SDA 42 I/O I2C-bus serial data input/output TTXRQ 43 O teletext request output, indicating when bit stream is valid TTX 44 I teletext bit stream input 44 TTX handbook, full pagewidth 34 XTALO 39 RESET 35 XTALI VDDD3 36 VDDA4 digital ground 3 37 XCLK I 38 VSSD3 38 39 VDDD3 VSSD3 40 RESET DESCRIPTION 41 SCL I/O 42 SDA PIN 43 TTXRQ SYMBOL res. 1 33 VSSA2 SP 2 32 VSSA1 AP 3 31 VDDA3 30 CVBS LLC 4 VSSD1 5 29 res. SAA7120 SAA7121 VDDD1 6 28 VDDA2 RCV1 7 27 Y RCV2 8 26 res. Fig.2 Pin configuration. 1997 Jan 06 5 res. 22 SA 21 res. 20 RTCI 19 VSSD2 18 VDDD2 17 23 res. MP0 16 MP5 11 MP1 15 24 C MP2 14 MP6 10 MP3 13 25 VDDA1 MP4 12 MP7 9 MBH790 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 be decoded optionally when the device is to operate in slave mode. FUNCTIONAL DESCRIPTION The digital video encoder (ConDENC) encodes digital luminance and colour difference signals simultaneously into analog CVBS and S-Video signals. NTSC-M, PAL B/G, and sub-standards are supported. It is also possible to connect a Philips Digital Video Decoder (SAA7111 or SAA7151B) to the ConDENC. Via pin RTCI, connected to RTCO of a decoder, information concerning the actual subcarrier, PAL-ID and (if used in conjunction with the SAA7111) the subcarrier phase can be inserted. Both interlaced and non-interlaced operation is possible for all standards. The basic encoder function consists of subcarrier generation, colour modulation and the insertion of synchronization signals. Luminance and chrominance signals are filtered in accordance with the standard requirements of “RS-170-A” and “CCIR 624”. The ConDENC synthesizes all necessary internal signals, colour subcarrier frequency and synchronization signals. Wide screen signalling data can be loaded via the I2C-bus. It is inserted into line 23 for 50 Hz field rate standards. For ease of analog post-filtering the signals are oversampled twice with respect to the pixel clock prior to digital-to-analog conversion. The IC contains closed caption and extended data services encoding (line 21), and supports anti-taping signal generation in accordance with Macrovision. The filter characteristics are shown in Figs 3 and 4. The DACs for Y, C, and CVBS have 10-bit resolution. Possibilities are provided for setting video parameters: Black and blanking level control The 8-bit multiplexed Cb-Y-Cr formats are “CCIR 656” (D1 format) compatible, but the SAV and EAV codes can Colour subcarrier frequency Variable burst amplitude. MGD672 6 Gv full pagewidth handbook, (dB) (4) 0 (2) (3) −6 (1) −12 −18 −24 −30 −36 −42 −48 −54 0 2 4 6 8 10 12 14 f (MHz) (1) CCRS1 = 0; CCRS0 = 1. (2) CCRS1 = 1; CCRS0 = 0. (3) CCRS1 = 0; CCRS0 = 0. (4) CCRS1 = 1; CCRS0 = 1. Fig.3 Luminance transfer characteristic 1. 1997 Jan 06 6 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 During reset (RESET = LOW) and after reset is released, all digital I/O stages are set to input mode. A reset forces the I2C-bus interface to abort a running bus transfer and sets register 3A to 03H, register 61 to 06H, registers 6BH and 6EH to 00H and bit TTX60 to 0. All other control registers are not influenced by a reset. MBE736 handbook, halfpage 1 Gv (dB) (1) 0 −1 Encoder VIDEO PATH −2 The encoder generates out of Y, U and V baseband signals luminance and colour subcarrier output signals, suitable for use as CVBS or separate Y and C signals. −3 Luminance is modified in gain and in offset (the latter programmable in a certain range to enable different black level set-ups). A fixed synchronization level in accordance with standard composite synchronization schemes is inserted. The inserted blanking level is programmable to allow for manipulations with Macrovision anti-taping. Additional insertion of AGC super-white pulses, programmable in height, is supported. −4 −5 0 2 4 f (MHz) 6 (1) CCRS1 = 0; CCRS0 = 0. Fig.4 Luminance transfer characteristic 2. MBE737 handbook, full 6 pagewidth Gv (dB) 0 −6 −12 −18 −24 (1) (2) −30 −36 −42 −48 −54 0 2 4 6 8 (1) SCBW = 1. (2) SCBW = 0. Fig.5 Chrominance transfer characteristic 1. 1997 Jan 06 7 10 12 f (MHz) 14 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 signal TTXRQ a single teletext bit has to be provided after a programmable delay at input pin. MBE735 handbook, halfpage 2 Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufficient small phase jitter on the output text lines. Gv (dB) 0 (1) TTXRQ provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines selectable independently for both fields. The internal insertion window for text is set to 360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS) teletext bits including clock run-in bits. For protocol and timing see Fig.7. (2) −2 −4 CLOSED CAPTION ENCODER −6 0 0.4 0.8 Using this circuit, data in accordance with the specification of closed caption or extended data service, delivered by the control interface, can be encoded (Line 21). Two dedicated pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code, are possible. 1.2 f (MHz) 1.6 (1) SCBW = 1. (2) SCBW = 0. Fig.6 Chrominance transfer characteristic 2. The actual line number where data is to be encoded in, can be modified in a certain range. Data clock frequency is in accordance with definition for NTSC-M standard 32 times horizontal line frequency. In order to enable easy analog post-filtering, luminance is interpolated from 13.5 MHz data rate to 27 MHz data rate, providing luminance in 10-bit resolution. This filter is also used to define smoothed transients for synchronization pulses and blanking period. For transfer characteristic of the luminance interpolation filter see Figs 3 and 4. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. It is also possible to encode Closed Caption Data for 50 Hz field frequencies at 32 times horizontal line frequency. Chrominance is modified in gain (programmable separately for U and V), standard dependent burst is inserted, before baseband colour signals are interpolated from 6.75 MHz data rate to 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher colour bandwidth, which can be made use of for Y and C output. For transfer characteristics of the chrominance interpolation filter see Figs 5 and 6. ANTI-TAPING (SAA7120 ONLY) For more information contact your nearest Philips Semiconductors sales office. Data manager In the data manager, real time arbitration on the data stream to be encoded is performed. The amplitude, beginning and ending of inserted burst is programmable in a certain range, suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier. The numeric ratio between Y and C outputs is in accordance with set standards. A pre-defined colour look-up table located in this block can be read out in a pre-defined sequence (8 steps per active video line), achieving a colour bar test pattern generator without the need for an external data source. The colour bar function is under software control only. TELETEXT INSERTION AND ENCODING Output interface/DACs Pin TTX receives a WST- or NABTS-Teletext bitstream sampled at the LLC clock. At each rising edge of output In the output interface encoded Y and C signals are converted from digital to analog in 10-bit resolution. 1997 Jan 06 8 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 Y and C signals are also combined to a 10-bit CVBS signal. On the RCV2 port, the device can provide a horizontal synchronization pulse with programmable start and stop phase; this pulse can be inhibited in the vertical blanking period to build up, for example, a composite blanking signal. The CVBS output occurs with the same processing delay as the Y and C outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by 15⁄16 with respect to Y and C DACs to make maximum use of conversion ranges. The polarity of both RCV1 and RCV2 is selectable by software control. Outputs of the DACs can be set together in two groups via software control to minimum output voltage for either purpose. The length of a field and the start and end of its active part can be programmed. The active part of a field always starts at the beginning of a line. Synchronization Teletext timing Synchronization of the ConDENC is able to operate in two modes; slave mode and master mode. The teletext timing is shown in Fig.7. tFD is the time needed to interpolate input data TTX and inserting it into the CVBS and Y output signal, such that it appears at tTTX = 10.2 µs (PAL) or tTTX = 10.5 µs (NTSC) after the leading edge of the horizontal synchronization pulse. In the slave mode, the circuit accepts synchronization pulses at the bidirectional RCV1 port. The timing and trigger behaviour related to RCV1 can be influenced by programming the polarity and the on-chip delay of RCV1. Active slope of RCV1 defines the vertical phase and optionally the odd/even and colour frame phase to be initialized, it can be also used to set the horizontal phase. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH-state at output pin TTXRQ, a new teletext bit must be provided by the source. If the horizontal phase is not to be influenced by RCV1, a horizontal synchronization pulse needs to be supplied at the pin RCV2. Timing and trigger behaviour can also be influenced by RCV2. Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS and TTXHD), the TTX data is always inserted at the correct position after the leading edge of outgoing horizontal synchronization pulse. If there are missing pulses at RCV1 and/or RCV2, the time base of ConDENC runs free, thus an arbitrary number of synchronization slopes may be absent, but no additional pulses (with the incorrect phase) must occur. Time tTTXWin is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbits/s (PAL), 296 teletext bits at a text data rate of 5.7272 Mbits/s (World Standard TTX) or 288 teletext bits at a text data rate of 5.7272 Mbits/s (NABTS). The insertion window is not opened if the control bit TTXEN is logic 0. If the vertical and horizontal phase is derived from RCV1, RCV2 can be used for horizontal or composite blanking input or output. Alternatively, the device can be triggered by auxiliary codes in a “CCIR 656” data stream at the MP port. In the master mode, the time base of the circuit continuously runs free. On the RCV1 port, the device can output: Using appropriate programming, all suitable lines of the odd field (TTXOVS and TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion. • A Vertical Synchronisation signal (VS) with 3 or 2.5 lines duration, or • An ODD/EVEN signal which is LOW in odd fields, or • A field sequence signal (FSEQ) which is HIGH in the first of 4 or 8 fields respectively. 1997 Jan 06 9 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 handbook, full pagewidth CVBS/Y tTTX textbit #: 1 tTTXWin 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TTX tPD tFD TTXRQ MBH788 Fig.7 Teletext timing. Analog output voltages Table 1 The analog output voltages are dependent on the open-loop voltage of the operational amplifiers for full-scale conversion (typical value 1.35 V), the internal series resistor (typical value 2 Ω), the external series resistor and the external load impedance. CONVERSION RANGE (peak-to-peak) (digits) The digital output signals in front of the DACs under nominal conditions occupy different conversion ranges, as indicated in Table 1 for a 100⁄100 colour bar signal. CVBS, SYNC TIP-TO-PEAK CARRIER Y (VBS) SYNC TIP-TO-WHITE 1016 881 Table 2 “CCIR 601” signal component levels SIGNALS COLOUR Values for the external series resistors result in a 75 Ω load. Input levels and formats The ConDENC expects digital Y, Cb, Cr data with levels (digital codes) in accordance with “CCIR 601” (see Tables 2 and 3). For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7.5 IRE set-up or without set-up. Reference levels are measured with a colour bar, 100% white, 100% amplitude and 100% saturation. 1997 Jan 06 Digital output signals conversion range 10 Y Cb Cr White 235 128 128 Yellow 210 16 146 Cyan 170 166 16 Green 145 54 34 Magenta 106 202 222 Red 81 90 240 Blue 41 240 110 Black 16 128 128 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 Tables 5 and 4 summarize the format of the I2C-bus addressing. For more information on how to use the I2C-bus see “The I2C-bus and how to use it”, order no. 9398 393 40011. Tables 7 to 42 contain the programming information for the subaddresses. Table 6 summarises this information. I2C-bus interface The I2C-bus interface is a standard slave transceiver, supporting 7-bit slave addresses and 400 kbits/s guaranteed transfer rate. It uses 8-bit subaddressing with an auto-increment function. All registers are write only, except one readable status byte. Two I2C-bus slave addresses are present: 88H: LOW at pin SA 8CH: HIGH at pin SA. Table 3 8-bit multiplexed format (similar to “CCIR 601” ) BITS Sample 0 1 2 2 4 5 6 7 Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Luminance pixel number 0 Colour pixel number Table 4 S 2 0 3 2 I2C-bus address format; see Table 5 SLAVE ADDRESS Table 5 1 ACK SUBADDRESS ACK DATA 0 ACK -------- DATA n Explanation of Table 4 PART DESCRIPTION S START condition Slave address 1 0 0 0 1 0 0 x or 1 0 0 0 1 1 0 x (1) ACK acknowledge, generated by the slave Subaddress(2) subaddress byte DATA data byte -------- continued data bytes and ACKs P STOP condition Notes 1. x is the read/write control bit; write: x = logic 0; read: x = logic 1, no subaddressing with read. 2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed. 1997 Jan 06 11 ACK P 1997 Jan 06 12 2B 2C 2D 2E 2F ⋅ Copy guard odd 0 Copy guard odd 1 Copy guard even 0 Copy guard even 1 Copy guard enable Null ⋅ 5B 5C 5D 5E 5F 60 61 62 63 64 65 Gain U Gain V Gain U MSB, Real time control, Black level Gain V MSB, Real time control, Blanking level CCR, Blanking level VBI Null Standard control RTC enable, Burst amplitude Subcarrier 0 Subcarrier 1 Subcarrier 2 5A 2A Burst end Chrominance phase 29 Real time control, Burst start 39 28 Wide screen signal 3A 27 Wide screen signal Input port control 26 Null Null ⋅ 25 ⋅ 00 Null SUB ADDRESS FSC23 FSC15 FSC07 RTCE 0 0 CCRS1 FSC22 FSC14 FSC06 BSTA6 DOWN 0 CCRS0 DECPH DECOE GAINV6 GAINU6 CHPS6 0 0 ⋅ 0 CGEN0 CGE16 CGE06 CGO16 CGO06 0 DECFIS 0 WSS6 0 ⋅ 0 D6 FSC21 FSC13 FSC05 BSTA5 INPI 0 BLNVB5 BLNNL5 BLCKL5 GAINV5 GAINU5 CHPS5 0 0 ⋅ 0 0 CGE15 CGE05 CGO15 CGO05 BE5 BS5 WSS13 WSS5 0 ⋅ 0 D5 FSC20 FSC12 FSC04 BSTA4 YGS 0 BLNVB4 BLNNL4 BLCKL4 GAINV4 GAINU4 CHPS4 SYMP 0 ⋅ 0 0 CGE14 CGE04 CGO14 CGO04 BE4 BS4 WSS12 WSS4 0 ⋅ 0 D4 FSC19 FSC11 FSC03 BSTA3 0 0 BLNVB3 BLNNL3 BLCKL3 GAINV3 GAINU3 CHPS3 0 0 ⋅ 0 0 CGE13 CGE03 CGO13 CGO03 BE3 BS3 WSS11 WSS3 0 ⋅ 0 D3 DATA BITS(1) FSC18 FSC10 FSC02 BSTA2 SCBW 0 BLNVB2 BLNNL2 BLCKL2 GAINV2 GAINU2 CHPS2 0 0 ⋅ 0 0 CGE12 CGE02 CGO12 CGO02 BE2 BS2 WSS10 WSS2 0 ⋅ 0 D2 FSC17 FSC09 FSC01 BSTA1 PAL 0 BLNVB1 BLNNL1 BLCKL1 GAINV1 GAINU1 CHPS1 Y2C 0 ⋅ 0 0 CGE11 CGE01 CGO11 CGO01 BE1 BS1 WSS9 WSS1 0 ⋅ 0 D1 FSC16 FSC08 FSC00 BSTA0 FISE 0 BLNVB0 BLNNL0 BLCKL0 GAINV0 GAINU0 CHPS0 UV2C 0 ⋅ 0 0 CGE10 CGE00 CGO10 CGO00 BE0 BS0 WSS8 WSS0 0 ⋅ 0 D0 Digital Video Encoder (ConDENC) GAINV8 GAINU8 GAINV7 GAINU7 CHPS7 CBENB 0 ⋅ 0 CGEN1 CGE17 CGE07 CGO17 CGO07 0 DECCOL WSSON WSS7 0 ⋅ 0 D7 Slave receiver (slave address 88H or 8CH) REGISTER FUNCTION Table 6 Philips Semiconductors Preliminary specification SAA7120; SAA7121 1997 Jan 06 13 7B 7C 7D 7E 7F Last active line MSB vertical Null Disable TTX line Disable TTX line LINE19 LINE11 0 LAL8 LAL6 FAL6 TTXEVE6 TTXEVS6 TTXOVE6 TTXOVS6 0 TTXHD6 TTXHS6 RCV2E10 RCV2E6 RCV2S6 CCEN0 0 HTRIG9 HTRIG6 SRCV10 L21E16 L21E06 L21O16 L21O06 FSC30 D6 LINE18 LINE10 0 0 LAL5 FAL5 TTXEVE5 TTXEVS5 TTXOVE5 TTXOVS5 0 TTXHD5 TTXHS5 RCV2E9 RCV2E5 RCV2S5 TTXEN PHRES1 HTRIG8 HTRIG5 TRCV2 L21E15 L21E05 L21O15 L21O05 FSC29 D5 1. All bits labelled ‘0’ are reserved. They must be programmed with logic 0. LINE20 LINE12 0 TTX60 LAL7 FAL7 TTXEVE7 TTXEVS7 TTXOVE7 TTXOVS7 0 TTXHD7 TTXHS7 0 RCV2E7 RCV2S7 CCEN1 SBLBN HTRIG10 HTRIG7 SRCV11 L21E17 L21E07 L21O17 L21O07 FSC31 D7 LINE17 LINE9 0 FAL8 LAL4 FAL4 TTXEVE4 TTXEVS4 TTXOVE4 TTXOVS4 0 TTXHD4 TTXHS4 RCV2E8 RCV2E4 RCV2S4 SCCLN4 PHRES0 VTRIG4 HTRIG4 ORCV1 L21E14 L21E04 L21O14 L21O04 FSC28 D4 LINE16 LINE8 0 TTXEVE8 LAL3 FAL3 TTXEVE3 TTXEVS3 TTXOVE3 TTXOVS3 0 TTXHD3 TTXHS3 0 RCV2E3 RCV2S3 SCCLN3 0 VTRIG3 HTRIG3 PRCV1 L21E13 L21E03 L21O13 L21O03 FSC27 D3 DATA BITS(1) LINE15 LINE7 0 TTXOVE8 LAL2 FAL2 TTXEVE2 TTXEVS2 TTXOVE2 TTXOVS2 VS_S2 TTXHD2 TTXHS2 RCV2S10 RCV2E2 RCV2S2 SCCLN2 0 VTRIG2 HTRIG2 CBLF L21E12 L21E02 L21O12 L21O02 FSC26 D2 LINE14 LINE6 0 TTXEVS8 LAL1 FAL1 TTXEVE1 TTXEVS1 TTXOVE1 TTXOVS1 VS_S1 TTXHD1 TTXHS1 RCV2S9 RCV2E1 RCV2S1 SCCLN1 FLC1 VTRIG1 HTRIG1 ORCV2 L21E11 L21E01 L21O11 L21O01 FSC25 D1 LINE13 LINE5 0 TTXOVS8 LAL0 FAL0 TTXEVE0 TTXEVS0 TTXOVE0 TTXOVS0 VS_S0 TTXHD0 TTXHS0 RCV2S8 RCV2E0 RCV2S0 SCCLN0 FLCO VTRIG0 HTRIG0 PRCV2 L21E10 L21E00 L21O10 L21O00 FSC24 D0 Digital Video Encoder (ConDENC) Note 79 7A 78 TTX even request V S First active line 77 TTX even request V E 76 72 MSBs RCV2 output TTX odd request V E 71 RCV2 output end TTX odd request V S 70 RCV2 output start 75 6F Closed caption, Teletext enable V-Sync shift 6E Multi control 74 6D Trigger control TTX request H delay 6C Trigger control 73 6B RCV port control TTX request H start 69 6A 68 Line 21 odd 1 Line 21 even 1 67 Line 21 even 0 66 Line 21 odd 0 SUB ADDRESS Subcarrier 3 REGISTER FUNCTION Philips Semiconductors Preliminary specification SAA7120; SAA7121 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 Slave Receiver Table 7 Subaddress 26 and 27 DATA BYTE LOGIC LEVEL − WSS DESCRIPTION wide screen signalling bits: 13 to 11 = reserved 10 to 8 = subtitles 7 to 4 = enhanced services 3 to 0 = aspect ratio WSSON Table 8 0 wide screen signalling output is disabled 1 wide screen signalling output is enabled Subaddress 28 and 29 DATA BYTE LOGIC LEVEL − BS DESCRIPTION REMARKS starting point of burst in clock cycles PAL : BS = 33 (21H) NTSC : BS = 25 (19H) BE − ending point of burst in clock cycles DECCOL 0 disable colour detection bit of RTCI input 1 enable colour detection bit of RTCI input 0 field sequence as FISE in subaddress 61 1 field sequence as FISE bit in RTCI input PAL : BS = 29 (1DH) NTSC : BS = 29 (1DH) DECFIS Table 9 bit RTCE must be set to 1 (see Fig.10) bit RTCE must be set to 1 (see Fig.10) Subaddress 2A to 2D DATA BYTE DESCRIPTION REMARKS CGO0 first byte of Copy guard data, odd field CGO1 second byte of Copy guard data, odd field CGE0 first byte of Copy guard data, even field CGE1 second byte of Copy guard data, even field LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of Line 20 encoding format. Table 10 Subaddress 2E DATA BYTE DESCRIPTION CCEN1 CCEN0 0 0 copy guard encoding off 0 1 enables encoding in field 1 (odd) 1 0 enables encoding in field 2 (even) 1 1 enables encoding in both fields 1997 Jan 06 14 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 Table 11 Subaddress 3A DATA BYTE UV2C Y2C SYMP CBENB LOGIC LEVEL DESCRIPTION 0 Cb, Cr data are two’s complement 1 Cb, Cr data are straight binary; default after reset 0 Y data is two’s complement 1 Y data is straight binary; default after reset 0 horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default after reset 1 horizontal and vertical trigger is decoded out of “CCIR 656” compatible data at MP port 0 data from input ports is encoded; default after reset 1 colour bar with fixed colours is encoded Table 12 Subaddress 5A DATA BYTE CHPS DESCRIPTION VALUE RESULT phase of encoded colour subcarrier (including burst) relative to horizontal sync; can be adjusted in steps of 360/256 degrees 3FH PAL-B/G and data from input ports 69H PAL-B/G and data from look-up table 67H NTSC-M and data from input ports 89H NTSC-M and data from look-up table Remark: in subaddresses 5B, 5C, 5D, 5E and 62 all IRE values are rounded up. Table 13 Subaddress 5B and 5D DATA BYTE GAINU DESCRIPTION variable gain for Cb signal; input representation accordance with “CCIR 601” CONDITIONS white-to-black = 92.5 IRE REMARKS GAINU = −2.17 × nominal to +2.16 × nominal GAINU = 0 output subcarrier of U contribution = 0 GAINU = 118 (76H) output subcarrier of U contribution = nominal white-to-black = 100 IRE GAINU = −2.05 × nominal to +2.04 × nominal GAINU = 0 output subcarrier of U contribution = 0 GAINU = 125 (7DH) output subcarrier of U contribution = nominal Table 14 Subaddress 5C and 5E DATA BYTE GAINV 1997 Jan 06 DESCRIPTION variable gain for Cr signal; input representation accordance with “CCIR 601” CONDITIONS white-to-black = 92.5 IRE REMARKS GAINV = −1.55 × nominal to +1.55 × nominal GAINV = 0 output subcarrier of V contribution = 0 GAINV = 165 (A5H) output subcarrier of V contribution = nominal white-to-black = 100 IRE GAINV = −1.46 × nominal to +1.46 × nominal GAINV = 0 output subcarrier of V contribution = 0 GAINV = 175 (AFH) output subcarrier of V contribution = nominal 15 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 Table 15 Subaddress 5D DATA BYTE BLCKL DECOE DESCRIPTION CONDITIONS REMARKS variable black level; input white-to-sync = 140 IRE(1) representation BLCKL = 0 accordance with BLCKL = 63 (3FH) “CCIR 601” white-to-sync = 143 IRE(2) real time control recommended value: BLCKL = 42 (2AH) output black level = 34 IRE output black level = 54 IRE recommended value: BLCKL = 35 (23H) BLCKL = 0 output black level = 32 IRE BLCKL = 63 (3FH) output black level = 52 IRE logic 0 disable odd/even field control bit from RTCI logic 1 enable odd/even field control bit from RTCI (see Fig.10) Notes 1. Output black level/IRE = BLCKL × 2/6.29 + 34.0 2. Output black level/IRE = BLCKL × 2/6.18 + 31.7 Table 16 Subaddress 5E DATA BYTE BLNNL DESCRIPTION variable blanking level CONDITIONS white-to-sync = 140 REMARKS IRE(1) BLNNL = 0 output blanking level = 25 IRE BLNNL = 63 (3FH) white-to-sync = 143 DECPH real time control recommended value: BLNNL = 46 (2EH) output blanking level = 45 IRE IRE(2) recommended value: BLNNL = 53 (35H) BLNNL = 0 output blanking level = 26 IRE BLNNL = 63 (3FH) output blanking level = 46 IRE logic 0 disable subcarrier phase reset bit from RTCI logic 1 enable subcarrier phase reset bit from RTCI (see Fig.10) Notes 1. Output black level/IRE = BLNNL × 2/6.29 + 25.4 2. Output black level/IRE = BLNNL × 2/6.18 + 25.9 Table 17 Subaddress 5F DATA BYTE DESCRIPTION BLNVB variable blanking level during vertical blanking interval is typically identical to value of BLNNL CCRS select cross colour reduction filter in luminance; see Table 18 Table 18 Logic levels and function of CCRS CCRS1 CCRS0 0 0 no cross colour reduction; for overall transfer characteristic of luminance see Fig.3 0 1 cross colour reduction #1 active; for overall transfer characteristic see Fig.3 1 0 cross colour reduction #2 active; for overall transfer characteristic see Fig.3 1 1 cross colour reduction #3 active; for overall transfer characteristic see Fig.3 1997 Jan 06 DESCRIPTION 16 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 Table 19 Subaddress 61 DATA BYTE FISE PAL SCBW YGS INPI DOWN LOGIC LEVEL DESCRIPTION 0 864 total pixel clocks per line; default after reset 1 858 total pixel clocks per line 0 NTSC encoding (non-alternating V component) 1 PAL encoding (alternating V component); default after reset 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4) 1 standard bandwidth for chrominance encoding (for overall transfer characteristic of chrominance in baseband representation see Figs 3 and 4); default after reset 0 luminance gain for white − black 100 IRE; default after reset 1 luminance gain for white − black 92.5 IRE including 7.5 IRE set-up of black 0 PAL switch phase is nominal; default after reset 1 PAL switch phase is inverted compared to nominal 0 DACs for CVBS, Y and C in normal operational mode; default after reset 1 DACs for CVBS, Y and C forced to lowest output voltage Table 20 Subaddress 62H DATA BYTE RTCE LOGIC LEVEL DESCRIPTION 0 no real time control of generated subcarrier frequency 1 real time control of generated subcarrier frequency through SAA7151B or SAA7111 (timing see Fig.10) Table 21 Subaddress 62H DATA BYTE BSTA DESCRIPTION amplitude of colour burst; input representation in accordance with “CCIR 601” CONDITIONS white-to-black = 92.5 IRE; burst = 40 IRE; NTSC encoding REMARKS recommended value: BSTA = 63 (3FH) BSTA = 0 to 2.02 × nominal white-to-black = 92.5 IRE; burst = 40 IRE; PAL encoding recommended value: BSTA = 45 (2DH) BSTA = 0 to 2.82 × nominal white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding recommended value: BSTA = 67 (43H) BSTA = 0 to 1.90 × nominal white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 3.02 × nominal 1997 Jan 06 17 recommended value: BSTA = 47 (2FH) Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 Table 22 Subaddress 63 to 66 (four bytes to program subcarrier frequency) DATA BYTE DESCRIPTION CONDITIONS FSC0 to FSC3 ffsc = subcarrier frequency (in f fsc 32 FSC = -------- × 2 , multiples of line frequency); f llc fllc = clock frequency (in multiples rounded up; see note 1 of line frequency) REMARKS FSC3 = most significant byte FSC0 = least significant byte Note 1. Examples: a) NTSC-M: ffsc = 227.5, fllc = 1716 → FSC = 569408543 (21F07C1FH). b) PAL-B/G: ffsc = 283.7516, fllc = 1728 → FSC = 705268427 (2A098ACBH). Table 23 Subaddress 67 to 6A DATA BYTE DESCRIPTION L21O0 first byte of captioning data, odd field L21O1 second byte of captioning data, odd field L21E0 first byte of extended data, even field L21E1 second byte of extended data, even field REMARKS LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of Line 21 encoding format. Table 24 Subaddress 6B DATA BYTE PRCV2 ORCV2 CBLF LOGIC LEVEL DESCRIPTION 0 polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively; default after reset 1 polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively 0 pin RCV2 is switched to input; default after reset 1 pin RCV2 is switched to output 0 if ORCV2 = HIGH, pin RCV2 provides an HREF signal (Horizontal Reference pulse that is defined by RCV2S and RCV2E, also during vertical blanking Interval); default after reset if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal synchronization only (if TRCV2 = 1); default after reset 1 if ORCV2 = HIGH, pin RCV2 provides a ‘Composite-Blanking-Not’ signal, for example a reference pulse that is defined by RCV2S and RCV2E, excluding Vertical Blanking Interval, which is defined by FAL and LAL if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal synchronization (if TRCV2 = 1) and as an internal blanking signal PRCV1 ORCV1 TRCV2 SRCV1 1997 Jan 06 0 polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after reset 1 polarity of RCV1 as output is active LOW, falling edge is taken when input 0 pin RCV1 is switched to input; default after reset 1 pin RCV1 is switched to output 0 horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded frame sync of “CCIR 656” input (at bit SYMP = HIGH); default after reset 1 horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW) − defines signal type on pin RCV1; see Table 25 18 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 Table 25 Logic levels and function of SRCV1 DATA BYTE AS OUTPUT AS INPUT VS VS SRCV11 SRCV10 0 0 0 1 FS FS 1 0 FSEQ FSEQ 1 1 not applicable FUNCTION vertical sync each field; default after reset frame sync (odd/even) field sequence, vertical sync every fourth field (PAL = 0) or eighth field (PAL = 1) not applicable − Table 26 Subaddress 6C and 6D DATA BYTE HTRIG DESCRIPTION sets the horizontal trigger phase related to signal on RCV1 or RCV2 input values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed increasing HTRIG decreases delays of all internally generated timing signals reference mark: analog output horizontal sync (leading slope) coincides with active edge of RCV used for triggering at HTRIG = 398H [398H] Table 27 Subaddress 6D DATA BYTE VTRIG DESCRIPTION sets the vertical trigger phase related to signal on RCV1 input increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines variation range of VTRIG = 0 to 31 (1FH) Table 28 Subaddress 6E DATA BYTE LOGIC LEVEL SBLBN 0 DESCRIPTION vertical blanking is defined by programming of FAL and LAL; default after reset 1 vertical blanking is forced in accordance with “CCIR 624” (50 Hz) or RS170A (60 Hz) PHRES − selects the phase reset mode of the colour subcarrier generator; see Table 29 FLC − field length control; see Table 30 Table 29 Logic levels and function of PHRES DATA BYTE DESCRIPTION PHRES1 PHRES0 0 0 no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset 0 1 reset every two lines 1 0 reset every eight fields 1 1 reset every four fields 1997 Jan 06 19 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 Table 30 Logic levels and function of FLC DATA BYTE DESCRIPTION FLC1 FLC0 0 0 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset 0 1 non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz 1 0 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz 1 1 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz Table 31 Subaddress 6F DATA BYTE LOGIC LEVEL − CCEN TTXEN SCCLN DESCRIPTION enables individual Line 21 encoding; see Table 32 0 disables teletext insertion 1 enables teletext insertion − selects the actual line, where closed caption or extended data are encoded line = (SCCLN + 4) for M-systems line = (SCCLN + 1) for other systems Table 32 Logic levels and function of CCEN DATA BYTE DESCRIPTION CCEN1 CCEN0 0 0 Line 21 encoding off 0 1 enables encoding in field 1 (odd) 1 0 enables encoding in field 2 (even) 1 1 enables encoding in both fields Table 33 Subaddress 70 to 72 DATA BYTE RCV2S DESCRIPTION start of output signal on pin RCV2 values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed first active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2S = 11AH [0FDH] RCV2E end of output signal on pin RCV2 values above 1715 (FISE = 1) or [1727 (FISE = 0)] are not allowed last active pixel at analog outputs (corresponding input pixel coinciding with RCV2) at RCV2E = 694H [687H] 1997 Jan 06 20 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 Table 34 Subaddress 73 and 74 DATA BYTE DESCRIPTION TTXHS start of signal on pin TTXRQ see Fig.7 TTXHD indicates the delay in clock cycles between rising edge of TTXRQ output and valid data on pin TTX minimum value has to be TTXHD = 2 Table 35 Subaddress 75 DATA BYTE VS_S DESCRIPTION Vertical Sync. shift between RCV1 and RCV2 (switched to output) in master mode it is possible to shift H-sync (RCV2; CBLF = 0) against V-sync (RCV1; SRCV1 = 00) standard value: VS_S = 3 Table 36 Subaddress 76, 77 and 7C DATA BYTE TTXOVS DESCRIPTION first line of occurrence of signal on pin TTXRQ in odd field line = (TTXOVS + 4) for M-systems line = (TTXOVS + 1) for other systems TTXOVE last line of occurrence of signal on pin TTXRQ in odd field line = (TTXOVE + 3) for M-systems line = TTXOVE for other systems Table 37 Subaddress 78, 79 and 7C DATA BYTE TTXEVS DESCRIPTION first line of occurrence of signal on pin TTXRQ in even field line = (TTXEVS + 4) for M-systems line = (TTXEVS + 1) for other systems TTXEVE last line of occurrence of signal on pin TTXRQ in even field line = (TTXEVE + 3) for M-systems line = TTXEVE for other systems Table 38 Subaddress 7C DATA BYTE TTX60 LOGIC LEVEL DESCRIPTION 0 enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset 1 enables World Standard Teletext 60 Hz (FISE = 1) Table 39 Subaddress 7A to 7C DATA BYTE DESCRIPTION FAL first active line = FAL + 4 for M-systems, = FAL + 1 for other systems, measured in lines FAL = 0 coincides with the first field synchronization pulse LAL last active line = LAL + 3 for M-systems, = LAL for other system, measured in lines LAL = 0 coincides with the first field synchronization pulse 1997 Jan 06 21 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 Table 40 Subaddress 7E and 7F DATA BYTE LINE DESCRIPTION individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective bits, disabled line = LINExx (50 Hz field rate) this bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE Slave Transmitter Table 41 Slave transmitter (slave address 89H or 8DH) REGISTER FUNCTION DATA BYTE SUBADDRESS − Status byte D7 D6 D5 D4 VER2 VER1 VER0 D3 CCRDO CCRDE D2 D1 D0 0 FSEQ O_E Table 42 No subaddress DATA BYTE LOGIC LEVEL DESCRIPTION VER − Version identification of the device. It will be changed with all versions of the device that have different programming models. Current version is 000 binary. CCRDO 1 Closed caption bytes of the odd field have been encoded. 0 The bit is reset after information has been written to the subaddresses 67 and 68. It is set immediately after the data has been encoded. 1 Closed caption bytes of the even field have been encoded. 0 The bit is reset after information has been written to the subaddresses 69 and 6A. It is set immediately after the data has been encoded. CCRDE FSEQ O_E 1997 Jan 06 1 During first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields). 0 Not first field of a sequence. 1 During even field. 0 During odd field. 22 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 CHARACTERISTICS VDDD = 3.0 to 3.6 V; Tamb = 0 to +70 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Supply VDDA analog supply voltage 3.1 3.5 V VDDD digital supply voltage 3.0 3.6 V IDDA analog supply current note 1 − 62 mA IDDD digital supply current note 1 − 38 mA Inputs VIL LOW level input voltage (except SDA, SCL, AP, SP and XTALI) −0.5 +0.8 V VIH HIGH level input voltage (except, SDA, SCL, AP, SP and XTALI) 2.0 VDDD + 0.3 V ILI input leakage current − 1 µA Ci input capacitance clocks − 10 pF data − 8 pF I/Os at high impedance − 8 pF Outputs VOL LOW level output voltage (except SDA and XTALO) IOL = 4 mA − 0.4 V VOH HIGH level output voltage (except, SDA, and XTALO) IOH = 4 mA VDDD − 4 − V I2C-bus; SDA and SCL VIL LOW level input voltage −0.5 VDDD + 0.3 V VIH HIGH level input voltage 2.3 VDDD + 0.3 V Ii input current Vi = LOW or HIGH −10 +10 µA VOL LOW level output voltage (SDA) IOL = 3 mA − 0.4 V Io output current during acknowledge 3 − mA note 2 34 41 ns Clock timing (LLC) TLLC cycle time δ duty factor tHIGH/tLLC note 3 40 60 % tr rise time note 2 − 5 ns tf fall time note 2 − 6 ns Input timing tSU;DAT input data set-up time (any pin except SCL, SDA, RESET, AP and SP) 6 − ns tHD;DAT input data hold time (any pin except SCL, SDA, RESET, AP and SP) 3 − ns 1997 Jan 06 23 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SYMBOL SAA7120; SAA7121 PARAMETER CONDITIONS MIN. MAX. UNIT Crystal oscillator fn nominal frequency (usually 27 MHz) 3rd harmonic − ∆f/fn permissible deviation of nominal frequency note 4 −50 × 10−6 +50 × 10−6 30 MHz CRYSTAL SPECIFICATION Tamb operating ambient temperature 0 70 °C CL load capacitance 8 − pF RS series resistance − 80 Ω C1 motional capacitance (typical) 1.5 − 20% 1.5 + 20% fF C0 parallel capacitance (typical) 3.5 − 20% 3.5 + 20% pF Data and reference signal output timing CL output load capacitance 7.5 40 pF th output hold time 4 − ns td output delay time − 25 ns 1.20 1.45 V Ω C, Y and CVBS outputs Vo(p-p) output signal voltage (peak-to-peak value) note 5 Rint internal serial resistance 1 3 RL output load resistance 75 300 Ω B−3dB output signal bandwidth of DACs 10 − MHz ILE LF integral linearity error of DACs − ±3 LSB DLE LF differential linearity error of DACs − ±1 LSB Notes 1. At maximum supply voltage with highly active input signals. 2. The data is for both input and output direction. 3. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%. 4. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency. 5. For full digital range, without load, VDDA = 3.3 V. The typical voltage swing is 1.35 V, the typical minimum output voltage (digital zero at DAC) is 0.2 V. 1997 Jan 06 24 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) handbook, full pagewidth SAA7120; SAA7121 TLLC tHIGH 2.6 V 1.5 V 0.6 V LLC clock output tHD; DAT tf tr TLLC tHIGH 2.4 V 1.5 V 0.8 V LLC clock input tSU; DAT tHD; DAT tf tr 2.0 V input data valid valid not valid 0.8 V td tHD; DAT 2.4 V output data valid valid not valid 0.6 V MBE742 Fig.8 Clock data timing. handbook, full pagewidth LLC MP(n) Cb(0) Y(0) Cr(0) Y(1) Cb(2) RCV2 MGB699 The data demultiplexing phase is coupled to the internal horizontal phase. The phase of the RCV2 signal is programmed to tbf (tbf for 50 Hz) in this example in output mode (RCV2S). Fig.9 Functional timing. 1997 Jan 06 25 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) handbook, full pagewidth H/L transition count start LOW 128 13 SAA7120; SAA7121 5 bits reserved (7) 4 bits reserved (7) (3) HPLL increment 0 (4) (2) FSCPLL increment (1) 21 (6) (5) 0 RTCI time slot: 0 1 14 19 67 69 72 74 68 valid sample not used in SAA7120/21 (1) SAA7111 provides (22:0) bits, resulting in 3 reserved bits before sequence bit. (2) Sequence bit PAL: 0 = (R−Y) line normal, 1 = (R−Y) line inverted NTSC: 0 = no change. (3) (4) (5) (6) (7) invalid sample 8/LLC MBH789 Reset bit: only from SAA7111 decoder. FISE bit: 0 = 50 Hz, 1 = 60 Hz. Odd/even bit: odd/even from external. Colour detection: 0 = no colour detected, 1 = colour detected. Reserved bits: 232 with 50 Hz systems, 229 with 60 Hz systems. Fig.10 RTCI timing. 6. If the colour detection bit is enabled (RTCE = 1; DECCOL = 1) and no colour was detected (colour detection bit = 0), the subcarrier frequency is generated by the ConDENC. In the other case (colour detection bit = 1) the subcarrier frequency is evaluated out of FSCPLL increment. Explanation of RTCI data bits 1. The ConDENC generates the subcarrier frequency out of the FSCPLL increment if enabled (see item 6.). 2. The PAL bit indicates the line with inverted R - Y component of colour difference signal. 3. If the reset bit is enabled (RTCE = 1; DECPH = 1; PHRES = 00), the phase of the subcarrier is reset in each line whenever the reset bit of RTCI input is set to 1. If the colour detection bit is disabled (RTCE = 1; DECCOL = 0), the subcarrier frequency is evaluated out of FSCPLL increment, independent of the colour detection bit of RTCI input. 4. If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the ConDENC takes this bit instead of the FISE bit in subaddress 61H. 5. If the odd/even bit is enabled (RTCE = 1; DECOE = 1), the ConDENC ignores its internally generated odd/even flag and takes the odd/even bit from RTCI input. 1997 Jan 06 26 1997 Jan 06 27 34 35 AGND DGND 6, 17, 39 use one capacitor for each VDDD 31 28 Fig.11 Application environment of ConDENC. AGND VSSA1, VSSA2 VSSD1, VSSD2, VSSD3 DGND 32, 33 5, 18, 38 2 Ω (1) DAC3 2 Ω (1) VDDA3 VDDA2 MBH786 24 27 30 AGND AGND AGND 2 Ω (1) 25 VDDA1 0.1 µF 0.1 µF 0.1 µF DAC2 DAC1 36 VDDA4 +3.3 V analog supply 0.1 µF VDDD1, VDDD2, VDDD3 0.1 µF SAA7120/21 XTALO 10 pF XTALI 3rd harmonic 27.0 MHz X1(3) 10 pF (1) Typical value. (2) For 100/100 colour bar. (3) Order no. 4312 065 02341. digital inputs and outputs 1 nF 0.1 µH +3.3 V digital supply C Y CVBS 75 Ω 10 Ω 75 Ω 10 Ω 75 Ω 4.7 Ω AGND 0.62 V (p-p)(2) UC AGND 1.00 V (p-p)(2) UY AGND 1.23 V (p-p)(2) UCVBS Digital Video Encoder (ConDENC) handbook, full pagewidth DGND Philips Semiconductors Preliminary specification SAA7120; SAA7121 APPLICATION INFORMATION Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 PACKAGE OUTLINE QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 c y X A 33 23 34 22 ZE e Q E HE A A2 wM (A 3) A1 θ bp Lp pin 1 index L 12 44 1 detail X 11 wM bp e ZD v M A D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 2.10 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 10.1 9.9 0.8 12.9 12.3 12.9 12.3 1.3 0.95 0.55 0.85 0.75 0.15 0.15 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 θ Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT307-2 1997 Jan 06 EUROPEAN PROJECTION 28 o 10 0o Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction • A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. • The footprint must be at an angle of 45° to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our “Quality Reference Handbook” (order code 9397 750 00192). Maximum permissible solder temperature is 260 °C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within 6 seconds. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 °C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 °C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1997 Jan 06 29 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 1997 Jan 06 30 Philips Semiconductors Preliminary specification Digital Video Encoder (ConDENC) SAA7120; SAA7121 NOTES 1997 Jan 06 31 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 657021/1200/01/pp32 Date of release: 1997 Jan 06 Document order number: 9397 750 01378