PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS PRELIMINARY - March 1, 2000 TEL:805-498-2111 FAX:805-498-3804 WEB:http://www.semtech.com DESCRIPTION The SC1154 is a synchronous-buck switch-mode controller designed for use in single ended power supply applications where efficiency is the primary concern. The controller is a hysteretic type, with a user selectable hysteresis. The SC1154 is ideal for implementing DC/DC converters needed to power advanced ® microprocessors such as Pentium ll, in both single and multiple processor configurations. Inhibit, undervoltage lockout and soft-start functions are included for controlled power-up. SC1154 features include an integrated 5 bit D/A converter, temperature compensated voltage reference, current limit comparator, over-current protection, and an adaptive deadtime circuit to prevent shoot-through of the power MOSFET during switching transitions. Power good signaling, logic compatible shutdown, and over-voltage protection are also provided. The integrated D/A converter provides programmability of output voltage from 2.0V to 3.5V in 100mV increments and 1.3V to 2.05V in 50mV increments with no external components. The SC1154 high side driver can be configured as either a grounded reference or as a floating bootstrap driver. High and low side drivers have a peak current rating of 2 amps. PIN CONFIGURATION SC1154 FEATURES • Programmable hysteresis • 5 bit DAC programmable output (1.3V-3.5V) • On-chip power good and OVP functions • Designed to meet latest Intel specifications • Up to 95% efficiency • +1% tolerance over temperature APPLICATIONS • Server Systems and Workstations • Pentium® II Core Supply • Multiple Microprocessor Supplies • Voltage Regulator Modules ORDERING INFORMATION (1) DEVICE SC1154CSW PACKAGE TEMP. RANGE (TJ) SO-28 0 - 125°C Note: (1) Add suffix ‘TR’ for tape and reel. SIMPLIFIED BLOCK DIAGRAM Top View (28-Pin SOIC) Pentium is a registered trademark of Intel Corporation © 2000 SEMTECH CORP. 1 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 ABSOLUTE MAXIMUM RATINGS Parameter Symbol Maximum Units VINMAX 14 V BOOT to DRVGND 25 V BOOT to BOOTLO 15 V -0.3 to +7.3 V +0.5V V LOHIB to AGND 14 V LOSENSE to AGND 14 V IOUTLO to AGND 14 V HISENSE to AGND 14 V VSENSE to AGND 5 V VIN12V Digital Inputs AGND to DRVGND Continuous Power Dissipation, TA = 25°C PD 1.2 W Continuous Power Dissipation, TC = 25°C PD 6.25 W Operating Junction Temperature TJ 0 to +125 °C Lead Temperature (Soldering) 10 seconds TL 300 °C TSTG -65 to 150 °C Storage Temperature 2 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 PIN DESCRIPTION Pin Pin Name Pin Function 1 IOUT Current Out. The output voltage on this pin is proportional to the load current as measured across the high side MOSFET, and is approximately equal to 2 x RDS(ON) x ILOAD. 2 DROOP Droop Voltage. This pin is used to set the amount of output voltage set-point droop as a function of load current. The voltage is set by a resistor divider between IOUT and AGND. 3 OCP 4 VHYST Hysteresis Set Pin. This pin is used to set the amount of hysteresis required by a resistor divider between VREFB and AGND. 5 VREFB Buffered Reference Voltage (from VID circuitry). 6 Over Current Protection. This pin is used to set the trip point for over current protection by a resistor divider between IOUT and AGND. VSENSE Output Voltage Sense. 7 AGND Small Signal Analog and Digital Ground. 8 SOFTST 9 NC 10 LODRV Low Drive Control. Connecting this pin to +5V enables normal operation. When LOHIB is grounded, this pin can be used to control LOWDR. 11 LOHIB Low Side Inhibit. This pin is used to eliminate shoot-thru current. Soft Start. Connecting a capacitor from this pin to AGND sets the time delay. Not connected 12 DRVGND Power Ground. 13 LOWDR 14 DRV 15 VIN12V 12V Supply. 16 BOOT Bootstrap. This pin is used to generate a floating drive for the high side FET driver. 17 HIGHDR 18 BOOTLO Bootstrap Low. In desktop applications, this pin connects to DRVGND. 19 HISENSE High Current Sense. Connected to the drain of the high side FET, or the input side of a current sense resistor between the input and the high side FET. 20 LOSENSE Low Current Sense. Connected to the source of the high side FET, or the FET side of a current sense resistor between the input and the high side FET. Low Side Driver Output. Drive Regulator for the MOSFET Drivers. High Side Driver Output. 21 IOUTLO This is the sampling capacitors bottom leg. Voltage on this pin is voltage on the LOSENSE pin when the high side FET is on. 22 INHIBIT Inhibit. If this pin is grounded, the MOSFET drivers are disabled. Usually connected to +5V through a pull-up resistor. 23 24 (1) Programming Input (MSB). (1) Programming Input. (1) Programming Input. (1) Programming Input. VID4 VID3 25 VID2 26 VID1 27 28 (1) Programming Input (LSB). VID0 PWRGD (1) Power Good. This open collector logic output is high if the output voltage is within 5% of the set point. 3 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 ELECTRICAL CHARACTERISTICS Unless specified: 0 < TJ < 125°C, VIN = 12V PARAMETER Supply Voltage Range SYMBOL CONDITIONS VIN12V Supply Current (Quiescent) IINq High Side Driver Supply Current (Quiescent) IBOOTq MIN TYP MAX UNITS 11.4 INH = 5V, VID not 11111, VIN above UVLO threshold during start-up, fSW = 200kHz, BOOTLO = 0V, CDH = CDL = 50pF 12 13 15 INH = 0V or VID = 11111 or VIN below UVLO threshold during start-up, BOOT = 13V, BOOTLO = 0V mA 10 INH = 5V, VID not 11111, VIN above UVLO threshold during start-up, fSW = 200kHz, BOOT = 13V, BOOTLO = 0V, CDH = 50pF V 5 µA mA REFERENCE/VOLTAGE IDENTIFICATION Reference Voltage Accuracy VREF VID0 - VID4 High Threshold Voltage VTH(H) VID0 - VID4 Low Threshold Voltage VTH(L) 11.4V < VIN12V < 12.6V, over full VID range (see Output Voltage Table) -1 1 2.25 % V 1 V 95 % VREF POWER GOOD Undervoltage Threshold Output Saturation Voltage Hysteresis 90 VTH(PWRGD) VSAT IO = 5mA VHYS(PWRGD) 0.5 V 10 mV OVER VOLTAGE PROTECTION OVP Trip Point Hysteresis (1) VOVP VHYS(OVP) 12 15 10 20 %VREF mV 4 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 ELECTRICAL CHARACTERISTICS (cont.) Unless specified: 0 < TJ < 125°C, VIN = 12V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10.4 13 15.6 µA SOFT START Charge Current Discharge Current ICHG Idischg VSS = 0.5V, resistance from VREFB pin to AGND = 20kΩ, VREFB = 1.3V Note: ICHG = (IVREFB / 5) V(S/S) = 1V 1 mA INHIBIT COMPARATOR VstartINH 1 2.0 2.4 V Start Threshold VstartUVLO 9.25 10 10.75 V Hysteresis VhysUVLO 1.8 2 2.2 V 5 mV Start Threshold VIN12V UVLO HYSTERETIC COMPARATOR VDROOP pin grounded Input Offset Voltage VosHYSCMP Input Bias Current IbiasHYSCMP 1 µA Hysteresis Accuracy VHYS_ACC 7 mV Hysteresis Setting VHYS_SET 60 mV 5 mV 0.11 V 100 nA DROOP COMPENSATION Initial Accuracy VDROOP_ACC VDROOP = 50mV OVERCURRENT PROTECTION OCP Trip Point Input Bias Current 0.09 VOCP 0.1 IbiasOCP HIGH-SIDE VDS SENSING Gain Initial Accuracy IOUT Source IOUT Sink Current Output Voltage Swing 2 VIOUT_ACC VHISENSE = 12V, VIOUTLO = 11.9V IsourceIOUT VIOUT = 0.5V, VHISENSE = 12V, VIOUTLO = 11.5V IsinkIOUT V/V 6 500 VIOUT = 0.05V, VHISENSE = 12V, VIOUTLO = 12V 40 VHISENSE = 11V, RIOUT = 10k0hm 0 mV µA 50 µA 3.75 V 5 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 ELECTRICAL CHARACTERISTICS (cont.) Unless specified: 0 < TJ < 125°C, VIN12V = 12V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS HIGH-SIDE VDS SENSING (cont.) VHISENSE = 4.5V, RIOUT = 10kOhm 0 2.0 V VHISENSE = 3V, RIOUT = 10kOhm 0 1.0 V LOSENSE High Level Input Voltage VihLOSENSE VHISENSE = 4.5V (Note 1) LOSENSE Low Level Input Voltage VilLOSENSE VHISENSE = 4.5V (Note 1) Sample/Hold Resistance RS/H 4.5V < = 13V 2.85 50 V 65 1.8 V 80 Ω BUFFERED REFERENCE VREFB Load Regulation VldregREFB 10µA < IREFB < 500µA 2 mV DEADTIME CIRCUIT LOHIB High Level Voltage VihLOHIB LOHIB Low Level Input Voltage VilLOHIB 2 V 1.0 LOWDR High Level Input Voltage VihLOWDR (Note 1) LOWDR Low Level Input Voltage VilLOWDR (Note 1) 2 V V 1.0 V 9 V DRIVE REGULATOR Output Voltage VDRV Load Regulation VldregDRV Short Circuit Current IshortDRV 11.4 < VIN12V < 12.6V, IDRV = 50mA 7 1mA < IDRV < 50mA 100 100 mV mA HIGH-SIDE OUTPUT DRIVER Peak Output Current IsrcHIGHDR’ duty cycle < 2%, tpw < 100us, IsinkHIGHDR TJ = 125°C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 1.5V (src), or VHIGHDR = 5V (sink) (Note 1) 2 A 6 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 ELECTRICAL CHARACTERISTICS (cont.) Unless specified: 0 < TJ < 125°C, VIN12V = 12V PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS HIGH-SIDE OUTPUT DRIVER (cont.) Output Resistance RsrcHIGHDR’ TJ = 125°C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 6V 45 RsinkHIGHDR TJ = 125°C VBOOT - VBOOTLO = 6.5V, VHIGHDR = 0.5V 5 Ω LOW-SIDE OUTPUT DRIVER Peak Outout Current Output Resistance IsrcLOWDR’ IsinkLOWDR duty cycle < 2%, tpw < 100us, TJ = 125°C VDRV = 6.5V, VLOWDR = 1.5V (src), or VLOWDR = 5V (sink) (Note 1) 2 A RsrcLOWDR’ TJ = 125°C VDRV = 6.5V, VLOWDR = 6V 45 RsinkLOWDR TJ = 125°C VDRV = 6.5V, VLOWDR = 0.5V 5 Ω (1) HYSTERETIC COMPARATORS Propagation Delay Time from VSENSE to HIGHDR or LOWDR (excluding deadtime) tHCPROP 150 10mV overdrive, 1.3V < Vref < 3.5V 250 ns OUTPUT DRIVERS HIGHDR rise/fall time trHIGHDR ,tfHIGHDR Cl = 9nF, VBOOT = 6.5v, VBOOTLO = grounded, TJ = 125 °C 60 ns LOWDR rise/fall time trLOWDR , tfLOWDR Cl = 9nF, VDRV = 6.5v, TJ = 125 °C 60 ns (1) OVERCURRENT PROTECTION Comparator Propagation Delay Time tOCPROP Deglitch Time tOCDGL 1 1 µs 3 µs OVERVOLTAGE PROTECTION Comparator Propagation Delay Time tOVPROP Deglitch Time tOVDGL 1 1 µs 3 µs 7 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 ELECTRICAL CHARACTERISTICS (cont.) Unless specified: 0 < TJ < 125° C, VIN12V = 12V PARAMETER HIGH-SIDE Vds SENSING SYMBOL CONDITIONS MIN TYP MAX UNITS VHISENSE = 12v, VIOUTLO pulsed from 12v to 11.9v, 100ns rise and fall times 2 µs VHISENSE = 4.5v, VIOUTLO pulsed from 4.5v to 4.4v, 100ns rise and fall times 3 µs VHISENSE = 3v, VIOUTLO pulsed from 3.0v to 2.9v, 100ns rise and fall times 3 µs (1) Response Time tVDSRESP Short Circuit Protection Rising Edge Delay tVDSRED LOSENSE grounded 300 500 ns Sample/Hold Switch turnon/turn-off Delay tSWXDLY 3v < VHISENSE < 11v VLOSENSE = VHISENSE 30 100 ns POWER GOOD Comparator Propagation Delay tPWRGD 1 µs SOFTSTART Comparator Propagation Delay tSLST overdrive = 10mv 560 900 ns 100 ns DEADTIME Driver Nonoverlap Time tNUL 30 Note 1: Guaranteed, but not tested 8 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 © 2000 SEMTECH CORP. - 100mV VSENSE + + DEGLITCH OCP - DEGLITCH 0.93VREF + 1.15VREF - PWRGD Q Vcc + AGND 10V - UVLO S R + INHIBIT 2V - INH BANDGAP FAULT 50uA IOUT - + DECODE 11111 G=2 + + - - VID DAC - + - VSENSE FILTER FILTER 0.93VREF - + - + - + - + VHYST VREFB HIGHDR LOSENSE DROOP VREF + 1.15VREF SHUTDOWN IOUTLO VID0 VID2 VID4 VID1 VID3 HISENSE + - I(VREFB) / 5 VREF RISING EDGE DELAY LOHIB ANALOG BIAS SOFTST FILTER PREREG LODRV LOWDR REGULATOR DRIVE Vcc DRVGND LOWDR BOOTLO HIGHDR BOOT DRV VIN12V PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 BLOCK DIAGRAM 9 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 OUTPUT VOLTAGE TABLE 0 = GND; 1 = Floating or +5V pull-up VID4 VID3 VID2 VID1 VID0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 VDC (V) 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05 NO CPU 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.30 3.40 3.50 NOTE: (1) If the VID bits are set to 11111, then the high-side and the low-side driver outputs will be set low, and the controller will be set to a low-Iq state. 10 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 FUNCTIONAL DESCRIPTION Reference/Voltage Identification The reference/voltage identification (VID) section consists of a temperature compensated bandgap reference and a 5-bit voltage selection network. The 5 VID pins are TTL compatable inputs to the VID selection network. They are internally pulled up to +5V generated from the +12V supply by a resistor divider, and provide programmability of output voltage from 2.0V to 3.5V in 100mV increments and 1.3V to 2.05V in 50mV increments. Refer to the Output Voltage Table for the VID code settings. The output voltage of the VID network, VREF is within 1% of the nominal setting over the full input and output voltage range and junction temperature range. The output of the reference/VID network is indirectly brought out through a buffer to the REFB pin. The voltage on this pin will be within 3mV of VREF. It is not recommended to drive loads with REFB other than setting the hysteresis of the hysteretic comparator, because the current drawn from REFB sets the charging current for the soft start capacitor. Refer to the soft start section for additional information. Hysteretic Comparator The hysteretic comparator regulates the output voltage of the synchronous-buck converter. The hysteresis is set by connecting the center point of a resistor divider from REFB to AGND to the HYST pin. The hysteresis of the comparator will be equal to twice the voltage difference between REFB and HYST, and has a maximum value of 60mV. The maximum propagation delay from the comparator inputs to the driver outputs is 250ns. Low Side Driver The low side driver is designed to drive a low RDS(ON) Nchannel MOSFET, and is rated for 2 amps source and sink. The bias for the low side driver is provided internally from VDRV. High Side Driver The high side driver is designed to drive a low RDS(ON) N-channel MOSFET, and is rated for 2 amps source and sink. It can be configured either as a ground referenced driver or as a floating bootstrap driver. When configured as a floating driver, the bias voltage to the driver is developed from the DRV regulator. The inter- nal bootstrap diode, connected between the DRV and BOOT pins, is a Schottky for improved drive efficiency. The maximum voltage that can be applied between the BOOT pin and ground is 25V. The driver can be referenced to ground by connecting BOOTLO to PGND, and connecting +12V to the BOOT pin. Deadtime Control Deadtime control prevents shoot-through current from flowing through the main power FETs during switching transitions by actively controlling the turn-on times of the FET drivers. The high side driver is not allowed to turn on until the gate drive voltage to the low-side FET is below 2 volts, and the low side driver is not allowed to turn on until the voltage at the junction of the 2 FETs (VPHASE) is below 2 volts. An internal low-pass filter with an 11MHz pole is located between the output of the low-side driver (DL) and the input of the deadtime circuit that controls the high-side driver, to filter out noise that could appear on DL when the high-side driver turns on. Current Sensing Current sensing is achieved by sampling and holding the voltage across the high side FET while it is turned on. The sampling network consists of an internal 50Ω switch and an external 0.1µF hold capacitor. Internal logic controls the turn-on and turn-off of the sample/ hold switch such that the switch does not turn on until VPHASE transitions high and turns off when the input to the high side driver goes low. Thus sampling will occur only when the high side FET is conducting current. The voltage at the IO pin equals 2 times the sensed voltage. In applications where a higher accuracy in current sensing is required, a sense resistor can be placed in series with the high side FET and the voltage across the sense resistor can be sampled by the current sensing circuit. Droop Compensation The droop compensation network reduces the load transient overshoot/undershoot at VOUT, relative to VREF. VOUT is programmed to a voltage greater than VREF (equal to VREF x (1+R5/R6)) by an external resistor divider from VOUT to the VSENSE pin to reduce the undershoot on VOUT during a low to high load current transient. The overshoot during a high to low load current transient is reduced by subtracting the voltage that is on the DROOP pin from VREF. The voltage on the IO pin is divided down with an external 11 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 FUNCTIONAL DESCRIPTION (cont.) resistor divider, and connected to the DROOP pin. Thus, under loaded conditions, VOUT is regulated to Vout = Vref • (1+R7/R8) - IOUT • R2/(R1+R2). Inhibit The inhibit pin is a TTL compatible digital pin that is used to enable the controller. When INH is low, the output drivers are low, the soft start capacitor is discharged, the soft start current source is disabled, and the controller is in a low IQ state. When INH goes high, the short across the soft start capacitor is removed, the soft start current source is enabled, and normal converter operation begins. When the system logic supply is connected to INH, it controls power sequencing by locking out controller operation until the system logic supply exceeds the input threshold voltage of the INH circuit; thus the +12V supply and the system logic supply (either +5V or 3.3V) must be above UVLO thresholds before the controller is allowed to start up. VIN The VIN undervoltage lockout circuit disables the controller while the +12V supply is below the 10V start threshold during power-up. While the controller is disabled, the output drivers will be low, the soft start capacitor will be shorted and the soft start current is disabled and the controller will be in a low IQ state. When VIN exceeds the start threshold, the short across the soft start capacitor is removed, the soft start current source is enabled and normal converter operation begins. There is a 2V hysteresis in the undervoltage lockout circuit for noise immunity. Soft Start The soft start circuit controls the rate at which VOUT powers up. A capacitor is connected between SS and AGND and is charged by an internal current source. The value of the current source is proportional to the reference voltage so the charging rate of CSS is also proportional to the reference voltage. By making the charging current proportional to VREF, the power-up time for VOUT will be independent of VREF. Thus, CSS can remain the same value for all VID settings. The soft start charging current is determined by the following equation: ISS = IREFB/5. Where IREFB is the current flowing out of the REFB pin. It is recommended that no additional loads be connected to REFB, other than the resistor divider for setting the hysteresis voltage. Thus these resistor values will determine the soft start charging current. The maximum current that can be sourced by REFB is 500µA. Power Good The power good circuit monitors for an undervoltage condition on VOUT. If VSENSE is 7% (nominal) below VREF, then the power good pin is pulled low. The PWRGD pin is an open drain output. Overvoltage Protection The overvoltage protection circuit monitors VOUT for an overvoltage condition. If VSENSE is 15% above VREF, than a fault latch is set and both output drivers are turned off. The latch will remain set until VIN goes below the undervoltage lockout value. A 1ms deglitch timer is included for noise immunity. Overcurrent Protection The overcurrent protection circuit monitors the current through the high side FET. The overcurrent threshold is adjustable with an external resistor divider between IO and AGND, with the divider voltage connected to the OCP pin. If the voltage on the OCP pin exceeds 100mV, then a fault latch is set and the output drivers are turned off. The latch will remain set until VIN goes below the undervoltage lockout value. A 1ms deglitch timer is included for noise immunity. The OCP circuit is also designed to protect the high side FET against a short-to-ground fault on the terminal common to both power FETs (VPHASE). Drive Regulator The drive regulator provides drive voltage to the low side driver, and to the high side driver when the high side driver is configured as a floating driver. The minimum drive voltage is 7V. The minimum short circuit current is 100mA. 12 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 C2 0.01 © 2000 SEMTECH CORP. R4 1k R2 1k C4 0.01 R3 2.7k R1 2k C7 0.1 C3 0.01 0.001 C5 C8 0.01 Dopt. MBR0530 pin18 R6 20k R5 100 R8 10k R7 150 +5V C6 0.1 DRV LowDr DrvGnd Lohib Lodrv Bias Slowst AnaGnd Vsense Vrefb Vhyst OCP Droop Iout C8 2.2uF 16V 14 13 12 11 10 9 8 7 6 5 4 3 2 1 U1 SC1154 Vin12 Boot HiDr BootLo Hisense Losense Ioutlo Inhibit VID4 VID3 VID2 VID1 VID0 PwrGd 15 16 17 18 19 20 21 22 23 24 25 26 27 28 C9 2.2uF 16V Q2 IRL2203S +12V Q1 IRL3103S S1 C14 0.33 10 9 8 7 6 C11 0.01 R9 10k D1 MBRD1035 0 Rb* C16 0.1 R10 10k +5V 1.5uH L2 Ra* 0 C17 150uF 16V INHIB PWRGD C19 150uF 16V 1uH L1 C20 0.1 +5V +12V C9 0.1 +5V +12V C21 C22 C23 C24 C25 C26 470uF 6.3V 470uF 6.3V 470uF 6.3V 470uF 6.3V 470uF 6.3V 460uF 6.3V C18 150uF 16V * Only one resistor/jumper to be installed, either Ra or Rb. R12 3.9 0.33 C13 R11 2.2 C12 0.1 1 2 3 4 5 +5V C27 0.1 1 2 3 4 J1 +5V +12V 1 2 3 4 5 6 J2 GND Vout _ Vout + Vin +5 to +12V _ + PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 APPLICATION CIRCUIT 13 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 MATERIALS LIST Quantity Reference Part/Description Vendor 1 C5 0.001µF 6 C1-C4, C8, C11 0.01µF 3 C17-C19 150µF, 16V (TPS) 7 C6,C7,C9,C12,C16,C20, C27 0.1µF 2 C13,C14 0.33µF 6 C21-C26 470µF, 6.3V (TPS) 2 C10,C15 2.2µF, 16V 1 D1 MBRD1035 MOT 1 L1 1µH, DO5022P-102 Coilcraft 1 L2 1.5µH, DO5022P-152HC Coilcraft 1 Q1 IRL3103NS, D2PAK Int. Rect. 1 Q2 IRL2203NS, D2PAK Int. Rect. 2 RA,RB 0Ω 1 R1 2K 2 R2,R4 1K 1 R3 2.7K 1 R5 100 1 R6 20K 1 R7 150 3 R8,R9,R10 10K 1 R11 2.2 1 R12 3.9 1 U1 SC1154, SO-28 Notes AVX AVX SEMTECH Layout guidelines 1. Locate R8 and C5 close to pins 6 and 7. 2. Locate C6 close to pins 5 and 7. 3. Components connected to IOUT, DROOP, OCP, VHYST, VREFB, VSENSE, and SOFTST should be referenced to AGND. 4. The bypass capacitors C10 and C15 should be placed close to the IC and referenced to DRVGND. 5. Locate bootstrap capacitor C13 close to the IC. 6. Place bypass capacitor C14 close to Drain of the top FET and Source of the bottom FET to be effective. 7. Route HISENSE and LOSENSE close to each other to minimize induced differential mode noise. 8. Bypass a high frequency disturbance with ceramic capacitor at the point where HISENSE is connected to Vin. 9. Input bulk capacitors should placed as close as possible to the power FETs because of the very high ripple current flow in this pass. 10. If Schottky diode used in parallel with a synchronous (bottom) FET, to achieve a greater efficiency at lower Vout settings, it needs to be placed next to the aforementioned FET in very close proximity. 11. Since the feedback path relies on the accurate sampling of the output ripple voltage, the best results can be achieved by connecting the AGND to the ground side of the bulk output capacitors. 12. DRVGND pin should be tight to the main ground plane utilizing very low impedance connection, e.g., multiple vias. 13. In order to prevent substrate glitching, a small (0.5A) Schottky diode should be placed in close proximity to the chip with the cathode connected to BOOTLO and anode connected to DRVGND. 14 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 EVALUATION BOARD ARTWORK TOP LAYER BOTTOM LAYER 15 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 EVALUATION BOARD LAYOUT TOP VIEW BOTTOM VIEW 16 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 TEST DATA SC1154 Efficiency 100.0 Vo 95.0 90.0 Vin = 5V 85.0 3.5 2.8 % 80.0 2.0 75.0 1.5 70.0 65.0 60.0 0 5 10 15 20 Output Current, A SC1154 Voltage Regulation 5.00 4.00 3.00 2.00 3.5 1.00 2.8 % 0.00 -1.00 0 2 4 6 8 10 12 14 2 1.5 -2.00 -3.00 -4.00 -5.00 Output Current, A 17 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320 PROGRAMMABLE SYNCHRONOUS DC/DC HYSTERETIC CONTROLLER FOR ADVANCED PROCESSORS SC1154 PRELIMINARY - March 1, 2000 OUTLINE - SO-28 ECN00-904 18 © 2000 SEMTECH CORP. 652 MITCHELL ROAD NEWBURY PARK CA 91320