ICs for Consumer Electronics MEGATEXT and MEGATEXT PLUS ICs SDA 5273 / SDA 5275 SDA 5273-2 / SDA 5275-2 Data Sheet 1997-09-01 MEGATEXT and MEGATEXT PLUS ICs SDA 5273 / SDA 5275 SDA 5273-2 / SDA 5275-2 Revision History: 1997-09-01 Previous Releases: 11.96 Page Subjects (changes since last revision) 20 Now also covers SDA 5275-2 and SDA 5273-2 versions; Reset/chip initialization update Data Classification Maximum Ratings Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. Characteristics The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 °C and the given supply voltage. Operating Range In the operating range the functions given in the circuit description are fulfilled. For detailed technical information about “Processing Guidelines” and “Quality Assurance” for ICs, see our “Short Form Catalog”. Edition 1997-09-01 Published by Siemens AG, Bereich Halbleiter, Marketing-Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1997. All Rights Reserved. As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. SDA 5273 / 75 SDA 5273-2 / 75-2 Contents Page 1 1.1 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3 Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 4 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 MEGATEXT is a registered trademark of Siemens AG Semiconductor Group 3 1997-09-01 MEGATEXT and MEGATEXT PLUS ICs SDA 5273 / 75 SDA 5273-2 / 75-2 Preliminary Data 1 CMOS IC Features Single chip teletext IC Analog CVBS-input with onchip clamping circuitry Slicer Supports level 1, 2.5 and 3.5 ETSI teletext standard Stores up to 14 teletext pages on chip Stores up to 2048 teletext pages with external 16 M memory ● SDA 5275: full level 2.5 processing ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● ● Analog RGB-output 41 latin script languages 12 × 10 character size Parallel display attributes 64 from 4096 colors selectable Enhanced flash modes Dynamically redefinable character set (DRCS, PCS) Pixel graphics Fullscreen display (64 × 32 or 80 × 24 character positions) Horizontal and vertical scrolling Graphic cursors 4:3 and 16:9 display Multinorm display (50/60/100/120 Hz) ● ● ● ● ● RISC-processor Firmware downloadable I2C / 3 wire UART-interface (1 Mbit/s) Independent clocks for acquisition and display Tools for greatly simplified software development P-LCC-68-1 P-SDIP-52-1 ● 24-Kbyte on-chip reconfigurable DRAM ● 44160-bit character ROM ● One external crystal for all standards Type Ordering Code Package SDA 5273 / 75 P on request P-LCC-68-1 SDA 5273 / 75 S on request P-SDIP-52-1 SDA 5273-2 / 75-2P on request P-LCC-68-1 SDA 5273-2 / 75-2S on request P-SDIP-52-1 SDA 5273C / 73-2C P on request P-LCC-68-1 SDA 5273C / 73-2C S on request P-SDIP-52-1 Semiconductor Group 4 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 Pin Configuration (top view) P-SDIP-52-1 CLK- ΙO 1 52 Ι NTQ TCSQ/FLD 2 51 Ι CEN VS/VCS 3 50 SDA HS 4 49 SCL X OUT 5 48 CORQ XIN 6 47 BLAN GPO 7 46 B TM 8 45 G CVBS 9 44 R V DD 1 10 43 V SS 1 V DD A 11 42 RGB-GND V SSA 1 12 41 V SSA 2 V DD 2 13 40 V SS2 RES 14 39 V BB /N.C. V DD 3 15 38 V SS3 V REF 16 37 CASQ V DD 4 17 36 V SS4 A8 18 35 D3 A7 19 34 D2 A6 20 33 D0 A5 21 32 D1 A4 22 31 WEQ A3 23 30 RASQ A2 24 29 A11 A1 25 28 A10 A0 26 27 A9 2 UEP04657 Semiconductor Group 5 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 1.1 Pin Definitions and Functions Pin No. P-SDIP-52-1 Symbol Function 1 CLK-IO System clock input/output 2 TCSQ/FLD Composite sync output/ field output 3 VS/VCS Vertical sync input/output 4 HS Horizontal sync input/output 5 XOUT 20.5-MHz crystal oscillator output 6 XIN 20.5-MHz crystal oscillator input 7 GPO General purpose output 8 TM Testpin, leave open or connect to VSS 9 CVBS CVBS-video signal input 10 VDD1 + 5 V digital supply 11 VDDA + 5 V analog supply 12 VSSA1 Analog ground 13 VDD2 + 5 V digital supply 14 RES Chip reset 15 VDD3 + 5 V digital supply 16 VREF + 3 V reference voltage input 17 VDD4 + 5 V digital supply 18 A8 External DRAM-address 19 A7 External DRAM-address 20 A6 External DRAM-address 21 A5 External DRAM-address 22 A4 External DRAM-address 23 A3 External DRAM-address 24 A2 External DRAM-address 25 A1 External DRAM-address 26 A0 External DRAM-address 27 A9 External DRAM-address 28 A10 External DRAM-address 29 A11 External DRAM-address 30 RASQ Row address strobe (DRAM) 31 WEQ Write enable (DRAM) 32 D1 External DRAM-data Semiconductor Group 6 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 1.1 Pin Definitions and Functions (cont’d) Pin No. P-SDIP-52-1 Symbol Function 33 D0 External DRAM-data 34 D2 External DRAM-data 35 D3 External DRAM-data 36 VSS4 0 V digital supply 37 CASQ Column address strobe 38 VSS3 0 V digital supply 39 VBB Substrate bias voltage N.C.1) 40 VSS2 0 V digital supply 41 VSSA2 Analog ground 42 RGB-GND RGB-ground 43 VSS1 0 V digital supply 44 R Analog red display output 45 G Analog green display output 46 B Analog blue display output 47 BLAN Blanking signal open drain output 48 CORQ Contrast reduction open drain output 49 SCL Bidirectional I2C Bus clock port 50 SDA Bidirectional I2C Bus data port 51 I2CEN I2C Bus enable 52 INTQ Interrupt request output to ext. controller 1) Depends on version. Please refer to the respective Delta Specification. Semiconductor Group 7 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 Pin Configuration (top view) TM GPO XIN XOUT HS VS/VCS TCSQ/FLD CLK-IO INTQ Ι 2 CEN SDA SCL CORQ BLAN B G R P-LCC-68-1 9 CVBS V DD1 V DDA V SSA1 N.C. N.C. VDD2 RES N.C. N.C. N.C. VDD3 N.C. VREF N.C. VDD4 A8 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 V SS1 RGB-GND V SSA2 N.C. V BB /N.C. V SS2 N.C. N.C. N.C. N.C. N.C. V SS3 N.C. N.C. N.C. CASQ V SS4 A7 A6 A5 A4 A3 A2 A1 A0 A9 A10 A11 RASQ WEQ D1 D0 D2 D3 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Semiconductor Group 8 UEP05514 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 1.2 Pin Definitions and Functions Pin No. P-LCC-68-1 Symbol Function 1 INTQ Interrupt request output to ext. controller 2 CLK-IO System clock input/output 3 TCSQ/FLD Composite sync output/ field output 4 VS/VCS Vertical sync input/output 5 HS Horizontal sync input/output 6 XOUT 20.5-MHz crystal oscillator output 7 XIN 20.5-MHz crystal oscillator input 8 GPO General purpose output 9 TM Testpin, leave open or connect VSS 10 CVBS CVBS-video signal input 11 VDD1 + 5 V digital supply 12 VDDA + 5 V analog supply 13 VSSA1 Analog ground 14 N.C. Not connected 15 N.C. Not connected 16 VDD2 + 5 V digital supply 17 RES Chip reset 18 N.C. Not connected 19 N.C. Not connected 20 N.C. Not connected 21 VDD3 + 5 V digital supply 22 N.C. Not connected 23 VREF + 3 V reference voltage input 24 N.C. Not connected 25 VDD4 + 5 V digital supply 26 A8 External DRAM-address 27 A7 External DRAM-address 28 A6 External DRAM-address 29 A5 External DRAM-address 30 A4 External DRAM-address 31 A3 External DRAM-address 32 A2 External DRAM-address Semiconductor Group 9 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 1.2 Pin Definitions and Functions (cont’d) Pin No. P-LCC-68-1 Symbol Function 33 A1 External DRAM-address 34 A0 External DRAM-address 35 A9 External DRAM-address 36 A10 External DRAM-address 37 A11 External DRAM-address 38 RASQ Row address strobe (DRAM) 39 WEQ Write enable (DRAM) 40 D1 External DRAM-data 41 D0 External DRAM-data 42 D2 External DRAM-data 43 D3 External DRAM-data 44 VSS4 0 V digital supply 45 CASQ Column address strobe 46 N.C. Not connected 47 N.C. Not connected 48 N.C. Not connected 49 VSS3 0 V digital supply 50 N.C. Not connected 51 N.C. Not connected 52 N.C. Not connected 53 N.C. Not connected 54 N.C. Not connected 55 VSS2 0 V digital supply 56 VBB Substrate bias voltage N.C.1) 57 N.C. Not connected 58 VSSA2 Analog ground 59 RGB-GND RGB-ground 60 VSS1 0 V digital supply 61 R Analog red display output 62 G Analog green display output 63 B Analog blue display output 1) Depends on version. Please refer to the respective Delta Specification. Semiconductor Group 10 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 1.2 Pin Definitions and Functions (cont’d) Pin No. P-LCC-68-1 Symbol Function 64 BLAN Blanking signal open drain output 65 CORQ Contrast reduction open drain output 66 SCL Bidirectional I2C Bus clock port 67 SDA Bidirectional I2C Bus data port 68 I2CEN I2C Bus enable Semiconductor Group 11 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 2 Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Limit Values min. typ. Unit max. Supply voltage VDD 0 6.0 V Ambient temperature TA 0 70 °C Storage temperature Tstg – 20 125 °C Power consumption Ptot 1.8 W Electrostatic discharge Test Condition 2000 V 100 pF, 1 kΩ HBM according to MIL-standard 883 method 3015.7 Unit Test Condition Characteristics TA = 0 to 70 °C Parameter Symbol Limit Values min. typ. max. VDDD 4.7 5.0 5.3 V VDDA 4.7 5.0 5.3 V VDDD = VDDA! IDDD 200 mA 20 pF load per pin IDDA 60 mA Supply Voltages Supply Currents Inputs Tristate of Outputs: I2CEN, HS, VS, GPO, RES, D0-D3 H-input voltage VIH 2.0 VDDD V L-input voltage VIL – 1.0 0.8 V Input capacitance CI 7 pF Input leakage current IL 10 µA VIH = 5.5 V Input current RES IIH 100 µA VIH = 5.5 V Semiconductor Group 12 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 Characteristics (cont‘d) TA = 0 to 70 °C Parameter Symbol Limit Values min. typ. Unit Test Condition max. Outputs TTL-Outputs: A0-A11, D0-D3, RASQ, CASQ, WEQ, HS, VS, GPO, INTQ, TCSQ H-output voltage VOH 2.4 VDDD V – IOH = 0.2 mA L-output voltage VOL 0 0.4 V IOL = 1.6 mA Load capacitance CL 50 pF Transition period tr, tf 15 ns Open Drain Outputs: BLAN, CORQ Sink current IOL 5 mA low level output L-output voltage VOL 0.4 V IOL = 2 mA H-output voltage VOH VDDD V BLAN = 1: BLAN = 0; CORQ = 1; CORQ = 0; display MEGATEXT RGB-outputs display other source switch contrast reduction OFF switch contrast reduction ON Sourcefollower Output: CVBS at pin TCSQ DC-offset to CVBS-input 1.2 Gain G Output current IO Output impedance RO Edge response tr V 0.9 0.9 200 1 mA CVBS = 1 V, TCSQ = 0 V Ω CVBS = 1 V µs 10 to 90 %, 1 Vpp, CL = 50 pF Sync Timing: HS, VS, TCSQ Sync Output Waveforms Pulse width HS tWH 2 µs Pulse width VS tWH 1 line VCS-waveform see diagram 6a, b TCSQ-waveform see diagram 6a, b Semiconductor Group 13 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 Characteristics (cont’d) TA = 0 to 70 °C Parameter Symbol Limit Values min. typ. Unit Test Condition max. Output Timing: HS, VS, TCSQ Hold and delay time with respect to 24-MHz system clock output: Delay time tOD Hold time tOH 20 0 ns see diagram 2 ns see diagram 2 Hold and delay time with respect to 24-MHz external system clock input: Delay time not specified Hold time not specified Input Timing: HS, VS No synchronous input mode specified! Clock Input/Output (see diagram 1) Clock Input H-input voltage VIH 2.0 VDDD V L-input voltage VIL – 1.0 0.8 V Input capacitance CI 7 pF Input leakage current Il 10 µA Period Tc 40 24-MHz clock Tc 35 27-MHz clock VIH = 5.5 V Transition time tCR, tCL Symmetry ratio tCH/tC 0.43 0.57 H-output voltage VOH 2.4 VDDD V – IOH = 0.2 mA L-output voltage VOL 0 0.4 V IOL = 1.6 mA Load capacitance CL 50 pF Period TC Transition time tCR, tCF Symmetry ratio tCH/tC 3 ns Clock Output Semiconductor Group 41.7 0.3 14 ns 5 ns 0.5 ns 20.5-MHz crystal 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 Characteristics (cont’d) TA = 0 to 70 °C Parameter Symbol Limit Values min. typ. Unit Test Condition max. RGB-Outputs VREF = 3 V no resistive load RGB-GND = 0 V Pin capacitance CP 7 V 2.2 V Output voltage range 0 RGB-amplitude 1.1 1.25 1.55 V R83: RGB-GAIN (4:0) = 1FH DC-offset voltage 0.7 0.8 1.0 V R83: RGB-LEVL (2:0) = 7 Clamp level 0 V DAC-resolution 4 bit Diff. non-linearity – 0.5 0.5 LSB Int. non-linearity – 0.5 0.5 LSB Output tracking – 0.5 0.5 LSB Output resistance 3-dB bandwidth RO 1 ----------------------2Π R O C L 270 Ω 10 MHz R83: RGB-GAIN (4:0) = 1FH RGB-LEVL (2:0) = 0 CL = 50 pF Bus Connection: SDA, SCL, I2CEN (see diagram 4) Inputs: SDA, SCL H-input voltage VIH 3.0 VDDD V L-input voltage VIL – 1.0 1.5 V Input capacitance CI 7 pF Input leakage current IL 10 µA VIH = 5.5 V VDD = 0 V … 5.5 V For modes with external clock MEGATEXT may only be operated in freerun mode as sync master. HS may not be used as an input in these cases. The RGB-output voltage is proportional to VREF. Semiconductor Group 15 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 Characteristics (cont’d) TA = 0 to 70 °C Parameter Symbol Limit Values min. typ. Unit Test Condition 0.4 V IOL = 3 mA 10 mA 100 kHz max. Open Drain Outputs: SDA, SCL L-output voltage VOL Sink current IOL 0 I2C-Mode Timing MEGATEXT is an I2C-slave transmitter/receiver. The Siemens I2C Bus specification applies. SCL-frequency fSCL Transition time tr, tf 2 µs Bus capacitance CBUS 400 pF Bus free before start tBUF 4.7 µs Hold time start tHSTA 4.0 µs L-time clock tLOW 4.0 µs H-time clock tHIGH 4.0 µs Set-up time start tSUSTA 4.0 µs Hold time SDA tHDDAT 0 µs Set-up time SDA tSUDAT 250 ns Set-up time SDA at stop tSUSTO 4.0 µs Output fall time tFO 0 0.2 µs I2CEN = high 3 V to 1 V M3L-Mode Timing The MEGATEXT M3L-Bus is specified in accordance with the standard USART-interface of micro controller SDA 30C162. SCL-frequency fSCL 0 L-time clock tL 400 ns H-time clock tH 400 ns SCL-load capacitance CSCL Set-up time SDA-input to SCL-falling edge tDSL 100 ns Hold time SDA-input from SCL-falling edge tDHH 400 ns Semiconductor Group 1.0 200 16 MHz 20.48-MHz crystal pF 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 Characteristics (cont’d) TA = 0 to 70 °C Parameter Symbol Limit Values min. typ. Unit Test Condition max. M3L-Mode Timing (cont’d) Set-up time SDA to I2CENrising edge tIM 400 ns Set up time I2CEN to SDAfalling edge tIS 400 ns I2CEN-high time tIH 1000 ns Delay from SCL-falling edge until SDA-open drain output stage changes impedance tDO 400 L-SDA level output impedance 600 ns Ω 100 The resulting delay of SDA-output data is the sum of the open drain stage plus the time determined by the bus capacitance and the external pullup resistor or the impedance of the internal open drain pulldown transistor respectively. I2CEN = 0 Wait condition To force the M3L-master to interrupt the transmission sequence until MEGATEXT is ready for more data, MEGATEXT can force down SCL after the transmission of a complete byte. At that time the bus master has to switch its SCL-output to high impedance and check the state of SCL afterwards.During SCL check I2CEN has to be low. Delay from SCL-rising edge to SCL forced low for WAITcondition tDWAIT 500 750 ns An internal pullup transistor restores SCL high level at the end of the WAIT-condition. tRWAIT 70 Voltage level VREF 2.8 Input leakage current Il – 10 SCL-pullup time at the end of WAIT 100 ns 3.5 V 10 µA Reference Voltage: VREF 3.0 VREF = 3 V VREF influences the DAC-range, the CVBS-output at pin TCSQ and the CVBS-ADC range. Semiconductor Group 17 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 Characteristics (cont’d) TA = 0 to 70 °C Parameter Symbol Limit Values min. typ. Unit Test Condition 1.0 µA CVBS = 2 V 45 pF max. CVBS-Input and ADC (VREF = 3 V) Input leakage current Il Input capacitance CP Ext. coupling capacitance CCPL – 1.0 100 nF Sensitivity of clamp level to current leakage/injection – 15 15 mV/ µA Il = 2 µA CCPL = 100 nF ADC-range 1.7 2.0 V VREF = 3 V CVBS-sync amplitude 0.1 V Crystal Oscillator: XIN, XOUT Bias resistance between XIN, XOUT RXbias 60 120 Small signal voltage gain GV 8 13 Feedback capacitance CFB 4.0 pF Pin capacitance CP 7.0 pF 180 kΩ 100 kHz, 50 mVpp Crystal Nominal frequency fO Effect of temperature and accuracy of adjustment df/fO –5% +5% Temperature range TA 0 70 °C Resonant impedance ZR 40 Ω Equivalent parallel C CL 20.48 15 Crystal load Ext. capacitors MHz pF 0.1 C1,2 15 mW pF The center frequency of the MEGATEXT horizontal PLL is proportional to the crystal frequency. In PAL-mode the centre frequency is 15.625 kHz for the typical crystal frequency of 20.48 MHz. Deviations from the typical crystal frequency will shift the range of the horizontal frequencies where the PLL is able to lock. Semiconductor Group 18 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 Characteristics (cont’d) TA = 0 to 70 °C Parameter Symbol Limit Values min. typ. Unit Test Condition max. DRAM-Interface (see diagram 5) The external DRAM is operated in page mode. The timing of the DRAM-interface signals are specified below. Cycle time tWC 420 Address hold time from RAS tRAH 25 ns Address hold time from CAS tCAH 60 ns Address set-up time from RAS tASR 5 ns Address set-up time from CAS tASC 5 ns L-time RAS tRASP 280 ns L-time CAS tCASL 70 ns H-time RAS tRP 140 ns H-time CAS tCP 70 ns 20 ms Refresh period 500 550 ns Write Cycle L-time WE tWEL 210 ns Data set-up time to CAS tDS 100 ns WE set-up time to CAS tRCS 0 ns Data hold time from CAS tDH 55 ns Data hold time from WE tOHZ 10 ns Read Cycle H-time WE (output enable) tOEL Access time from CAS tCAC Data hold time of DRAM tOFF Semiconductor Group 210 ns 60 40 ns ns 19 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 Characteristics (cont’d) TA = 0 to 70 °C Parameter Symbol Limit Values min. typ. Unit Test Condition max. Reset/Chip Initialization A power-on reset or a reset pulse at pin RES lead to a hardware reset and a software initialization of registers and internal DRAM. During initialization bus transfers are not allowed. At / after power-on a reset pulse at pin RES is necessary. RES may return to 0 after the supply voltage reached its lower limit for chip function (4.7 V). This may be achieved by a capacitor C between RES and VDD and by a resistor R between RES and VSS. The dimensions of R and C depend on the worst case rise time of VDD. Initialization time after power- tINIT on or falling edge of RES 25 ms VDD greater 4.7 V If the supply voltage drops below VDD min, the IC has to be reset by pin RES. Pulse width RES 100 ns High level at pin RES causes chip reset. In rare cases, the IC may remain in a permanent reset state after power up, depending on the applicational context. After power up, the software should check proper operation. In case the Megatext does not react properly, power supply should be switched off for at least 3 s. After that, power supply can be switched on again. Other Items Horizontal frequency pull-in range of CVBS-PLL: Horizontal frequency pull-in range of display-PLL: Semiconductor Group 15 15.625 16.2 kHz PAL 20.48 MHz crystal 15.2 15.748 16.3 kHz NTSC 20.48 MHz crystal 15 15.625 16.2 kHz 20.48 MHz crystal 20 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 3 Diagrams t CR t CF 2.0 V CLK 1.5 V 0.8 V t CH t CL tC UET04660 Timing Diagram 1 2.4 V 1.5 V CLK_OUT 0.8 V t OD t OH t OH 2.4 V HS VS 0.8 V tW t OD UET04662 Timing Diagram 2 Semiconductor Group 21 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 V IH Ι 2 CEN V IL t HIGH t f t LOW V IH SCL V IL t BUF t SUSTA t SUDAT t BUF t HDDAT t SUSTO V IH SDA V IL UET04815 Timing Diagram 3a I2C-Bus Mode Semiconductor Group 22 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 V IH Ι 2 CEN V IL t BUF t BUF t IS t HIGH t f t LOW t r t IM V IH SCL V IL t DS t DSL t DHH t DO t DHH V IH SDA V IL V OL Wait Condition t RWAIT t DWAIT SCL V IH WAIT V IL V OL UET04816 Timing Diagram 3b M3L-Bus Mode Semiconductor Group 23 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 t WC A0... A11 Row Address Column Address Column Address t WE WEQ t WEL D0... D3 t OHZ Data from SDA 527x Data from SDA 527x t DS t DS t RP t DH t DH t RAH RASQ t RASP t ASR t CAH t CP t CP CASQ t ASC t CASL t CASL UET04663 Timing Diagram 4a DRAM-Page Mode Write Cycle Semiconductor Group 24 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 t RC A0... A11 Column Address Row Address Column Address t OE WEQ t OEL D0... D3 Data from RAM Data from RAM t OFF t OFF t CAC t RP t CAC t RAH RASQ t RASP t ASB t CAH t CP t CP CASQ t ASC t CASL t CASL UET04664 Timing Diagram 4b DRAM-Page Mode Read Cycle Semiconductor Group 25 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 a) Line Sync Pulse b) Equalizing Pulse 0 4.7 0 2.35 32 34.35 64 t [ µ s] 64 t [ µ s] 59.3 64 t [ µ s] c) Main Pulse 0 27.3 32 Timing with Tolerances ± 100 ns VCS 622 (309) 623 (310) 624 (311) 625 (312) 1 2 3 4 5 6 310 311 312 313 314 315 316 317 318 319 VCS Interlaced TCS 622 (309) 623 (310) 624 (311) 625 (312) 1 2 3 4 5 6 Interlaced TCS 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) TCS 309 (310) (621) (623) 310 (311) (622) (624) 311 (312) (623) (625) 312 (313) (624) (626) 1 (1) 2 (2) 3 (3) 4 (4) 5 (5) 6 (6) NonInterlaced -312/312 Lines -313/312 Lines -626/624 Lines UED04865 Timing Diagram 5a VCS and TCS in PAL Freerun Mode Semiconductor Group 26 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 a) Line Sync Pulse 0 4.7 63.6 t [µs] 63.6 t [µs] 63.6 t [µs] b) Equalizing Pulse 0 2.3 31.8 34.1 c) Main Pulse 0 27.1 31.8 58.9 VCS 522 (259) 523 (260) 524 (261) 525 (262) 1 2 3 4 5 6 260 261 262 263 264 (1) 265 (2) 266 (3) 267 (4) 268 (5) 269 (6) VCS TCS Interlaced 522 (259) 523 (260) 524 (261) 525 (262) 1 2 3 4 5 6 TCS Interlaced 260 261 262 263 264 (1) 265 (2) 266 (3) 267 (4) 268 (5) 269 (6) TCS 259 (260) (521) (523) 260 (261) (522) (524) 261 (262) (523) (525) 262 (263) (524) (526) 1 (1) 2 (2) 3 (3) 4 (4) 5 (5) 6 (6) NonInterlaced -262/262 Lines -263/262 Lines -526/524 Lines UED04872 Timing Diagram 5b VCS and TCS in NTSC Freerun Mode Semiconductor Group 27 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 TTL HS VS TTL TCSQ 1.15 Vpp 270 Ω TTL INTQ Ι 2 CEN SDA SCL G B R V DD 4.7 kΩ 22 pF Contrast 150 Ω Reduction 22 pF 20.48 MHz 4.7 kΩ V DD V DD 5V V DD 470 Ω Ref. ZD 3V 220 nF V SS 220 nF RGB-GND V SSA2 N.C. V BB N.C. N.C. V DD2 V SS2 N.C. N.C. N.C. N.C. N.C. V SS3 RESET N.C. N.C. N.C. V DD3 SDA 527x N.C. V REF N.C. N.C. N.C. CASQ V SS4 N.C. V DD4 A8 A7 A6 A5 A4 A3 A2 A1 A0 A9 A10 A11 RASQ WEQ D1 D0 D2 D3 10 kΩ V SS1 CVBS V DD1 V DDA V SSA1 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 220 nF 100 kΩ 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 10 µF 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 TM GPO XIN XOUT HS VS TCSQ CLK INTQ Ι 2 CEN SDA SCL CORQ BLAN B G R 2 Vpp V DD 150 Ω Blank 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 100 nF CVBS DRAM UES04659 Application Circuit Semiconductor Group 28 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 4 Package Outlines 5.08 max 1.2 x 45˚ 0.2 0.5 min 3.5 ±0.2 P-LCC-68-1 (SMD) (Plastic Leaded Chip Carrier) 1.27 0.43 ±0.1 0.81 max 23.3 ±0.3 0.18 M A-B D 68x 20.32 24.21 ±0.07 1) 0.1 0.38 M A-B D 34x 25.28 -0.26 D B A 0.5 x 45˚ 3x 68 1 1.1 x 45˚ Index Marking 24.21 ±0.07 1) 25.28 -0.26 1) Does not include plastic or metal protrusions of 0.15 max per side Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 29 GPL05099 Dimensions in mm 1997-09-01 SDA 5273 / 75 SDA 5273-2 / 75-2 1.3 max 0.46 ±0.1 0.25 M 52x 52 1 14.02 ±0.25 15.24 +1.7 27 26 46.1 -0.3 Index Marking Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 0.25 ±0.05 30 0.25 max GPD05262 1.78 15.24 +0.7 3.43 -0.4 0.5 min 4.83 max Plastic Package, P-SDIP-52-1 (Plastic Dual In-Line Package) Dimensions in mm 1997-09-01