4M × 1-Bit Dynamic RAM HYB 514100BJ-50/-60 Advanced Information • 4 194 304 words by 1-bit organization • 0 to 70 °C operating temperature • Fast Page Mode Operation • Performance: -50 -60 tRAC RAS access time 50 60 ns tCAC CAS access time 13 15 ns tAA Access time from address 25 30 ns tRC Read/Write cycle time 95 110 ns tPC Fast page mode cycle time 35 40 ns • Single + 5 V (± 10 %) supply with a built-in VBB generator • Low power dissipation max. 660 mW active (-50 version) max. 605 mW active (-60 version) • Standby power dissipation: 11 mW max. standby (TTL) 5.5 mW max. standby (CMOS) • Output unlatched at cycle end allows two-dimensional chip selection • Read, write, read-modify write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode capability • All inputs and outputs TTL-compatible • 1024 refresh cycles/16 ms • Plastic Packages: P-SOJ-26/20-2 with 300 mil width Semiconductor Group 1 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM The HYB 514100BJ is the new generation dynamic RAM organized as 4 194 304 words by 1-bit. The HYB 514100BJ utilizes CMOS silicon gate process as well as advances circuit techniques to provide wide operation margins, both internally and for the system user. Multiplexed address inputs permit the HYB 514100BJ to be packed in a standard plastic P-SOJ-26/20 package. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System oriented features include single + 5 V (± 10 %) power supply, direct interfacing with high performance logic device families such as Schottky TTL. Type Ordering Code Package Descriptions HYB 514100BJ-50 Q67100-Q971 P-SOJ-26/20-2 300 mil DRAM (access time 50 ns) HYB 514100BJ-60 Q67100-Q759 P-SOJ-26/20-2 300 mil DRAM (access time 60 ns) P-SOJ-26/20-2 DI WE RAS N.C. A10 1 2 3 4 5 26 25 24 23 22 V SS DO CAS N.C. A9 A0 A1 A2 A3 V CC 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 SPP02808 Pin Configuration Pin Names A0 – A10 Address Input RAS Row Address Strobe CAS Column Address Strobe WE Read/Write Input DI Data In DO Data Out VCC Power Supply (+ 5 V) VSS Ground (0 V) N.C. No Connection Semiconductor Group 2 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM & WE CAS No.2 Clock Generator 11 A0 Column Address Buffers (11) Data In Buffer DI Data Out Buffer DO 11 Column Decoder A1 A2 Refresh Controller A3 Sense Amplifier I/O Gating A4 A5 A6 A8 10 A9 A10 4096 . .. A7 . .. Refresh Counter (10) 11 RAS Row Address Buffers (11) 10 Row Decoder .. . 1024 .. . No.1 Clock Generator Substrate Bias Generator Memory Array V CC V SS SPB02847 Block Diagram Semiconductor Group 3 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM Absolute Maximum Ratings Operating temperature range ........................................................................................... 0 to 70 °C Storage temperature range.................................................................................... – 55 to + 150 °C Input/output voltage ....................................................................................................... – 1 to + 7 V Power Supply voltage .................................................................................................... – 1 to + 7 V Data out current (short circuit) ............................................................................................... 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = 0 to 70 °C, VSS = 0 V, VCC = 5 10 %, tT = 5 ns Parameter Symbol Limit Values min. max. Unit Test Condition Input high voltage VIH 2.4 VCC + 0.5 V 1 Input low voltage VIL – 1.0 0.8 V 1 Output high voltage (IOUT = – 5 mA) VOH 2.4 – V 1 Output low voltage (IOUT = 4.2 mA) VOL – 0.4 V 1 Input leakage current, any input (0 V < VIN < 7, all other input = 0 V) II(L) – 10 10 µA 1 Output leakage current (DO is disabled, 0 < VOUT < VCC) IO(L) – 10 10 µA 1 – – 120 110 mA mA 2, 3 ICC2 – 2 mA Average VCC supply current during RAS-only ICC3 refresh cycles -50 version -60 version – – 120 110 mA mA 2 Average VCC supply current during fast page ICC4 mode operation -50 version -60 version – – 80 70 mA mA 2, 3 Average VCC supply current ICC1 -50 version -60 version Standby VCC supply current (RAS = CAS = WE = VIH) Semiconductor Group 4 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM DC Characteristics (cont’d) TA = 0 to 70 °C, VSS = 0 V, VCC = 5 10 %, tT = 5 ns Parameter Symbol Standby VCC supply current ICC5 Average VCC supply current during CAS-before-RAS refresh mode ICC6 Limit Values min. max. Unit Test Condition – 1 mA 1 2 -50 version -60 version – – 120 110 mA mA Capacitance TA = 0 to 70 °C, VCC = 5.0 V ± 10 %, f = 1 MHz Parameter Symbol Limit Values min. max. Unit Input capacitance (A0 to A10, DI) CI1 – 5 pF Input capacitance (RAS, CAS, WE) CI2 – 7 pF Output capacitance (DO) CIO – 7 pF AC Characteristics 5, 6 TA = 0 to 70 °C, VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Limit Values Unit Note -50 -60 min. max. min. max. Common Parameters Random read or write cycle time tRC 95 – 110 – ns RAS precharge time tRP 35 – 40 – ns RAS pulse width tRAS 50 10k 60 10k ns CAS pulse width tCAS 13 10k 15 10k ns Row address setup time tASR 0 – 0 – ns Row address hold time tRAH 8 – 10 – ns Column address setup time tASC 0 – 0 – ns Column address hold time tCAH 10 – 15 – ns RAS to CAS delay time tRCD 18 37 20 45 ns RAS to column address delay time tRAD 13 25 15 30 ns RAS hold time tRSH 13 15 – ns CAS hold time tCSH 50 60 – ns Semiconductor Group 5 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM AC Characteristics (cont’d) 5, 6 TA = 0 to 70 °C, VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Limit Values Unit Note -50 -60 min. max. min. max. CAS to RAS precharge time tCRP 5 – 5 – ns Transition time (rise and fall) tT 3 50 3 50 ns Refresh period tREF – 16 – 16 ms Access time from RAS tRAC – 50 – 60 ns 8, 9 Access time from CAS tCAC – 13 – 15 ns 8, 9 Access time from column address tAA – 25 – 30 ns 8, 10 Column addr. to RAS lead time tRAL 25 – 30 – ns Read command setup time tRCS 0 – 0 – ns Read command hold time tRCH 0 – 0 – ns 11 Read command hold time referenced to RAS tRRH 0 – 0 – ns 11 CAS to output in low–Z tCLZ 0 – 0 – ns 8 Output buffer turn-off delay tOFF 0 13 0 15 ns 12 Write command hold time tWCH 8 – 10 – ns Write command pulse width tWP 8 – 10 – ns Write command setup time tWCS 0 – 0 – ns Write command to RAS lead time tRWL 13 – 15 – ns Write command to CAS lead time tCWL 13 – 15 – ns Data setup time tDS 0 – 0 – ns 14 Data hold time tDH 10 – 10 – ns 14 Read-write cycle time tRWC 115 – 130 – ns RAS to WE delay time tRWD 50 – 60 – ns 13 CAS to WE delay time tCWD 13 – 15 – ns 13 Column address to WE delay time tAWD 25 – 30 – ns 13 7 Read Cycle Write Cycle 13 Read-Modify-Write Cycle Semiconductor Group 6 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM AC Characteristics (cont’d) 5, 6 TA = 0 to 70 °C, VCC = 5 V ± 10 %, tT = 5 ns Parameter Symbol Limit Values Unit Note -50 -60 min. max. min. max. Fast Page Mode Cycle Fast page mode cycle time tPC 35 – 40 – ns CAS precharge time tCP 10 – 10 – ns Access time from CAS precharge tCPA – 30 – 35 ns RAS pulse width tRAS 50 200k 60 200k ns CAS precharge to RAS Delay tRHCP 30 – 35 – ns Fast page mode read-write cycle time tPRWC 55 – 60 – ns CAS precharge to WE tCPWD 30 – 35 – ns CAS setup time tCSR 10 – 10 – ns CAS hold time tCHR 10 – 10 – ns RAS to CAS precharge time tRPC 5 – 5 – ns Write to RAS precharge time tWRP 10 – 10 – ns Write hold time referenced to RAS tWRH 10 – 10 – ns tCPT 35 – 40 – ns Write command setup time tWTS 10 – 10 – ns Write command hold time tWTH 10 – 10 – ns 7 Fast Page Mode Read-Modify-Write Cycle CAS-before-RAS Refresh Cycle CAS-before-RAS Counter Test Cycle CAS precharge time Test Mode Semiconductor Group 7 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM Notes All voltages are referenced to VSS. ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5. An initial pause of 200 µs is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume tT = 5 ns. 7. VIH (MIN.) and VIL (MAX.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8. Measured with a load equivalent to 2 TTL loads and 100 pF. 9. Operation within the tRCD (MAX.) limit ensures that tRAC (MAX.) can be met. tRCD (MAX.) is specified as a reference point only: If tRCD is greater than the specified tRCD (MAX.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD (MAX.) limit ensures that tRAC (MAX.) can be met. tRAD (MAX.) is specified as a reference point only: If tRAD is greater than the specified tRAD (MAX.) limit, then access time is controlled by tAA. 11.Either tRCH or tRRH must be satisfied for a read cycle. 12.tOFF (MAX.) defines the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 13.tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (MIN.), the cycle is an early write cycle and the data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (MIN.), tCWD > tCWD (MIN.), tAWD > tAWD(MIN.) and tCPWD > tCPWD (MIN.), the cycle is a readwrite cycle and DO will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the DO pin (at access time) is indeterminate. 14.These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 1. 2. 3. 4. Semiconductor Group 8 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM t RC t RAS t RP VIH RAS VIL t CSH t RCD t RSH t CAS VIH t CRP CAS VIL t RAD t ASR VIH A0 - A10 VIL t RAL t CAH t ASC Row Address t ASR Column Address Row Address t RAH t RCH t RCS t RRH VIH WE VIL t AA t CAC t CLZ VOH DO (Output) V OL Hi Z t OFF Valid Data OUT Hi Z t RAC "H" or "L" SPT03013 Read Cycle Semiconductor Group 9 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM t RC t RAS t RP VIH RAS VIL t CSH t RCD t RSH t CAS VIH t CRP CAS VIL t RAD t ASR VIH A0 - A10 VIL t ASC Row Address t RAH t RAL t CAH t ASR Column Address t CWL t WCS VIH Row Address t WP WE VIL t DS DI (Input) t WCH t RWL t DH VIH Valid Data IN VIL VOH DO (Output) V OL Hi Z "H" or "L" SPT03014 Write Cycle (Early Write) Semiconductor Group 10 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM t RWC t RAS VIH RAS VIL t CSH t RP t CRP t CAS t RSH t RCD VIH CAS VIL t RAH t ASR VIH A0 - A10 VIL t CAH t ASR t ASC Row Address Column Address Row Address t CWL t AWD t RAD t CWD t RWL t WP t RWD VIH WE VIL t DS t AA t RCS DI (Input) t DH VIH Valid Data IN VIL t CAC t CLZ t OFF VOH DO (Output) V OL Data OUT t RAC "H" or "L" SPT03015 Read-Write (Read-Modify-Write) Cycle Semiconductor Group 11 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM t RASP VIH RAS VIL t CSH t RP t CP t RCD t PRWC t CAS t RSH t CAS t CAS t CRP VIH CAS VIL t RAD t ASR VIH A0 - A10 VIL t RAH t CAH t CAH t ASC Row Address t CAH t ASC Column Address t ASC Column Address t RWD t CWD t RCS t RAL Row Address Column Address t CPWD t CWD t CWL t ASR t CPWD t CWD t CWL t RWL t CWL VIH WE VIL t AWD t AWD t AWD t WP t AA DI (Input) t DS t WP t DH t AA t DS t WP t AA t DH t DS t DH VIH Data IN Data IN Data IN VIL t CPA t CLZ t CLZ t CAC t CAC t RAC VOH DO (Output) V OL t CPA t CLZ t OFF t OFF t OFF Data OUT Data OUT "H" or "L" Data OUT SPT03016 Fast Page Mode Read-Modify-Write Cycle Semiconductor Group 12 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM t RASP VIH RAS VIL t RCD t RP t PC t RHCP t CP t RSH t CAS t CAS t CRP t CAS VIH CAS VIL t RAH t ASR VIH A0 - A10 VIL t ASC Row Addr t CSH t CAH t ASC t CAH t CAH Column Address Column Address t ASR t ASC Column Address Row Address t RCH t RCH t RAD t RCS t RCS t RCS t RRH VIH WE VIL t RAC t CPA t AA t CAC t AA t CAC t OFF t CLZ VOH DO (Output) V OL t CPA t AA t CAC t OFF t CLZ Valid Data OUT t OFF t CLZ Valid Data OUT Valid Data OUT "H" or "L" SPT03017 Fast Page Mode Read Cycle Semiconductor Group 13 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM t RASP VIH RAS VIL t PC t RP t CAS t RCD t CAS t RSH t CAS t CP t CRP VIH CAS VIL t RAH t ASR VIH A0 - A10 VIL t ASC Row Addr t CAH t ASC Column Address t RAL t CAH t CAH t ASC Column Address Column Address t RAD t WCS t CWL t CWL t WCS t WCH t WP t ASR t WCS t WCH t WP Row Address t RWL t CWL t WCH t WP VIH WE VIL t DS DI (Input) VIH t DH Valid Data IN VIL t DH t DS Valid Data IN VOH DO (Output) V OL t DS t DH Valid Data IN Hi Z "H" or "L" SPT03018 Fast Page Mode Early Write Cycle Semiconductor Group 14 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM t RC t RAS t RP VIH RAS VIL t CRP t RPC VIH CAS VIL t RAH t ASR VIH t ASR Row Address A0 - A10 VIL Row Address VOH DO (Output) V OL Hi Z "H" or "L" SPT03019 RAS-Only Refresh Cycle Semiconductor Group 15 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM t RC t RP t RAS t RP VIH RAS VIL t RPC t CRP t CSR t CP t CHR t RPC VIH CAS VIL t WRP t WRH VIH WE VIL t OFF VOH DO (Output) V OL Hi Z "H" or "L" SPT03020 CAS-Before-RAS Refresh Cycle Semiconductor Group 16 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM t RC t RAS t RC t RP t RAS t RP VIH RAS VIL t RCD t RSH t CHR t CRP VIH CAS VIL t RAD t ASC t RAH t WRH t ASR VIH A0 - A10 VIL t CAH Row Addr. t WRP t ASR Column Address Row Address t RRH t RCS VIH WE VIL t AA t CAC t CLZ t OFF t RAC VOH DO (Output) V OL Valid Data OUT "H" or "L" Hi Z SPT03021 Hidden Refresh Cycle (Read) Semiconductor Group 17 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM t RC t RC t RAS t RP t RAS t RP VIH RAS VIL t RCD t RSH t CHR t CRP VIH CAS VIL t RAD t ASC t RAH t ASR VIH A0 - A10 VIL t ASR t CAH Row Addr Column Address Row Address t WCS t WCH t WP VIH WE VIL t DS t DH DI (Input) VIN Valid Data VIL VOH DO (Output) V OL Hi Z "H" or "L" SPT03022 Hidden Refresh Cycle (Early Write) Semiconductor Group 18 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM t RAS t RP VIH RAS VIL t RSH t CHR t CSR t CPT VIH t CAS CAS VIL t RAL t CAH t ASR t ASC VIH Column Address A0 - A10 VIL t WRH t RRH t AA t CAC t WRP Read Cycle Row Address t RCS t RCH VIH WE VIL t OFF t CLZ VOH DO (Output) V OL Valid Data OUT t WCS t WRP Write Cycle t RWL t CWL t WRH VIH t WCH WE VIL t DH t DS DI (Input) VIH Valid Data IN VIL VOH DO (Output) VOL Read-ModifyWrite Cycle Hi Z t CWL t RWL t WRP t WRH VIH t RCS t AWD t CWD t WP WE VIL t CAC t AA DI (Input) t DS t DH VIH Data IN VIL t OFF t CLZ VOH DO (Output) V OL Valid Data OUT t CAC "H" or "L" SPT03023 CAS-Before-RAS Refresh Counter Test Cycle Semiconductor Group 19 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM t RC t RP t RAS t RP VIH RAS VIL t RPG t CSR t CP t RPC t CRP t CHR VIH CAS VIL t ASR VIH Row Address A0 - A10 VIL t WTH t WTS VIH WE VIL t OFF VOH DO (Output) V OL Hi Z "H" or "L" SPT03024 Test Mode Entry Test Mode The HYB 514100BJ is organized 4 194 304 words by 1-bit but can internally be configured as 524 288 words by 8-bits. A WE, CAS-before-RAS cycle puts the device into Test Mode. In Test Mode, data is written into 8 sectors in parallel and retrieved the same way. If, upon reading, all bits are equal, the data output pin indicates a “1”. If any of the bits differ, the data output pin indicates a “0”. In Test Mode the 4M DRAM can be tested as if it were a 512K DRAM. Test Mode is exited by any refresh operation which is not a WE, CAS-before-RAS cycle. Addresses A10R, A10C and A0C do not care during Test Mode. Semiconductor Group 20 1998-10-01 HYB 514100BJ-50/-60 4M × 1 DRAM Package Outlines 1.27 0.51-0.1 0.85 max 0.1 0.2 20x 15.24 26 6.8 ±0.3 8.63 -0.25 0.25 B 0.18 B 0.25 A 22 18 14 5 9 13 1.4 ø1 7.75 -0.25 0.3 30˚ B 0.2 +0.1 3.75 -0.5 0.8 min 2.75 0.6 Plastic Package, P-SOJ-26/20-2 (SMD) (Plastic small outline J-leaded) 1 1 17.27 -0.25 A Index Marking GPJ09100 Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 21 Dimensions in mm 1998-10-01