ETC SED1560

SED1560/1/2
Technical Manual
(Preliminary)
S-MOS Systems, Inc.
October, 1996
Version 3.0 (Preliminary)
174-3.0
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174-3.0
Table of Contents
SED1560 Series
TABLE OF CONTENTS
1.0 Overview ................................................................................................................................................... 5
1.1 Description .................................................................................................................................... 7
1.2 Features ........................................................................................................................................ 7
1.3 System Block Diagrams ................................................................................................................ 7
1.4 Block Diagram ............................................................................................................................... 9
2.0 Pin Description ....................................................................................................................................... 11
2.1 Power Supply .............................................................................................................................. 13
2.2 LCD Driver Power Supplies ......................................................................................................... 13
2.3 Microprocessor Interface ............................................................................................................. 14
2.4 Oscillator and Display Timing Control ......................................................................................... 15
2.5 LCD Driver Outputs ..................................................................................................................... 16
3.0 Electrical Characteristics ...................................................................................................................... 17
3.1 Absolute Maximum Ratings ......................................................................................................... 19
3.2 DC Characteristics ...................................................................................................................... 20
3.3 AC Characteristics........................................................................................................................ 24
3.3.1 Reset ............................................................................................................................ 24
3.4 Display Control Timing ................................................................................................................ 25
3.5 System Buses: Read/Write Characteristics I (80-Series MPU) ................................................... 27
3.6 System Buses: Read/Write Characteristics II (68-Series MPU) .................................................. 28
3.7 Serial Interface ............................................................................................................................ 30
4.0 Functional Description .......................................................................................................................... 33
4.1 Microprocessor Interface ............................................................................................................. 35
4.1.1 Parallel/Serial Interface ................................................................................................ 35
4.1.2 Parallel Interface ........................................................................................................... 35
4.1.3 Serial Interface ............................................................................................................. 35
4.1.4 Chip Select Inputs ........................................................................................................ 36
4.2 Data Transfer .............................................................................................................................. 36
4.3 Status Flag .................................................................................................................................. 38
4.4 Display Data RAM ....................................................................................................................... 38
4.5 Column Address Counter ............................................................................................................ 38
4.6 Page Address Register ............................................................................................................... 38
4.7 Initial Display Line Register ......................................................................................................... 40
4.8 Output Selection Circuit............................................................................................................... 40
4.9 SED1560 Output Status .............................................................................................................. 42
4.10 SED1561 Output Status ............................................................................................................ 42
4.11 SED1562 Output Status ............................................................................................................ 43
4.12 Display Timers ........................................................................................................................... 43
4.12.1 Line Counter and Display Data Latch Timing ............................................................. 43
4.12.2 FR and SYNC ............................................................................................................. 43
4.12.3 Common Timing Signals ............................................................................................ 43
4.13 Two-frame AC Driver Waveform (SED1561, 1/32 duty) ............................................................ 44
4.14 n Line Inverse Driver Waveform (n-5, line inverse register 4) .................................................. 45
4.15 Display Data Latch .................................................................................................................... 46
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SED1560 Series
4.16
4.17
4.18
4.19
4.20
4.21
4.22
4.23
4.24
4.25
4.26
4.27
Table of Contents
LCD Driver ................................................................................................................................. 46
Display Data Latch Circuit ......................................................................................................... 46
LCD Driver Circuit ..................................................................................................................... 46
Oscillator Circuit ........................................................................................................................ 46
FR Control Circuit ...................................................................................................................... 46
Power Supply Circuit ................................................................................................................. 48
Tripler Boosting Circuit .............................................................................................................. 48
Voltage Regulation Circuit (Software Contrast Adjustment Function is Not Used) ................... 49
Voltage Regulation Circuit Using Software Contrast Adjustment Control Function .................. 50
Precautions on Using the SED1560 Series Software Contrast Adjustment Control Function .. 51
Liquid Crystal Voltage Generating Circuit ................................................................................. 54
Reset ......................................................................................................................................... 56
5.0 Commands .............................................................................................................................................. 57
5.1 Command Summary .................................................................................................................. 59
5.2 Command Definitions ................................................................................................................. 60
5.3 Software Contrast Control Register............................................................................................. 67
5.4 Microprocessor Interface ............................................................................................................. 69
5.5 LCD Panel Interface Examples ................................................................................................... 70
5.6 Special Common Driver Configurations ...................................................................................... 72
6.0 Packaging ............................................................................................................................................... 73
6.1 Pad Layout .................................................................................................................................. 75
6.2 SED1560/1/2 TAB Pin Layout ..................................................................................................... 77
6.3 TCP Dimensions (2-sided) .......................................................................................................... 78
6.4 TCP Dimensions (4-sided) .......................................................................................................... 79
6.5 TCP Dimensions (D1561TOC) .................................................................................................... 80
6.6 Pad Profile ................................................................................................................................... 81
6.7 BGA Package Dimensions .......................................................................................................... 82
6.8 BGA Pin Assignment ................................................................................................................... 83
6.9 SED1560TQA OL Dimensions .................................................................................................... 84
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1.0
Overview
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1.0 Overview
1.0 – 1.3
1.1 DESCRIPTION
1.2 FEATURES
The SED1560 Series are intelligent CMOS LCD drivercontrollers with the ability to drive alphanumeric and
graphic displays. The SED1560 Series communicates
with a high-speed microprocessor, such as the Intel
80XX family or the Motorola 68XX family, through
either a serial or an 8-bit parallel interface. It stores the
data sent from the microprocessor in the built-in display
data RAM (166 × 65 bits) and generates an LCD drive
signal. These devices incorporate an internal DC/DC
converter to generate the negative voltage needed for
LCD contrast. The controllers feature software contrast
adjustment by command setting.
The three different versions of the SED1560 Series
support the following duty ratios and display sizes:
Model
SED1560
SED1561
SED1562
Duty Ratio
SEG × COM
1/65, 1/64, 1/49, 1/48
102 × 65
1/33, 1/32, 1/25, 1/24
134 × 33
1/17, 1/16
150 × 17
• Low-power operation: 8 µA @ 1 kHz, 6V LCD
• 350 µA current consumption during CPU access
@ 200 kHz
• Direct interface to both 80XX and 68XX, 5 MHz,
zero wait-state
• On-chip display data RAM (166 × 65 bits)
• On-chip DC/DC converter for LCD voltage
• On-chip voltage regulator and low-power voltage follower
• –.17% / °C temperature gradient
• On-chip oscillator with external resistor
• 32 levels of contrast adjustment by software
• Supports master/slave operation
• Selectable output configuration
• 2.4V to 6.0V supply voltage
• 3.5V to 16V LCD voltage
• Package: TAB 2 side
T0B
TAB 4 side
TQA
Al pad
D*A
Au bump
D*B
BGA 225 pad
B0A
1.3 SYSTEM BLOCK DIAGRAMS
20 CHAR × 8 LINES
RES
CPU
CS
D0 ~ D7
SED1560
80xx
68xx
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1.3
1.0 Overview
1.3 SYSTEM BLOCK DIAGRAMS (cont.)
COM0~COM32
26 CHAR × 4 LINES
SEG0~SEG133
RES
CPU
CS
D0 ~ D7
SED1561
80xx
68xx
30 CHAR × 2 LINES
RES
CPU
CS
D0 ~ D7
SED1562
80xx
68xx
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174-3.0
1.0 Overview
1.4
1.4 BLOCK DIAGRAM
O00 to O31 O32
to
O101 O102 to O165 COM1
VSS
VDD
VDD
V1
Common
and
segment
drivers
V2
V3
V4
Common
and
segment
drivers
Segment
driver
V1
V2
Commons
only
V3
V4
V5
CAP1+
CAP1–
CAP2+
Shift
register
LCD
supply
voltage
generator
V5
Frame
control
Shift
register
166-bit display data latch
CAP2–
VR
T1, T2
Output
status
select
I/O
buffer
Line
address
decoder
166 x 65-bit display
data RAM
Line
counter
Display
initial line
register
166-bit column address decoder
8-bit column address counter
Page
address
register
Bus holder
174-3.0
Display
timing
generator
8-bit column address register
Command
decoder
Status flag
Oscillator
MPU interface
I/O buffer
CS1 CS2 A0 RD WR C86 SI SCL P/S RES
D7 D6 D5 D4 D3 D2 D1 D0
FR
SYNC
CL
CLO
DYO
M/S
OSC1
OSC2
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2.0
Pin Description
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174-3.0
2.0 Pin Description
2.1 – 2.2
2.1 POWER SUPPLY
Number of Pins
2
2
11
I/O
Supply
Supply
Name
Description
VDD
Common to MPU power supply pin VCC
VSS
Ground
Supply V1 to V5 LCD driver supply voltages. The voltage determined by the LCD
cell is impedance-converted by a resistive divider or an operational
LCD
amplifier for application. Voltage levels are based on VDD. The
voltage
voltages must satisfy the following relationship:
VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5
Master mode select: bias voltages are generated on-chip.
SED1560
1/9 V5
2/9 V5
7/9 V5
8/9 V5
V1
V2
V3
V4
SED1561
1/7 V5
2/7 V5
5/7 V5
6/7 V5
SED1562
1/5 V5
2/5 V5
3/5 V5
4/5 V5
2.2 LCD DRIVER POWER SUPPLIES
Number of Pins
1
I/O
O
Name
CAP1+
Description
DC/DC voltage converter capacitor 1 positive connection
1
1
1
1
O
O
O
O
CAP1–
CAP2+
CAP2–
VOUT
DC/DC voltage converter capacitor 1 negative connection
DC/DC voltage converter capacitor 2 positive connection
DC/DC voltage converter capacitor 2 negative connection
1
I
VR
2
I
T1, T2
DC/DC voltage converter output
Voltage adjustment pin. Applies voltage between VDD and V5 using
a resistive divider.
Liquid crystal power control terminals
T1
T2
Boosting
Circuit
L
L
H
H
L
H
L
H
Valid
Valid
Invalid
Invalid
Voltage
Regulation
Circuit
Valid
Valid
Valid
Invalid
V/F Circuit
Valid
Valid*
Valid
Valid
* V/F circuit current capacity enhancement
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2.3
2.0 Pin Description
2.3 MICROPROCESSOR INTERFACE
Number of Pins
8
1
I/O
I/O
I
1
2
I
I
1
1
1
I
I
I
1
1
I
I
1
I
Name
Description
D0 to D7 Data is transferred between the controller and MPU via these pins
A0
Control/display data flag input. This is connected to the LSB of the
microprocessor address bus.
• When LOW, the data on D0 to D7 is command data
• When HIGH, the data on D0 to D7 is display data
RES
Reset input. Setting this pin low initializes the SED156X.
CS1,
Chip select inputs. Data input/output is enabled when CS1 is LOW
CS2
and CS2 is HIGH.
RD
Read enable input. See note 1.
WR
Write enable input. See note 2.
C86
Microprocessor interface select input.
• LOW when interfacing to 8080-series
• HIGH when interfacing to 6800-series
SI
Serial data input
SCL
Serial clock input. Data is read on the rising edge of SCL and
converted to 8-bit parallel data.
P/S
Parallel/serial data input select
P/S
Operating
Mode
Chip
Select
Data/
command
Data
I/O
Read/
write
Serial
Clock
HIGH
Parallel
CS1, CS2
A0
D0 to
D7
RD, WR
—
LOW
Serial
CS1, CS2
A0
SI
Write only
SCL
In serial mode, data cannot be read from the RAM, and D0 to D7, HZ,
RD and WR must be HIGH or LOW. In parallel mode, SI and SCL
must be HIGH or LOW.
Notes:
1. When interfacing to 8080-series microprocessors, RD is active-LOW. When interfacing to 6800-series microprocessors, they are
active-HIGH.
2. When interfacing to 8080-series microprocessors, WR is active-LOW. When interfacing to 6800-series microprocessors, read
mode is selected when WR is HIGH, and write mode is selected when WR is LOW.
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2.0 Pin Description
2.4
2.4 OSCILLATOR AND DISPLAY TIMING CONTROL
Number of Pins
I/O
Name
Description
2
I
OSC1
Using internal oscillator when M/S = “H”, connect resistor Rf to the
OSC1 and OSC2 pins. The OSC2 pin is used for output of the
oscillator amplifier.
2
I/O
OSC2
When M/S = “L”: the OSC2 pin is used for input of oscillation signal.
The OSC1 pin should be left open. Fix the CL pin to the VSS level when
using the internal oscillator circuit as the display clock.
1
I
CL
Display clock input. The line counter increments on the rising edge of
CL, and the display pattern is output on the falling edge. When using
the external display clock, OSC1 = “H”, OSC2 = “L”, and reset this LSI
by RES pin.
1
O
CLO
1
I
M/S
Display clock output. When using the internal oscillator, the clock
signal is output on this pin. Connect CLO to YSCL on the common
driver.
Master/slave select input. Master produces signals for display, and
slave receives them. This is for display synchronization.
Device
156X
M/S
Operating Internal Power
Mode
Oscillator Supply
FR SYNC OSC1 OSC2 DYO
LOW
Slave
OFF
OFF
I
I
Open
I
O
HIGH
Master
ON
ON
O
O
I
O
O
Note:
I = input mode
O = output mode
1
I/O
FR
1
I/O
SYNC
1
O
DYO
LCD AC drive signal input/output. Output is selected when M/S is
HIGH, and input is selected when M/S is LOW.
Display sync input/output. Output is selected when M/S is HIGH, and
input is selected when M/S is LOW.
Start-up output for common driver. Connect to DIO of the common
driver, such as the SED1630.
* SED1630 has a DIO input.
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2.5
2.0 Pin Description
2.5 LCD DRIVER OUTPUTS
Number of Pins
166
I/O
O
Name
O0 to
O165
Description
LCD driver outputs. O0 to O31 and O102 to O165 are selectable
segment or common outputs, determined by a selection command.
O32 to O101 are segment outputs only.
For segment outputs, the ON voltage level is given as shown in the
following table:
RAM Data
LOW
HIGH
LCD ON Voltage
FR
Normal Display
Inverse Display
LOW
V3
V5
HIGH
V2
VDD
LOW
V5
V3
HIGH
VDD
V2
For common outputs, the ON voltage is given as shown in the following table:
Scan Data
LOW
HIGH
1
O
COM1
FR
LCD ON Voltage
LOW
V4
HIGH
V1
LOW
VDD
HIGH
V5
LCD driver common output. Common outputs when the “DUTY + 1”
command is executed are as follows:
Device
“DUTY + 1” ON
“DUTY + 1” OFF
SED1560
COM64, COM48
V1 or V4
SED1561
COM32, COM24
V1 or V4
SED1562
COM16
V1 or V4
Common output special for the indicator.
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3.0
Electrical Characteristics
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3.0 Electrical Characteristics
3.1
3.1 ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Supply voltage range
Driver supply voltage range (1)
Driver supply voltage range (2)
Input voltage range
Output voltage range
Operating temperature range
Storage temperature range (TCP)
VSS
V5
V1, V2, V3, V4
VIN
V0
Topr
Tstr
Rating
–7.0 to 0.03
–6.0 to 0.3
(when triple voltage conversion)
–18.0 to 0.3
V5 to 0.3
VSS–0.3 to 0.3
VSS–0.3 to 0.3
–30 to 85
–55 to 125
Unit
V
V
V
V
V
°C
°C
Notes:
1. The voltages shown are based on VDD = 0V.
2. Always keep the condition VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 for voltages V1, V2, V3 and V4.
3. If devices are used over the absolute maximum rating, the LSIs may be destroyed permanently. It is desirable to use them under
the electrical characteristic conditions for general operation. Otherwise, a malfunction of the LSI may be caused and LSI reliability
may be affected.
4. For operating temperatures below –30°C, please consult an S-MOS engineer.
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3.2
3.0 Electrical Characteristics
3.2 DC CHARACTERISTICS
VDD = 0V, VSS = –5 ± 10%, Ta = –30 to +85°C unless otherwise noted.
Parameter
Power
voltage (1)
Recommended
operation
Symbol
Condition
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
–4.5
V
VSS
V5
V1, V2
–16.0
0.4 × V5
—
—
–3.5
VDD
V
V
V5 *2
V1, V2
V3, V4
VIHC1
V5
0.3 × VSS
—
—
0.6 × V5
VDD
V
V
V3, V4
*3
VIHC2
0.15 × VSS
—
VDD
V
*4
0.2 × VSS
0.15 × VSS
—
—
VDD
VDD
V
V
*3
*4
VSS
VSS
—
—
0.7 × VSS
0.85 × VSS
V
V
*3
*4
VIHC1
VIHC2
VSS = –2.7V
VSS = –2.7V
V ILC1
V ILC2
VSS *1
V ILC1
VSS = –2.7V
VSS
—
0.8 × VSS
V
*3
V ILC2
VOHC1
VSS = –2.7V
VSS
0.85 × VSS
V
*4
0.2 × VSS
—
—
—
—
VDD
VDD
V
*5
OSC2
V
*5
OSC2
V
*5
OSC2
V
*5
OSC2
IOH = –1 mA
VDD
VOHC2
VOHC1
VSS = –2.7V
IOH = –120 µA 0.2 × VSS
IOH = –0.5 mA 0.2 × VSS
VOHC2
VSS = –2.7V
IOH = –50 µA
0.2 × VSS
—
VDD
IOL = 1 mA
IOL = 120 µA
VSS
VSS
—
—
0.8 × VSS
IOL = 0.5 mA
IOL = 50 µA
VSS
VSS
—
—
0.8 × VSS
–1.0
—
1.0
µA
*6
–3.0
—
—
2.0
3.0
3.0
µA
*7
—
—
3.0
0.00
4.5
5.0
—
0.01
f = 1 MHz
VSS = –5V
—
15
VSS = –2.7V
V OLC1
V OLC2
V OLC1
V OLC2
ILO
RON
VSS = –2.7V
VSS = –2.7V
VIN = VDD or VSS
Ta = 25°C
V5 = –14.0V
V5 = –8.0V
0.8 × VSS
0.8 × VSS
kΩ
O0 ~ O166
*8
µA
VSS
15.0
µA
V5
5.0
18
8.0
22
pF
*3 *4
11
16
21
kHz
*9
tR
1.0
—
—
µs
*10
tRW
10
—
—
µs
*11
ISSQ
I5Q
V5 = –18.0V
Input terminal capacity
CIN
Ta = 25°C
Oscillator frequency
fOSC
Rf = 1 MΩ
±2%
Reset “L” pulse width
–5.0
Applicable
Pin
–2.4
Output leakage current
Reset time
–5.5
Unit
—
ILI
Static power consumption
Max
–6.0
Input leakage current
LCD driver ON resistance
Typ
VSS
Operational
Operational
Operating
Operational
voltage (2)
Operational
Min
(continued)
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174-3.0
3.0 Electrical Characteristics
VDD = 0V, VSS = –5 ± 10%, Ta = –30 to +85°C unless otherwise noted.
(continued)
Parameter
Symbol
Built-in power circuit
Input voltage
Condition
VSS
Amplified output voltage
V OUT
Voltage regulator
circuit operation voltage
V OUT
Voltage follower
operation voltage
If amplified 3 times
Min
Typ
Max
Unit
Applicable
Pin
–6.0
—
–2.4
V
*12
–18.0
—
—
V
V OUT
–18.0
—
–6.0
V
V OUT
V5 1
Supplied to SED1560
–16.0
—
–6.0
V
V5 2
V5 3
Supplied to SED1561
Supplied to SED1562
–16.0
–16.0
—
—
–5.0
–4.5
V
V
VREG
Ta = 25°C
–2.35
–2.5
–2.65
V
Reference voltage
Notes:
3.2
*13
* See Notes on page 22.
When dynamic current consumption (I) is displayed; the built-in power supply is on and T1 = T2 = Low.
Test conditions, unless otherwise specified: VDD = 0V, VSS = –5V ±10%, T a = –30 to 85°C
Parameter
Symbol
SED1560
SED1561
SED1562
IDD (1)
Typ
Max
V5 = –12.5V; 3 times amplified
Condition
Min
169
340
Unit Remarks
µA
V5 = –8.0V; 3 times amplified
V5 = –6.0V; 2 times amplified
124
53
250
110
µA
µA
VSS = –2.7V; 3 times amplified
V5 = –6.0V
66
130
µA
*16
Typical current consumption characteristics
• Dynamic current consumption (I), if an external clock and an external power supply are used.
(µA)
Conditions: The built-in power supply is off but
the external one is used.
40
SED1560
IDD (1) 30
(ISS +I5)
20
SED1560 ......... V5 = –12.5V
SED1561 ......... V5 = –8.0V
SED1562 ......... V5 = –6.0V
SED1561
External clock:
SED1560 ......... fCL = 4 kHz
SED1561 ......... fCL = 2 kHz
SED1562 ......... fCL = 1 kHz
SED1562
10
0
–1
–2
–3
–4
VSS
174-3.0
–5
–6
–7
(V)
Remarks:
*14
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21
3.2
3.0 Electrical Characteristics
• Dynamic current consumption (I), if the built-in oscillator and the external power supply are used.
Conditions: The built-in power supply is off but the
external one is used.
(µA)
80
SED1560 ......... V5 = –12.5V
SED1561 ......... V5 = –8.0V
SED1562 ......... V5 = –6.0V
SED1560
IDD (1) 60
(ISS +I5)
40
SED1561
Internal oscillation:
SED1562
SED1560 ......... Rf = 1 MΩ
SED1561 ......... Rf = 1 MΩ
SED1562 ......... Rf = 1 MΩ
20
0
–1
–2
–3
–4
–5
–6
–7
Remarks:
*15
(V)
VSS
• Dynamic current consumption (I), if the built-in power supply is used.
Conditions: The built-in power supply is on and
T1 = T2 = Low.
200
(µA)
SED1560 ......... V5 = –12.5V;
3 times amplified
SED1560
150
IDD (1)
SED1561
SED1561 ......... V5 = –8.0V;
3 times amplified
100
SED1562 ......... V5 = –6.0V;
2 times amplified
SED1562
50
Internal oscillation:
0
–1
–2
–3
–4
–5
VSS
–6
SED1560 ......... Rf = 1 MΩ
SED1561 ......... Rf = 1 MΩ
SED1562 ......... Rf = 1 MΩ
–7
(V)
Remarks:
*16
Notes:
*1. A wide range of operating voltage is possible, but considerable
voltage variation during MPU access is not guaranteed.
the SED156* is usually operable after “tr” time.
*11. Specifies the minimum pulse width of RES signal. The Low pulse
greater than “tRW” must be entered for reset.
*2. The operating voltage range of the VSS and V5 systems (see Figure
3.3). The operating voltage range is applied if an external power
supply is used.
*12. If the voltage is amplified three times by the built-in power circuit,
the primary power VSS must be used within the input voltage range.
*3. Pins A0, D0 to D7, RD (E),WR (R/W), CS1, CS2, FR, SYNC, M/S,
C86, SI, P/S, T1 AND T2.
*13. The V5 voltage can be adjusted within the voltage follower operating range by the voltage regulator circuit.
*4. Pins CL, SCL, and RES.
*5. Pins D0 to D7, FR, SYNC, CL0, and DY0
*6. Pins A0, RD (E), WR (R/W), CS1, CS2, CL, M/S, RES, C86, SI,
SCL, P/S, T1, and T2.
*7. Applied if pins D0 to D7, FR, and SYNC are high impedance.
*14, 15, 16. Indicates the current consumed by the separate IC. The
current consumption due to the LCD panel capacity and wiring
capacity is not included.
The current consumption is shown if the checker is used, the
display is turned on, the output status of Case 6 is selected, and the
SED1560 is set to 1/64 duty, the SED1561 is set to 1/32 duty, and
the SED1562 is set to 1/64 duty.
*8. The resistance when the 0.1 -volt voltage is applied between the
“On” output terminal and each power terminal (V1, V2, V3 or V4).
It must be within the operating voltage (2).
*14. Applied if an external clock is used and if not accessed by the MPU.
*9. The relationship between the oscillation frequency, frame and Rf
value (see Figure 3.2).
*15. Applied if the built-in oscillation circuit is used and if not accessed
by the MPU.
*10. “tr” (reset time) indicates the period between the time when the RES
signal rises and when the internal circuit has been reset. Therefore,
*16. Applied if the built-in oscillation circuit and the built-in power circuit
are used (T1 = T2 = Low) and if not accessed by the MPU.
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174-3.0
3.0 Electrical Characteristics
3.2
The relationship between oscillator frequency fOSC
and LCD frame frequency fF is obtained from the
following expression:
VSS = –5V
Ta = 25°C
40
30
[KHz]
fOSC
Table 3.1
20
Device
10
SED1560
0
0.5
1.0
1.5
2.0
2.5
SED1561
Rf [MΩ]
SED1562
Figure 3.1
Oscillator frequency vs. frame vs. Rf
[SED1560 Series]
Duty
fF
1/64
1/48
fOSC/256
fOSC/192
1/32
1/24
1/16
fOSC/256
fOSC/192
fOSC/256
(fF indicates not fF signal cycle but cycle of LCD AC.)
200
duty 1/64 SED1560
duty 1/48
[Hz]
100
fF
duty 1/32 SED1561
duty 1/24
duty 1/16 SED1562
0
2
4
6
8
fCL [KHz]
Figure 3.2 External clock (fCL) vs. frame frequency [SED1560 Series]
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23
3.2 – 3.3.1
3.0 Electrical Characteristics
10
–20
5.0V
–16
1
–15
2.7V
–13
[V]
V5
[mA]
IDD (2)
–10
–5
0
0.1
0.01
–2
–2.4 –3.0
–4
–6
–8
0
VSS [V]
0.01
0.1
1
10
fcyc [MHz]
Figure 3.3
Operating voltage range for VSS and V5
Figure 3.4
Power consumption during CPU access cycle
(IDD [2])
3.3 AC CHARACTERISTICS
3.3.1 Reset
Table 3.5 Reset
Parameter
Reset time
Reset LOW-level
pulsewidth
Symbol
Condition
tR
tR is measured from the rising edge
of RES. The SED156X resumes
normal operating mode after a reset.
tRW
Min
Rating
Typ
Max
1.0
—
—
µs
1.0
—
—
µs
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Unit
174-3.0
3.0 Electrical Characteristics
3.4
3.4 DISPLAY CONTROL TIMING
CL
tWLCL
tf
tWHCL
tDFR
tr
FR
tDSNC
SYNC
tDOH
tDOL
tCDH
tCDL
DYO
CLO
Figure 3.5 Display control timing
Display Control Input Timing
Parameter
CL LOW-level pulsewidth
CL HIGH-level pulsewidth
CL rise time
CL fall time
FR delay time
SYNC delay time
Parameter
CL LOW-level pulsewidth
CL HIGH-level pulsewidth
CL rise time
CL fall time
FR delay time
SYNC delay time
Symbol
tWLCL
t WHCL
tr
tf
t DFR
t DSNC
Symbol
tWLCL
t WHCL
tr
tf
t DFR
t DSNC
1. Effective only when the SED156X is in the master mode.
2. The FR/SYNC delay time input timing is provided in the
slave operation.
174-3.0
Condition
Condition
VSS = –5.5 to –4.5V, Ta = –30 to 85°C
Rating
Unit
Min
Typ
Max
35
—
—
µs
35
—
—
µs
—
30
—
ns
—
30
—
ns
–1.0
—
1.0
µs
–1.0
—
1.0
µs
VSS = –4.5 to –2.7V, Ta = –30 to 85°C
Rating
Unit
Min
Typ
Max
35
—
—
µs
35
—
—
µs
—
40
—
ns
—
40
—
ns
–1.0
—
1.0
µs
–1.0
—
1.0
µs
The FR/SYNC delay time output timing is provided in the
master operation.
3. Each timing is based on 20% and 80% of VSS.
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25
3.4
3.0 Electrical Characteristics
Display Control Output Timing
Parameter
FR delay time
SYNC delay time
DYO LOW-level delay time
DYO HIGH-level delay time
CLO to DYO LOW-level
delay time
CLO to DYO HIGH-level
delay time
Parameter
FR delay time
SYNC delay time
DYO LOW-level delay time
DYO HIGH-level delay time
CLO to DYO LOW-level
delay time
CLO to DYO HIGH-level
delay time
Symbol
tDFR
tDSNC
tDOL
tDOH
tCDL
tCDH
Symbol
tDFR
tDSNC
tDOL
tDOH
tCDL
tCDH
Condition
CL = 50 pF
CL = 100 pF
SED156X operating in
master mode only
SED156X operating in
master mode only
Condition
CL = 50 pF
CL = 100 pF
SED156X operating in
master mode only
SED156X operating in
master mode only
VSS = –5.5 to –4.5V, Ta = –30 to 85°C
Rating
Unit
Min
Typ
Max
—
60
150
ns
—
60
150
ns
—
70
160
ns
—
70
160
ns
—
40
100
ns
—
40
100
ns
VSS = –4.5 to –2.7V, Ta = –30 to 85°C
Rating
Unit
Min
Typ
Max
—
120
240
ns
—
120
240
ns
—
140
250
ns
—
140
250
ns
—
100
200
ns
—
100
200
ns
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174-3.0
3.0 Electrical Characteristics
3.5
3.5 SYSTEM BUSES: READ/WRITE CHARACTERISTICS I (80-SERIES MPU)
tAH8
A0
tAW8
tCYC8
tCCLR
tCCLW
WR, RD, (CS)
tf
tr
tCCHR
tCCHW
tDS8
tDH8
D0 to D7
(Write)
tACC8
tCH8
D0 to D7
(Read)
VSS = –5.0 ± 10%, Ta = –30 to 85°C
Parameter
Address hold time
Address setup time
System cycle time
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
Data setup time
Data hold time
RD access time
Output disable time
Input signal change time
174-3.0
Signal
A0, CS
WR
RD
WR
RD
D0 ~ D7
Symbol
t AH8
t AW8
tCYC8
t CCLW
t CCLR
tCCHW
tCCHR
t DS8
tDH8
tACC8
tCH8
tr, t f
Condition
CL = 100pF
Min
10
10
200
22
77
172
117
20
10
—
10
—
Max
—
—
—
—
—
—
—
—
—
70
50
15
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Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
27
3.5 – 3.6
3.0 Electrical Characteristics
VSS = –2.7 to –4.5V, Ta = –30 to 85°C
Parameter
Address hold time
Address setup time
System cycle time
Control L pulse width (WR)
Control L pulse width (RD)
Control H pulse width (WR)
Control H pulse width (RD)
Data setup time
Data hold time
RD access time
Output disable time
Input signal change time
Notes:
Signal
A0, CS
Symbol
tAH8
tAW8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
tDH8
tACC8
tCH8
tr, t f
WR
RD
WR
RD
D0 ~ D7
Condition
Min
25
25
450
44
194
394
244
40
20
—
10
—
CL = 100pF
Max
—
—
—
—
—
—
—
—
—
140
100
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. When using the system cycle time in the high-speed mode, it is limited by tr + tf ≤ (tCYC8 – tCCLW – t CCHW) or tr + tf ≤ (tCYC8 –
tCCLR – tCCHR)
2. All signal timings are limited based on 20% and 80% of VSS voltage.
3. Read/write operation is performed while CS (CS1 and CS2) is active and the RD or WR signal is in the low level.
If read/write operation is performed by the RD or WR signal while CS is active, it is determined by the RD or WR signal timing.
If read/write operation is performed by CS while the RD or WR signal is in the low level, it is determined by the CS active
timing.
3.6 SYSTEM BUSES: READ/WRITE CHARACTERISTICS II (68-SERIES MPU)
tCYC6
E
tEWLR
tEWLW
tAW6
tEWHR
tEWHW
tr
tAH6
tf
A0, RW
tDS6
tAH6
tDH6
D0 ~ D7
(WRITE)
tACC6
tOH6
D0 ~ D7
(READ)
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174-3.0
3.0 Electrical Characteristics
3.6
VSS = –5.0 ± 10%, Ta = –30 to 85°C
Parameter
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
Output disable time
Access time
READ
WRITE
READ
Enable L pulse
width
WRITE
Input signal change time
Enable H pulse
width
Signal
(A0)
R/W
D0 ~ D7
E
E
Symbol
tCYC6
t AW6
t AH6
t DS6
tDH6
t OH6
tACC6
t EWHR
t EWHW
tEWLR
tEWLW
tr, t f
Condition
CL = 100pF
Min
200
10
10
20
10
10
—
77
22
117
172
—
Max
—
—
—
—
—
50
70
—
—
—
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VSS = –2.7 to +4.5V, T a = –30 to 85°C
Parameter
System cycle time
Address setup time
Address hold time
Data setup time
Data hold time
Output disable time
Access time
Signal
Symbol
A0, CS
tCYC6
(CS1, CS2)
t AW6
R/W
t AH6
t DS6
tDH6
D0 ~ D7
t OH6
tACC5
READ
t EWHR
Enable H pulse
E
width
WRITE
t EWHW
READ
tEWLR
Enable L pulse
E
width
WRITE
tEWLW
Input signal change time
tr, t f
Notes:
Condition
CL = 100pF
Min
450
25
25
40
20
20
—
154
44
244
394
—
Max
—
—
—
—
—
100
140
—
—
—
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. When using the system cycle time in the high-speed mode, it is limited by tr + tf ≤ (tCYC6 – tEWLW – tEWHW) or tr + tf ≤ (tCYC6
– tEWLR – tEWHR)
2. All signal timings are limited based on 20% and 80% of VSS voltage.
3. Read/write operation is performed while CS (CS1 and CS2) is active and the E signal is in the high level.
If read/write operation is performed by the E signal while CS is active, it is determined by the E signal timing.
If read/write operation is performed by CS while the E signal is in the high level, it is determined by the CS active timing.
174-3.0
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29
3.7
3.0 Electrical Characteristics
3.7 SERIAL INTERFACE
tCSS
tCSH
CS
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tf
tr
tSDS
tSHW
tSDH
SI
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174-3.0
3.0 Electrical Characteristics
3.7
VSS = –5.0 ± 10%, Ta = –30 to 85°C
Parameter
Serial clock cycle
SCL high pulse width
SCL low pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
Signal
SCL
A0
SI
CS
Input signal change time
Symbol
tSCYC
tSHW
t SLW
tSAS
t SAH
t SDS
tSDH
t CSS
tCSH
tr, t f
Condition
Min
500
150
150
120
200
120
50
30
400
—
Max
—
—
—
—
—
—
—
—
—
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VSS = –2.7 to –4.5V, Ta = –30 to 85°C
Parameter
Serial clock cycle
SCL high pulse width
SCL low pulse width
Address setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
Input signal change time
Note:
Signal
SCL
A0
SI
CS
Symbol
tSCYC
tSHW
t SLW
tSAS
t SAH
t SDS
tSDH
t CSS
tCSH
tr, t f
Condition
Min
1000
300
300
250
400
250
100
60
800
—
Max
—
—
—
—
—
—
—
—
—
50
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*2. All signal timings are limited based on 20% and 80% of VSS voltage.
174-3.0
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THIS PAGE INTENTIONALLY BLANK
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174-3.0
4.0
Functional
Description
174-3.0
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THIS PAGE INTENTIONALLY BLANK
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174-3.0
4.0 Functional Description
4.0 – 4.1.3
4.1 MICROPROCESSOR INTERFACE
4.1.1 Parallel/Serial Interface
Table 4.1 Parallel/serial Interface Selection
P/S
HIGH
LOW
Input Type
Parallel
Serial
CS1
CS1
CS1
CS2
CS2
CS2
A0
A0
A0
RD
RD
×
WR
WR
×
C86
C86
×
SI
×
SI
SCL
×
SCL
D0 to D7
D0 to D7
(Hi-Z)
× = don’t care
Parallel data can be transferred in either direction
between the controlling microprocessor and the
SED1560 Series via an 8-bit I/O buffer (D0 to D7).
Serial data can be sent from the microprocessor to the
SED1560 Series through the serial data input (SI), but
not from the SED1560 Series to the microprocessor.
The parallel or serial interface is selected by
setting P/S as shown in Table 4.1.
Table 4.3 Parallel Data Transfer
Common
6800
Series
A0
R/W
RD
WR
1
1
0
1
Display data read out
1
0
1
0
Display data write
0
1
0
1
Status read
0
0
1
0
Write to internal register
(command)
8080 Series
For the parallel interface, the type of microprocessor
is selected by C86 as shown in Table 4.2.
Table 4.2 Microprocessor Selection for Parallel
Interface
C86
MPU
Bus Type
CS1 CS2 A0
HIGH
6800-series
CS1 CS2 A0
LOW
8080-series
CS1 CS2 A0
RD WR
E
D0 to D7
R/W D0 to D7
RD WR
D0 to D7
4.1.2 Parallel Interface
A0, WR (or R/W) and RD (or E) determine the type of
parallel data transfer. See Table 4.3.
Description
4.1.3 Serial Interface
The serial interface consists of an 8-bit shift register and
a 3-bit counter. These are reset when CS1 is HIGH and
CS2 is LOW. When these states are reversed, serial
data and clock pulses can be received from the microprocessor on SI and SCL respectively.
Serial data is read on the rising edge of SCL and must
be input at SI in the sequence D7 to D0. On every
eighth clock pulse, the data is transferred from the
shift register and processed as 8-bit parallel data.
Input data is display data when A0 is HIGH and command data when A0 is LOW. A0 is read on the rising
edge of every eighth clock signal. See Figure 4.1.
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4.1.3 – 4.2
4.0 Functional Description
CS1
CS2
SI
SCL
D7
1
D6
2
D5
3
D4
4
D3
5
D2
6
D1
7
D0
8
D7
9
D6
10
A0
Figure 4.1 Serial interface timing
4.1.4 Chip Select Inputs
Data transfer between the microprocessor and the
SED1560 Series is enabled when CS1 is LOW and
CS2 is HIGH. If these pins are set to any other values,
D0 to D7 are in high impedance state and will not
accept data.
4.2 DATA TRANSFER
To match the timing of the display data RAM and
registers to that of the controlling microprocessor, the
SED1560 Series uses an internal data bus and bus
buffer. When the microprocessor reads the contents
of RAM, the data for the initial read cycle is first stored
in the bus buffer (dummy read cycle). On the next read
cycle, the data is read from the bus buffer onto the
microprocessor bus. At the same time, the next block
of data is transferred from RAM to the bus buffer.
Likewise, when the microprocessor writes data to display data RAM, the data is first stored in the bus buffer
before being written to RAM at the next write cycle.
When writing data from the microprocessor to RAM,
there is no delay since data is automatically transferred from the bus buffer to the display data RAM. If
the data rate is required to slow down, the microprocessor can insert a NOP instruction which has the
same effect as executing a wait procedure.
When a sequence of address sets is executed, a
dummy read cycle must be inserted between each
pair of address sets. This is necessary because the
addressed data from the RAM is delayed one cycle by
the bus buffer, before it is sent to the microprocessor.
A dummy read cycle is thus necessary after an
address set and after a write cycle.
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174-3.0
4.0 Functional Description
4.2
WR
MPU
DATA
N
Bus
holder
N+1
N
N+2
N+1
N+3
N+2
N+3
Internal
timing
WR
Figure 4.2 Write timing
WR
RD
MPU
DATA
N
N
Address set
n
Dummy read
n+1
Data read n
Data read (n+1)
WR
RD
Internal
timing
Column
address
Bus
holder
N
N
N+1
n
N+2
N+1
N+2
Figure 4.3 Read timing
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4.3 – 4.6
4.0 Functional Description
4.3 STATUS FLAG
4.5 COLUMN ADDRESS COUNTER
The SED1560 Series has a single bit status flag, D7.
When D7 is HIGH, the device is busy and will accept
only a Status Read command. It is not necessary for
the microprocessor to check the status of this bit
before each command, if enough time is allowed for
the last cycle to be completed.
The column address counter is an 8-bit presettable
counter that provides the column address to display
data RAM. See Figure 4.4. It is incremented by 1 each
time a read or write command is received. The counter
automatically stops at the highest address, A6H. The
contents of the column address counter are changed
by the Column Address Set command. This counter is
independent of the page address register.
4.4 DISPLAY DATA RAM
The SED1560 Series stores the display data sent
from the microcomputer in the built-in display data
RAM (166 × 65 bits) and generates the LCD drive
signals. It is a 166-column × 65-row addressable array
as shown in Figure 4.4.
The 65 rows are divided into 8 pages of 8 lines and a
ninth page with a single line (D0 only). Data is read
from or written to the 8 lines of each page directly
through D0 to D7.
The microprocessor reads from and writes to RAM
through the I/O buffer. Since the LCD controller operates independently, data can be written to RAM at the
same time as data is being displayed, without causing
the LCD to flicker.
When the Select ADC command is used to select
inverse display operation, the column address decoder inverts the relationship between the RAM column data and the display segment outputs.
4.6 PAGE ADDRESS REGISTER
The 4-bit page address register provides the page
address to display data RAM. The contents of the
register are changed by the Page Address Set command.
Page address 8 (1000) is a special use RAM area for
the indicator.
The time taken to transfer data is very short, because
the microprocessor inputs D0 to D7 correspond to the
LCD common lines as shown in Figure 4.5. Large
display configuration can thus be created using multiple SED1560 Series devices.
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174-3.0
4.0 Functional Description
0 0
0 1
0 0
1 0
0 0
1 1
0 1
0 0
0 1
0 1
0 1
1 0
1 1
1 0
0 0
Page 0
Page 1
Page 2
Page 3
Page 4
Page 5
Page 6
Page 7
Common
address
1/64
Start
1/32
Page 8
ADC
LCD
OUT DO DO
=1 =0
O0 A5 O0
O1 A4 O1
O2 A3 O2
O3 A2 O3
O4 A1 O4
O5 A0 O5
O6 9F O6
O7 9E O7
0 1
00H
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
to
to
to
COM 0
COM 1
COM 2
COM 3
COM 4
COM 5
COM 6
COM 7
COM 8
COM 9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM 1
Note:
For 1/65
and 1/33 display
duty cycles, page 9
is accessed following 1BH and 3BH,
respectively.
A2
A3
A4
A5
0 0
Line
address
Column address
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
O3
O2
O1
O0
0 0
DATA
O162
O163
O164
O165
Page
address
4.6
Figure 4.4 Display data RAM addressing
D0
D1
D2
D3
D4
1
0
1
0
0
COM0
COM1
COM2
COM3
COM4
Figure 4.5 RAM-to-LCD data transfer
174-3.0
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39
4.7 – 4.8
4.0 Functional Description
4.7 INITIAL DISPLAY LINE REGISTER
The Initial Display Line register stores the address of
the RAM line that corresponds to the first (normally
the top) line (COM0) of the display. See Figure 4.4.
The contents of this 6-bit register are changed by the
Initial Display Line command. At the start of each LCD
frame, synchronized with SYNC, the initial line is
copied to the line counter. The line counter is then
incremented on the CL clock signal once for every
display line. This generates the line addresses for the
transfer of the 166 bits of RAM data to the LCD drivers.
the six different LCD driver arrangements.
If a 1/65 or 1/33 display duty cycle is selected by the
DUTY+1 command, the line address corresponding
to the 65th or 33rd SYNC signal is changed and the
indicator special-use line address is selected. If the
DUTY+1 command is not used, the indicator specialuse line address is not selected.
When COM outputs are assigned to the output drivers, the unused RAM area is not available. However,
all RAM column addresses can still be accessed by
the microprocessor.
4.8 OUTPUT SELECTION CIRCUIT
Cases 1 to 6 are determined according to the three
lowest bits in the output status register in the output
selection circuit. The COM output scanning direction
can be selected by setting bit D3 in the output status
register to “H” or “L”.
The number of common (COM) and segment (SEG)
driver outputs can be selected to fit different LCD
panel configurations by the output selection circuit.
There are 70 segment-only outputs (O32 to O101)
and 96 common or segment dual outputs (O0 to O31
and O102 to O165). A command selects the status of
the dual common/segment outputs. Figure 4.6 shows
ADC
(D0)
L
H
0
165
The necessary LCD driver voltage is automatically
allocated to the COM/SEG dual outputs when their
function is determined by the output selection circuit.
The SED1560 selects Case 1, 2 or 6 while the
SED1561 selects Case 3, 4, 5 or 6. The COM/SEG
output status for the SED1562 is fixed and so cannot
be selected.
Since duty setting and output selection are independent, the appropriate duty must be selected for
each case.
When the DUTY+1 command is executed, pin
COM1 becomes as shown in Figure 4.4 irrelevant to output selection.
165
0
Column address
Display data RAM
Case 1
Case 2
Case 3
Case 4
Case 5
Case 6
SED1562
102 segments
32 commons
32 commons
102 segments
134 segments
134 segments
134 segments
166 segments
150 segments
16 commons
O0
O15
O31
O101
64 commons
32 commons
32 commons
16 commons
16 commons
O133
O149
O165
Figure 4.6 Output configuration selection
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174-3.0
4.0 Functional Description
Since master/slave operation and the output selection circuit are completely independent in the
SED1560 Series, a chip on either the master or
slave side can be allocated to the COM output
function in multi-chip configuration.
4.8
The LCD driver outputs shown in Table 4.5 become
ineffective when the SED1560 or SED1561 is used
with 1/48 or 1/24 duty, respectively. In this case,
ineffective outputs are used in the open state.
Table 4.4
SED1560
Duty
COMI function
1/64
COM64
SED1561
1/48
COM48
1/32
COM32
1/24
COM24
SED1562
1/16
COM16
Table 4.5
Case 1
SED1560
Case 2
Case 3
SED1561
Case 4
Case 5
174-3.0
D3
0
1
0
1
0
1
0
1
0
1
Output Status Register
D2
D1
1
0
1
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
0
0
D0
1
1
0
0
1
1
0
0
1
1
Ineffective Output
O150 ~ O165
O102 ~ O117
O150 ~ O165
O16 ~ O31
O0 ~ O7
O23 ~ O31
O158 ~ O165
O134 ~ O141
O158 ~ O165
O8 ~ O15
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41
4.9 – 4.10
4.0 Functional Description
4.9 SED1560 OUTPUT STATUS
The SED1560 selects any output status from Cases 1, 2 and 6.
1/64 Duty (Display Area 102 × 64)
Case
1
2
6
Status Register
LCD Driver Output
D3
D2
D1
D0
O0
O31
O32
O101
O102
O133
O134
O165
0
1
0
1
COM0
COM63
1
1
0
1
COM63
COM0
0
1
0
0
COM31
COM0
SEG102
COM32
COM63
1
1
0
0
COM32
COM63
SEG102
COM31
COM0
—
0
0
0
SEG166
1/48 Duty (Display Area 102 × 48)
Case
1
2
6
Status Register
LCD Driver Output
D3
D2
D1
D0
0
1
0
1
1
1
0
1
0
1
0
0
1
1
0
0
—
0
0
0
O0
O31
O32
O101
O102
O133
COM0
O134
O165
COM47
COM47
COM31
COM32
COM0
SEG102
47
COM0
COM32
SEG102
47
COM31
COM0
SEG166
4.10 SED1561 OUTPUT STATUS
The SED1561 selects any output status from Cases 3, 4, 5 and 6.
1/32 Duty (Display Area 134 × 32)
Case
3
4
5
6
Status Register
LCD Driver Output
D3
D2
D1
D0
O0
O15 O16 O31 O32
0
0
1
1
COM31
COM0
SEG134
1
0
1
1
COM0
COM31
SEG134
0
0
1
0
SEG134
COM0
COM31
1
0
1
0
SEG134
COM31
COM0
0
0
0
1
15
1
0
0
1
COM16
—
0
0
0
COM0
31
O133 O134 149 150 O165
SEG134
COM16 31
SEG134
15
COM0
SEG166
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174-3.0
4.0 Functional Description
4.10 – 4.12.3
1/24 Duty (Display Area 134 × 24)
Case
3
4
5
6
Status Register
LCD Driver Output
D3
D2
D1
D0
0
0
1
1
O0
O15 O16 O31 O32
COM23
COM0
O133 O134 149 150 O165
COM0
SEG134
1
0
1
1
0
0
1
0
COM23
SEG134
1
0
1
0
0
0
0
1
15 COM0
SEG134
16 23
1
0
0
1
16 23
SEG134
15 COM0
—
0
0
0
SEG134
COM0
SEG134
COM23
COM23
COM0
SEG166
4.11 SED1562 OUTPUT STATUS
COM/SEG output status of the SED1562 is fixed.
1/16 Duty (Display Area 150 × 16)
LCD Driver Output
O0
O149
SEG150
O150
15
O165
COM0
4.12 DISPLAY TIMERS
4.12.1 Line Counter and Display Data Latch
Timing
The display clock, CL, provides the timing signals for
the line counter and the display data latch. The RAM
line address is generated synchronously using the
display clock. The display data latch synchronizes the
166-bit display data with the display clock.
The timing of the LCD panel driver outputs is
independent of the timing of the input data from
the microprocessor.
4.12.2 FR and SYNC
The LCD AC signal, FR, and the synchronization
signal, SYNC, are generated from the display clock.
The FR controller generates the timing for the LCD
panel driver outputs. Normally, 2-frame wave patterns are generated, but n-line inverse wave patterns
can also be generated. These produce a high-quality
display if n is based on the LCD panel being used.
174-3.0
SYNC synchronizes the timing of the line counter and
common timers. It is also needed to synchronize the
frame period and a 50% duty clock.
In a multiple-chip configuration, FR and SYNC are
inputs. The SYNC signal from the master synchronizes the line counter and common timing of the slave.
4.12.3 Common Timing Signals
The internal common timing and the special-use
common driver start signal, DYO, are generated from
CL. As shown in Figures 4.7 and 4.8, DYO outputs a
HIGH-level pulse on the rising edge of the CL clock
pulse that precedes a change on SYNC. DYO is
generated by both the SED1560 Series devices,
regardless of whether the device is in master or slave
mode. However, when operating in slave mode, the
device duty and the external SYNC signal must be the
same as that of the master. In a multiple-chip configuration, FR and SYNC must be supplied to the slave
from the master.
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4.13
4.0 Functional Description
Table 4.6 Master and Slave Timing Signal Status
Part Number
SED1560
Series
Mode
FR
Master
Output
Slave
Input
SYNC
CLO
DYO
CL
Output
Output
Output
Input
High
Imped- Output
ance
4.13 TWO-FRAME AC DRIVER WAVEFORM (SED1561, 1/32 DUTY)
31 32
1
2
3
4
5
6
27 28 29 30 31 32
1
2
3
4
5
CL
SYNC
FR
DYO
COM0
VDD
V1
V2
V3
COM1
VDD
V1
V2
V3
RAM
data
VDD
V2
V3
V5
SEG n
Figure 4.7 Frame driver timing for duty 1/32
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174-3.0
4.0 Functional Description
4.14
4.14 n LINE INVERSE DRIVER WAVEFORM (n=5, LINE INVERSE REGISTER 4)
31 32
1
2
3
4
5
6
27 28 29 30 31 32
1
2
3
4
5
CL
SYNC
FR
DYO
COM0
VDD
V1
V4
V5
COM1
VDD
V1
V4
V5
RAM
data
VDD
V2
V3
V5
SEG n
Note: When n = 5, the line inversion register is set to 4.
Figure 4.8 Line inverse driver timing
174-3.0
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4.15 – 4.20
4.0 Functional Description
4.15 DISPLAY DATA LATCH
4.19 OSCILLATOR CIRCUIT
Display data is transferred from RAM to the LCD
drivers through the display data latch. This latch is
controlled by the Display ON/OFF, Display All Points
ON/OFF and Normal/Inverse Display commands.
The low power consumption type CR oscillator
adjusting the oscillator frequency by use of only
oscillator resistor Rf is used as a display timing
signal source or clock for the voltage raising circuit
of the LCD power supply.
These commands do not alter the data.
4.16 LCD DRIVER
The LCD driver converts RAM data into the 167
outputs that drive the LCD panel. There are 70 segment outputs, 96 segment or common dual outputs,
and a COM1 output for the indicator display.
Two shift registers for the common/segment drivers
are used to ensure that the common outputs are output in the correct sequence. The driver output voltages depend on the display data, the common scanning signal and FR.
The oscillator circuit is available only in the master
operation mode. When a signal from the oscillator circuit
is used for display clock, fix the CL pin to the VSS level.
When the oscillator circuit is not used, fix the OSC1 or
OSC2 pin to the VDD or VSS level, respectively.
The oscillator signal frequency is divided and output
from the CL0 pin as display clock. The frequency is
divided to one-fourth, one-eighth, or one-sixteenth in
the SED1560, SED1561, or SED1562, respectively.
4.20 FR CONTROL CIRCUIT
The LCD driver voltage supplied to the LCD driver
outputs is selected using FR signal.
4.17 DISPLAY DATA LATCH CIRCUIT
The display data latch circuit temporarily stores the
output display data from the display data RAM to
the LCD driver circuit in each common period.
Since the Normal/Inverse Display, Display ON/
OFF and Display All Points ON/OFF commands
control the data in this latch, the data in the display
data RAM remains unchanged.
4.18 LCD DRIVER CIRCUIT
This multiplexer generates 4-value levels for the LCD
driver, having 167 outputs of 70 SEG outputs, 96
SEG/COM dual outputs and a COM output for the
indicator display. The SEG/COM dual outputs have a
shift register and sequentially transmit COM scanning signals. The LCD driver voltage is output according to the combination of display data, COM scanning
signal and FR signal. Figure 4.9 shows a typical SEG/
COM output waveform.
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174-3.0
4.0 Functional Description
FR
(SYNC)
COM0
COM1
COM2
COM0
COM3
COM4
COM5
COM6
COM1
COM7
COM8
COM9
COM2
COM10
COM11
COM12
COM13
SEG0
COM14
COM15
SEG0 SEG1 SEG2 SEG3 SEG4
SEG1
COM0
to
SEG0
COM0
to
SEG1
4.20
VDD
VSS
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
VDD
V1
V2
V3
V4
V5
V5
V4
V3
V2
V1
VDD
–V1
–V2
–V3
–V4
–V5
V5
V4
V3
V2
V1
VDD
–V1
–V2
–V3
–V4
–V5
Figure 4.9 Example of segment and common timing
174-3.0
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47
4.21 – 4.22
4.0 Functional Description
When (T1, T2) = (H, L), the boosting circuit does not
work and open the boosting circuit terminals (CAP1+,
CAP1–, CAP2+ and CAP2–) and apply liquid crystal
driving voltage to the VOUT terminals from outside.
4.21 POWER SUPPLY CIRCUIT
The SED1560 Series has an internal DC/DC converter to generate LCD bias voltages. The internal
power supply circuit can be used only when the
controller operates in master mode. The power circuit
consists of a triple boosting circuit, a voltage regulation circuit and a low power voltage follower circuit.
When (T1, T2) = (H, H), the boosting circuit and
voltage regulation circuit do not work and open the
boosting circuit terminals and the VR terminals and
apply liquid crystal driving voltage to the V5, and leave
the VOUT pin open.
The power circuit built into SED1560 Series is set for
smaller scale liquid crystal panels and it is not suitable when the picture element is larger or to drive a
liquid crystal panel with larger indication capacity
using multiple chips. It is recommended that an external power supply is used when using a liquid crystal
panel with a larger load capacity.
4.22 TRIPLER BOOSTING CIRCUIT
By connecting capacitors C1 between CAP1+ and
CAP1–, CAP2+ and CAP2– and VSS – VOUT, the
electric potential between VDD – VSS is boosted to the
triple toward negative side and outputted from the
VOUT terminal. When a double boosting is required,
disconnect the capacitor between CAP2+ and CAP2–
and short-circuit the CAP2– and VOUT terminals to
obtain output boosted to the double out of the VOUT (or
CAP2–) terminal.
The power supply circuit can be controlled by the builtin power ON/OFF command. When the built-in power
is turned off, the boosting circuit, voltage regulation
circuit and voltage follower circuit all go open. In this
case, the liquid crystal driving voltage V1, V2, V3, V4
and V5 should be supplied from outside and the
terminals CAP1+, CAP1–, CAP2+, CAP2–, VOUT and
VR should be kept opened.
Signals from the oscillation circuit are used in the
boosting circuit and it then is necessary that the
oscillation circuit is in operation.
Various functions of the power circuit can be selected
by combinations of the setting of the T1 and T2. It is
also possible to make a combined use of the external
power supply and a portion of the functions of the builtin power supply.
Electric potentials by the boosting functions are shown
in Figure 4.10 and 4.11.
Table 4.7
T1
T2
Voltage
Converter
Circuit
L
L
H
H
L
H
L
H
O
O
X
X
Voltage
Regulation
Circuit
V/F
Circuit
O
O
O
X
O
O
O
O
External
Voltage
Input
Voltage
Converter
Circuit
Terminals
Voltage
Regulation
Terminals
—
—
VOUT
V5
OPEN
OPEN
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OPEN
174-3.0
4.0 Functional Description
4.22 – 4.23
VDD = 0V
(VCC = +5V) VDD = 0V
VSS = –5V
(GND) VSS = –5V
VOUT = 2vss = –10V
VOUT = 3vss = –15V
Figure 4.10
Electric potentials of double boosting
Figure 4.11
Electric potentials of triple boosting
4.23 VOLTAGE REGULATION CIRCUIT (SOFTWARE CONTRAST ADJUSTMENT FUNCTION IS
NOT USED)
The boosted voltage coming out from VOUT is adjusted to become the liquid crystal driving voltage V5
via the voltage regulation circuit. V5 voltage can be
regulated within a range of |V5| < |VOUT| by adjustment of resistors Ra and Rb and it may be calculated
by the following equation:
Rb
V5 = (1 +
) VREG
Ra
Equation 4.1
wherein VREG is the constant voltage source inside
the IC and the voltage is constant at VREG ≈ 2.5V.
Voltage regulation of the V5 output is made by connecting variable resistors between VR, VDD and V5.
For fine adjustment of the V5 voltage, a combination
of fixed resistors R1 and R3 and a variable resistor R2
is needed.
The voltage regulation circuit renders a temperature
gradient, after VREG output, of about –0.17% / °C, but
when any other temperature gradient is needed,
connect a thermistor in series with the output voltage
regulating resistors.
Since the VR terminal has a high input impedance, it
is necessary to take some noise suppression measures, such as using the shortest length wiring or
shielded wiring.
VDD
VREG
Ra
+
Examples of settings of R1, R2, and R3:
V5
VR
• R1 + R2 + R3 = 5 MΩ (determined by the
current required to flow between VDD and V5)
• Voltage variation range by R2: –11V ~ –13V
(determined based on the characteristics of
the liquid crystal being used)
Using the above conditions and Equation 4.1, the
following calculations can be made:
–
Rb
Figure 4.12
Voltage regulation circuit
R1 = 0.947 MΩ
R2 = 0.174 MΩ
R3 = 3.879 MΩ
174-3.0
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49
4.24
4.0 Functional Description
4.24 VOLTAGE REGULATION CIRCUIT USING SOFTWARE CONTRAST ADJUSTMENT
CONTROL FUNCTION
By using software contrast adjustment control function, it is possible to control the liquid crystal driving
voltage V5 by inputting corresponding commands to adjust the contrast of the liquid crystal display.
With such an electronic contrast control function, setting 5-bit data to the electronic contrast control
register will make available 32 states of voltages from which one voltage level can be selected for the
liquid crystal driving voltage V5.
When using the software contrast control function, it is necessary to execute built-in power supply on
command after one of (T1, T2) = (L, L), (T1, T2) = (L, H), or (T1, T2) = (H, L) is set.
Example of Constant Setting When Using the Software Contrast Adjustment Control Function
(1) Determine a V5 voltage setting range by the electronic contrast control.
Liquid crystal driving voltage ...........................V5 – 10V max. to –15V min.
V5 variable voltage width ................................ 4V
(2) Determine Rb.
Rb = V5 variable voltage width / IREF
Rb = 4V / 6.5µA
= 615 kΩ
(32 states
(16 states
IREF ≈ 6.5µA constant-current value)
IREF ≈ 3.2µA constant-current value)
(3) Determine Ra.
Ra =
VREG
(V5 set voltage max – VREG) / Rb
Ra =
2.5V
(10V – 2.5V) / 615Ω
(For VREG and V5 set voltage, absolute values are used.)
= 205 kΩ
(4) Adjust Ra.
Set the electronic contrast control register value to (D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0) or (0, 1, 1,
1, 1), and adjust the Ra value to the optimum contrast.
To set the voltage value by the software contrast adjustment control to the 16 states, fix the data D4 of
the electronic contrast control register to L and set data in D3 to D0. At this time, set IREF ≈ 3.2µA and
determine Ra and Rb according to the above steps (1) to (4).
Because IREF is a simplified constant-current source, it is necessary to consider the variation of
maximum ±40% as manufacturing dispersion. The temperature dependency of IREF becomes ∆IREF ≈
–0.0525 µA/°C (in the variable voltage 32 states) or ∆IREF ≈ –0.0234 µA/°C (variable voltage 16 states).
Determine Ra and Rb for the LCD to be used, by taking the above dispersion and variations due to
temperatures into consideration.
When using the software contrast adjustment control function, Ra must be a variable resistance and the
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174-3.0
4.0 Functional Description
4.24 – 4.25
optimum contrast adjustment described in (4) must be made for each IC chip in order to compensate
the V5 voltage value due to the dispersion of VREG and IREF.
When the contrast control function is not used, set the register value to (D4, D3, D2, D1, D0) = (0, 0,
0, 0, 0) by the RES signal or electronic contrast control register set command.
4.25 PRECAUTIONS ON USING THE SED1560 SERIES SOFTWARE CONTRAST ADJUSTMENT
CONTROL FUNCTION
The SED1560 Series is provided with a software contrast adjustment control function having up to 32
levels to control the regulator. The V5 voltage, when the software contrast control function is used, is
represented by the following expression:
V5 = (1 + Rb / Ra). VREG + Rb × ∆IREF
By this expression, the software contrast control function controls an increment of V5 voltage by means
of the current source IREF built into the IC. (In the case of 32 levels, ∆IREF = IREF / 32).
The V5 minimum voltage is set by the resistance ratio of the externally-installed Ra and Rb, and the
voltage step width by the software contrast control is determined by the resistance value of Rb.
The reference voltage VREG and current source IREF built into the SED1560 Series are kept constant
against voltage variations.
However, IC manufacturing dispersion and variations due to temperatures are caused as shown below.
VREG = 2.5V ± 0.15V
IREF = 3.2µA ± 40% (for 16 levels)
6.5µA ± 40% (for 32 levels)
VREG = –0.17%/°C
IREF = –0.0234 µA/°C
IREF = –0.0525 µA/°C
Example of Constant Setting
Conditions: Center value ............................. VDD – V5 = 8.5V
Variable voltage width ............... 3.2V
Variable voltage level................ 32 levels
(1) Determination of Rb.
Rb = V5 variable voltage width / IREF
= 3.2V / 6.5µA
= 492 kΩ
VDD
VREG
Ra
+
V5
–
VR
Rb
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51
4.25
4.0 Functional Description
(2) Determination of Ra.
Ra =
VREG
(V5 minimum set voltage – VREG) / Rb
=
2.5V
{(8.5V – 3.2V/2) – 2.5V} / 492kΩ
= 280 kΩ
(3) Temperature dependency of V5 when VREG = 2.5V and IREF = 6.5µA (32 levels).
V5 minimum set voltage (V5 min) = 8.5V – 3.2V/2 = 6.9V
Ta = 25°C
V5 max = V5 minimum set voltage + Rb × IREF
= 6.9V + 492kΩ × 6.5 µA
= 10.1V ....................................... 1
V5 typ
= (V5 max + V5 min) / 2
= (10.1V + 6.9V) / 2
= 8.5V ......................................... 2
Ta = –10°C
V5 min
= (1 + Rb / R a) × VREG (Ta = –10°C)
= (1 + 492kΩ / 280kΩ) × 2.5V × {1 + (–0.17%/°C) × (–10°C – 25°C)}
= 7.3V ......................................... 3
V5 max = V5 min + Rb × IREF (Ta = –10°C)
= 7.3V + 492kΩ × {6.5µA + (–0.0525 µA/°C) × (–10°C – 25°C)}
= 11.4V ....................................... 4
V5 typ
= (V5 max + V5 min) / 2
= (11.4V + 7.3V) / 2
= 9.35V ....................................... 5
Ta = 50°C
V5 min
= (1 + Rb / R a) × VREG (Ta = 50°C)
= (1 + 492kΩ / 280kΩ) × 2.5V × {1 + (–0.17%/°C) × (50°C – 25°C)}
= 6.6V ......................................... 6
V5 max = V5 min + Rb × IREF (Ta = 50°C)
= 6.6V + 492kΩ × {6.5µA + (–0.0525 µA/°C) × (50°C – 25°C)}
= 9.15V ....................................... 7
V5 typ
= (V5 max + V5 min) / 2
= (9.15V + 6.6V) / 2
= 7.9V ......................................... 8
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174-3.0
4.0 Functional Description
•
•
•
•
4.25
To set the number of variable voltage levels to 16, specify IREF = 3.2µA.
Margin calculation is performed by considering the dispersion of VREG and VREF according to the
same procedure as (3). From this margin calculation, it is made clear that the center value of V5 is
affected by variations of VREG and IREF.
Accordingly, it is necessary to set the electronic contrast control register value to (D4, D3, D2, D1,
D0) = (1, 0, 0, 0, 0) or (0, 1, 1, 1, 1) and adjust the Ra value to the optimum contrast.
The voltage step width by the electronic contrast control is changed by the dispersion of IREF. It is
necessary to consider that supposing that 0.2V/STEP is set by TYP value, the maximum variation
of 0.12V to 0.28V occurs.
SED 1560 Series
14
(V)
12
•
4
1
10
°
8
V5
∗
•
5
•
2
°
7
°
6
∗
∗
3
8
6
•
V5 max
°
∗
V5 typ
4
2
0
–20
–10
0
10
20
Ta
30
40
V5 min
50
60
(°C)
Example of V5 voltage when using SED1560 Series electronic contrast control
174-3.0
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53
4.25 – 4.26
Since the IREF is a simplified constant current source,
when using the electronic contrast control function, it
becomes necessary to make adjustment to the optimum contrast as given in the above item (4), with each
of the IC chips, using the R a as a variable resistor.
When not using the software contrast adjustment
control function, set the register to (D3, D2, D1, D0)
= (0, 0, 0, 0) using the RES signal or by means of the
software contrast adjustment control register setting command.
4.0 Functional Description
Table 4.8
Type
SED1560
SED1561
SED1562
Table 4.9 Reference Setting Value
Reference set values:
SED1560 ..... V5 ≈ –11 ~ –13V
SED1561 ..... V5 ≈ –7 ~ –9V
SED1562 ..... V5 ≈ –5 ~ –7V (Variable)
4.26 LIQUID CRYSTAL VOLTAGE
GENERATING CIRCUIT
A V5 potential is resistively divided within the IC to
cause V1, V2, V3 and V4 potentials needed for driving
of liquid crystals. The V1, V2, V3 and V4 potentials are
further converted in the impedance by the voltage
follower before being supplied to the liquid crystal
driving circuit.
The liquid crystal driving voltage is fixed with each
type (see Table 4.8).
As shown in Figure 4.13, it needs to connect, externally, 5 units of voltage stabilizing capacitors C2 to the
liquid crystal power terminals. When selecting such
capacitor C2, make actual liquid crystal displays
matching to the display capacity of the liquid crystal
display panel, before determining the capacitance as
the constant value for voltage stabilization.
Liquid Crystal Driving Voltage
1/9 of the bias voltage
1/7 of the bias voltage
1/5 of the bias voltage
C1
C2
R1
R2
R3
LCD
SIZE
DOT
SED1560
0.47µF~
1.0µF~
1.0µF~
1MΩ
200KΩ
4MΩ
32 × 51
mm
64 × 102
SED1561
0.47µF~
0.47µF~
0.47µF~
700KΩ
200KΩ
1.6MΩ
16 × 67
mm
32 × 134
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SED1562
0.47µF~
0.47µF~
0.47µF~
500KΩ
200KΩ
700KΩ
8 × 75
mm
16 × 150
174-3.0
4.0 Functional Description
Rf
4.26
Rf
*1
VDD
VDD
OSC1
OSC2
OSC1
M/S
CAP1+
CAP1+
C1
CAP1–
VSS
CAP1–
C1
CAP2+
CAP2+
C1
CAP2–
CAP2–
VOUT
VOUT
R3
V5
V5
VR
R2
M/S
VSS
CL
VSS
OSC2
*2
VR
SED156X
SED156X
R1
VDD
VDD
V1
V1
V2
C2
V3
V4
External
supply
voltage
V2
V3
V4
V5
V5
Figure 4.13
When the built-in power supply is used
Figure 4.14
When external LCD power supply is used
*1 Connect oscillator feedback resistor Rf as
short as possible and place it close to the
IC for preventing a malfunction.
*2 Use short wiring or shielded cables for the
VR pin due to high input impedance.
*3 Determine C1 and C2 depending on the
size of the LCD panel driven. You must set
these values so that the LCD driving voltage becomes stable. Set (T1, T2) = (H, L)
and supply an external voltage to VOUT.
Display the LCD heavy load pattern and
determine C2 so that the LCD driving
voltages (V1 to V5) become stable. However, it is necessary to make every C2
capacitance value equal. Then, set (T1,
T2) = (L, L) and determine C1.
*4 The “LCD SIZE” indicates the vertical
and horizontal length of the LCD panel
display area.
174-3.0
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55
4.27
4.0 Functional Description
4.27 RESET
When power is turned ON, the SED1560 Series is
initialized on the rising edge of RES. Initial settings are
as follows:
1. Display
: OFF
2. Display mode
: Normal
3. n-line inversion
: OFF
4. Duty cycle
5. ADC select
6. Read/write modify
7. On-chip power supply
8. Serial interface register
9. Display initial line register
10. Column address counter
11. Page address register
12. Output selection circuit
13. n-line inversion register
14. Software contrast setting
:
:
:
:
:
:
:
:
:
:
:
1/64
Normal
OFF
OFF
Cleared
Line 1
0
Page 0
Case 6
16
zero
The RES pin should be connected to the microprocessor reset terminal so that both devices are reset at the
same time. RES must be LOW for at least 1 µs to
correctly reset the SED1560 Series. Normal operation starts 1 µs after the rising edge on RES.
If the SED1560 Series is not properly initialized when
power is turned ON, it can lock itself into a state that
cannot be cancelled.
When the Reset command is used, only initial settings 9 to 14 are active.
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5.0
Commands
174-3.0
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THIS PAGE INTENTIONALLY BLANK
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174-3.0
5.0 Commands
5.1
5.1 COMMAND SUMMARY
A0, RD and WR identify the data bus commands.
Interpretation and execution of commands are synchronized to the internal clock. Since a busy check is
normally not needed, commands can be processed at
high speed. When the serial interface is used, the
order of data entry is D7 to D0.
Table 5.1
Command
Code
A0
RD
WR
D7
D6
D5
D4
D3
D2
D1
D0
Display ON/OFF
0
1
0
1
0
1
0
1
1
1
D
Initial display line
0
1
0
0
1
Page address set
0
1
0
1
0
1
Description
Turns the display ON and OFF.
D = 0 OFF
D = 1 ON
Display line address
Sets the display RAM line address for
COM0.
1
Page address
Sets the RAM page address register.
Sets the column address register upper
four bits.
Sets the column address register lower
four bits.
Column address set
(upper four bits)
0
1
0
0
0
0
1
Column address
upper four bits
Column address set
(lower four bits)
0
1
0
0
0
0
0
Column address
lower four bits
Read status
0
0
1
Write display data
1
1
0
Status
Write data
0
0
Read display data
1
0
1
Read data
0
0
Reads out status information.
Writes to display RAM.
Reads from display RAM.
Select ADC
0
1
0
1
0
1
0
0
0
0
D
Sets the display RAM segment output.
D = 0 Normal
D = 1 Inverse
Normal/inverse
display
0
1
0
1
0
1
0
0
1
1
D
Sets the LCD display mode.
D = 0 Normal
D = 1 Inverse
Display all points
ON/OFF
0
1
0
1
0
1
0
0
1
0
D
Sets the segments display mode.
D = 0 Normal
D = 1 All display segments ON
Select duty
0
1
0
1
0
1
0
1
0
0
D
Sets the LCD controller duty (1).
D = 0, D=1 See Table 5.3
Duty + 1
0
1
0
1
0
1
0
1
0
1
D
Sets the LCD controller duty (2).
D = 0 Normal
D = 1 Duty + 1
Set n-line inversion
0
1
0
0
0
1
1
Cancel n-line inversion
0
1
0
0
0
1
0
0
0
0
0
Cancels line inversion display mode.
Read Modify Write
0
1
0
1
1
1
0
0
0
0
0
Sets modified read mode. The column
address counter is not incremented when
reading.
End
0
1
0
1
1
1
0
1
1
1
0
Cancels modified read mode.
Power-on
completion
0
1
0
1
1
1
0
1
1
0
1
Completes the turn-on sequence of builtin power supply
Reset
0
1
0
1
1
1
0
0
0
1
0
Resets the internal registers.
Output status set
0
1
0
1
1
0
0
LCD power supply
ON/OFF
0
1
0
0
0
1
0
Software contrast
setting
0
1
0
1
0
0
Electronic contrast control
resistance value
Power save
174-3.0
Number of
inverted items
Sets the number of inverted lines in the inversion register for the inversion controller.
Sets the common and segment output
status register.
Output status
0
1
0
D
Turns the power supply ON and OFF.
D = 0 OFF
D = 1 ON
Setting the V5 output voltage to the electronic contrast control register.
A complex command to turn off the display
and light all indicators.
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59
5.2 – 5.2.4
5.2 Command Definitions
5.2 COMMAND DEFINITIONS
5.2.1 Display ON/OFF
Alternately turns the display ON and OFF.
R/W
A0 RD WR D7 D6
0
1
0
1
0
Note:
D=0
D=1
D5
1
D4
0
D3
1
D2 D1
1
1
D0
D
Display OFF
Display ON
5.2.2 Initial Display Line
Loads the RAM line address of the initial display line,
COM0, into the initial display line register. The RAM
display data becomes the top line of the LCD screen.
It is followed by the higher number lines in ascending
order, corresponding to the duty cycle. The screen
can be scrolled using this command by incrementing
the line address.
A3
A2
A1
A0
Page
0
0
0
0
0
0
0
1
0
1
0
0
1
0
2
0
0
0
1
1
0
1
0
3
4
0
0
1
1
0
1
1
0
5
6
0
1
1
1
7
1
0
0
0
8
5.2.4 Column Address Set
Loads the RAM column address from the microprocessor into the column address register. The column
address is divided into two parts—4 high-order bits
and 4 low-order bits.
R/W
A0 RD WR D7 D6
0
1
0
0
1
D5
A5
D4
A4
D3
A3
D2 D1
A2 A1
D0
A0
When the microprocessor reads or writes display
data to or from RAM, column addresses are automatically incremented, starting with the address
stored in the column address register and ending
with address 166.
A5
0
A4
0
A3
0
A2
0
A1
0
A0
0
Line Address
0
0
0
0
0
0
0
0
0
1
1
0
1
2
The page address is not incremented automatically.
↓
D5
D4
D3
D2 D1
D0
0
1
A7
A6
A5
A4
A0 RD WR D7 D6
0
1
0
0
0
D5
0
D4
0
D3
A3
D2 D1
A2 A1
D0
A0
A7
A6
A5
A2
A1
A0
Column
Address
0
0
0
0
0
0
0
0
0
0
0
0
0
↓
0
0
0
1
1
↓
1
0
1
0
0
1
0
1
165
0
↓
1
1
1
1
1
1
1
1
1
1
0
1
R/W
A0 RD WR D7 D6
62
63
0
1
0
0
0
R/W
5.2.3 Page Address Set
Loads the RAM page address from the microprocessor into the page address register. A page address,
along with a column address, defines a RAM location
for writing or reading display data. When the page
address is changed, the display status is not affected.
Page address 8 is a special use RAM area for the
indicator. Only D0 is available for data exchange.
R/W
A0 RD WR D7 D6
0
1
0
1
0
D5
D4
D3
D2 D1
D0
1
1
A3
A2
A0
A1
A4 A3
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174-3.0
5.2 Command Definitions
5.2.5 – 5.2.9
5.2.5 Read Status
5.2.7 Read Display Data
Indicates to the microprocessor the SED1560 Series
status conditions.
Sends bytes of display data to the microprocessor
from the RAM location specified by the column address and page address registers. The column address is incremented automatically so that the microprocessor can continuously read data from the addressed page. A dummy read is required after loading
an address into the column address register.
R/W
A0 RD WR D7 D6
0
0
1
BUSY ADC
D5
D4
D3
ON/
OFF
RESET
0
D2 D1
0
0
D0
0
• BUSY - Indicates whether or not the SED1560
Series will accept a command. If BUSY is 1,
the device is currently executing a command
or is resetting, and no new commands can
be accepted. If BUSY is 0, a new command
can be accepted. It is not necessary for the
microprocessor to check the status of this bit
if enough time is allowed for the last cycle to
be completed.
• ADC - Indicates the relationship between RAM
column addresses and the segment drivers.
If ADC is 1, the relationship is normal and
column address n corresponds to segment
driver n . If ADC is 0, the relationship is
inverted and column address (165 – n) corresponds to segment driver n.
• ON/OFF - Indicates whether the display is
ON or OFF. If ON/OFF is 1, the display is
OFF. If ON/OFF is 0, the display is ON.
Note that this is the opposite of the Display
ON/OFF command.
• RESET - Indicates whether initialization is
in process as the result of RES or the
Reset command.
Display data cannot be read through the serial interface.
R/W
A0 RD WR D7 D6
1
0
1
D5 D4 D3
Read data
D2 D1
D0
5.2.8 Select ADC
Selects the relationship between the RAM column
addresses and the segment drivers. When reading or
writing display data, the column address is incremented
as shown in Figure 5.4.
R/W
A0 RD WR D7 D6
0
1
0
1
0
D5
1
D4
0
D3
0
D2 D1
0
0
D0
D
Note:
D = 0 Rotate right (normal direction)
D = 1 Rotate left (reverse direction)
The output pin relationship can also be changed by the
microprocessor. There are very few restrictions on pin
assignments when constructing an LCD module.
5.2.9 Normal/Inverse Display
5.2.6 Write Display Data
Writes bytes of display data from the microprocessor to the RAM location specified by the column
address and page address registers. The column
address is incremented automatically so that the
microprocessor can continuously write data to the
addressed page.
R/W
A0 RD WR D7 D6
1
1
0
174-3.0
Determines whether the data in RAM is displayed
normally or inverted.
R/W
A0 RD WR D7 D6
0
1
0
1
0
D5
D4
D3
1
0
0
D2 D1
1
D0
1
D
Note:
D = 0 LCD segment is ON when RAM data is 1 (normal).
D = 1 LCD segment is ON when RAM data is 0 (inverse).
D5
D4 D3 D2 D1
Write data
D0
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61
5.2.10 – 5.2.14
5.2 Command Definitions
5.2.10 Display All Points ON/OFF
Turns all LCD points ON independently of the display
data in RAM. The RAM contents are not changed.
This command has priority over the normal/inverse
display command.
R/W
A0 RD WR D7 D6
0
1
0
1
0
D5
D4
D3
1
0
0
D2 D1
1
0
D0
the RAM area corresponding to page address 8, D0.
(Refer to Figure 5.4.)
In multi-chip configuration, the Duty + 1 command
must be executed to both the master and slave sides.
R/W
A0 RD WR D7 D6
0
1
0
1
0
D5
D4
D3
1
0
1
D2 D1
0
1
D0
D
D
Table 5.3
Note:
D = 0 Normal display status
D = 1 All display segments ON
Model
D
0
Duty
1/48 or 1/64
1
1/49 or 1/65
SED1561
0
1
1/24 or 1/32
1/25 or 1/33
SED1562
0
1
1/16
1/17
SED1560
If this command is received when the display status is
OFF, the Power Save command is executed.
5.2.11 Select Duty
Selects the LCD driver duty.
Since this is independent from the contents of the
output status register, the duty must be selected
according to the LCD output status.
In multi-chip configuration, the master and slave devices must have the same duty.
R/W
A0 RD WR D7 D6
0
1
0
1
0
5.2.13 Set n-line Inversion
Selects the number of inverse lines for the LCD AC
controller. The value of n is set between 2 and 16 and
is stored in the n-line inversion register.
R/W
A0 RD WR D7 D6
0
D5
1
D4
0
D3
1
D2 D1
0
0
D0
D
Table 5.2
1
0
0
0
D5
D4
D3
D2 D1
D0
1
1
A3
A2
A0
A3
A2
A1
A0
Number of Inverted Lines
0
0
0
0
0
0
0
1
—
2
0
0
1
0
3
↓
Model
D
Duty
SED1560
0
1
1/48
1/64
1
1
1
0
15
0
1/24
1
1
1
1
16
1
0
1/32
1/16
1
1/16
SED1561
SED1562
5.2.12 Duty + 1
Increases the duty by 1. If 1/48 or 1/64 duty is selected
in the SED1560, for example, 1/49 or 1/65 is set,
respectively, and COM1 functions as either the COM48
or COM64 output. The display line always accesses
A1
↓
5.2.14 Cancel n-line Inversion
Cancels n -line inversion and restores the normal 2frame AC control. The contents of the n-line inversion
register are not changed.
R/W
A0 RD WR D7 D6
0
1
0
0
0
D5
1
D4
0
D3
0
D2 D1
0
0
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D0
0
174-3.0
5.2 Command Definitions
5.2.15 – 5.2.17
5.2.15 Modify Read
Following this command, the column address is no
longer incremented automatically by a Read Display
Data command. The column address is still
incremented by the Write Display Data command.
This mode is cancelled by the End command. The
column address is then returned to its value prior to
the Modify Read command. This command makes it
easy to manage the duplication of data from a particular display area for features such as cursor blinking.
Page address set
Column address set
Read–modify–write cycle
R/W
A0 RD WR D7 D6
0
1
0
1
1
D5
1
D4
0
D3
0
D2 D1
0
0
D0
0
Dummy read
Note: the Column Address Set command cannot be used in
modify-read mode.
Data read
5.2.16 End
Cancels the modify read mode. The column address
prior to the Modify Read command is restored.
Data write
R/W
A0 RD WR D7 D6
0
1
0
1
1
D5
D4
D3
1
0
1
D2 D1
1
1
D0
0
No
5.2.17 Reset
Resets the initial display line, column address, page
address, and n-line inversion registers to their initial
values. This command does not affect the display
data in RAM.
Changes
finished?
Yes
END
R/W
A0 RD WR D7 D6
0
1
0
1
1
D5
D4
D3
1
0
0
D2 D1
0
1
D0
0
Figure 5.1
Command sequence for cursor blinking
The reset command does not initialize the LCD power
supply. Only hardware RES can be used to initialize
the power supplies.
Return
Column
address
N
N+1
N+2
N+3
N+m
N
Read–modify–write mode set
End
Figure 5.2
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5.2.18 – 5.2.20
5.2 Command Definitions
5.2.18 Output Status Set
5.2.20 LCD Power Supply ON/OFF
Selects the common or segment output state of the
LCD driver dual outputs. The A3 bit selects the scan
direction of the outputs.
Turns the SED1560 Series LCD power supply ON or
OFF. When the power supply is ON, the voltage
converter, the voltage regulator circuit and the voltage followers are operating. In order for the converter
to function, the oscillator must also be operating.
R/W
A0 RD WR D7 D6
0
1
0
1
1
D5
D4
D3
D2 D1
D0
0
0
A3
A2
A0
A1
R/W
A0 RD WR D7 D6
0
1
0
0
0
5.2.19 Output Status Register
Available only in the SED1560 and SED1561.
The COM output scanning direction can be selected
by setting A3 to “H” or “L”. For details, refer to the
Output Status Circuit in each function description.
R/W
D5
0
D4
0
D3
A3
D2 D1
A2 A1
D4
D3
1
2
0
0
D2 D1
1
4
0
D0
0
OFF
Note:
D = 0 Supply OFF (24H)
This command selects the role of the COM/SEG dual
pins and determines the LCD driver output status.
A0 RD WR D7 D6
0
1
0
1
1
D5
D0
A0
D = 1 Supply ON (25H)
When an external power supply is used with the
SED1560 Series, the internal supply must be OFF.
If the SED1560 Series is used in a multiple-chip
configuration, an external power supply that meets
the specifications of the LCD panel must be used. An
SED1560 Series operating as a slave must have its
internal power supply turned OFF.
A3: Selection of the COM output scanning direction
Table 5.4
A2 A1 A0
Sequence in the Built-In Power ON/OFF Status
Output
Status
Number of
COM/SEG
Output Pins
Remarks
Applies to the
SED1560/61
0
0
0
Case 6
SEG 166
0
0
1
Case 5
SEG 134, COM 32
0
1
0
Case 4
SEG 134, COM 32
0
1
1
Case 3
SEG 134, COM 32
1
0
0
Case 2
1
0
1
Case 1
SEG 102, COM 64 Applies to the
SEG 102, COM 64 SED1560
1
1
0
Case 6
SEG 166
1
1
1
Case 6
SEG 166
Applies to the
SED1561
To turn on internal power supply, execute the following built-in power supply ON sequence. To turn off
internal power supply, execute the power save sequence as shown in the following power supply OFF
status.
Accordingly, to turn on internal power supply again
after turn it off (power save), execute the “Power Save
Clear Sequence” that is described below.
Applies to the
SED1560/61
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5.2 Command Definitions
5.2.20
Sequence in the Power Save Status
To give a liquid crystal driving voltage level by the
externally-installed resistance dividing circuit, the
current flowing in this resistance must be cut before
or concurrently with putting the SED1560 Series
into the power save status so that it may be fixed to
the floating or VDD level.
When using an external power supply, likewise, its
function must be stopped before or concurrently
with putting the SED1560 Series into the power
save status so that it may be fixed to the floating or
VDD level. In a configuration in which an exclusive
common driver such as SED1630 is combined with
the SED1560 Series, it is necessary to stop the
external power supply function after putting all the
common output into non-selection level.
Power Save Sequence
Power Save Clear Sequence
Power Save and Power Save Clear must be executed
according to the following sequence.
*3
Output Status Select
command
C*(H)
*2
*DUTY+1
command
AB(H)
Internal Power Supply ON
command
25(H)
command
ED(H)
Display OFF
command
AE(H)
*3
Output Status case 6
command
CF(H)
*2
*DUTY+1 Clear
command
AA(H)
*1
Display All ON Status OFF
*1
Display all ON
command
A5(H)
*6
(Waiting time)
*5
Power Supply Startup End
*1. In the power save sequence, the power
save status is provided after the display all
ON command. In the power save clear sequence, the power save status is cleared
after the display all ON status OFF command.
*2. When the COMI pin is not used, it is not
necessary to enter the DUTY + 1 command
and DUTY + 1 clear command.
*3. In the SED1562, it is not necessary to execute a command to decide an output status.
*4. The display ON command can be executed
anywhere if it is later than the display all ON
status OFF command.
174-3.0
*5. When internal power supply startup end
command is not executed, current is consumed stationarily. Internal power supply
startup end command must always be used
in a pair with internal power supply ON
command.
*6. The waiting time depends on the externallyinstalled capacitance C2 (refer to Table 5.9).
After the waiting time shown in the graph
above (see bottom of previous page), the
power supply can be started surely.
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5.2.20
5.2 Command Definitions
Internal Power Supply ON Status
Internal Power Supply OFF Status
Reset by RES signal
*1
Output Status Select
command
A*(H)
Display OFF
command
AE(H)
*2
*DUTY+1
command
AB(H)
Output Status case 6
command
CF(H)
Internal Power Supply ON
command
25(H)
*DUTY+1 Clear
command
AA(H)
Display all ON
command
A5(H)
*4,5
(Waiting time)
*3
Power Supply Startup End
command
*2
ED(H)
*1. Regarding the SED1562, it is not necessary to execute a command to decide an
output status.
*2. When the COMI pin is not used, it is not
necessary to enter the DUTY + 1 and DUTY
+ 1 Clear commands.
*3. When the built-in power supply startup
end command is not executed, current is
consumed stationarily. Internal power supply startup end command must always be
used in a pair with internal power supply
ON command.
*4. The waiting time depends on the externallyinstalled capacitance C2 (refer to Table 5.9).
After the waiting time shown in the graph
below, the power supply can be started surely.
*5. Within the waiting time in internal power
supply ON status, any command other than
internal power supply control commands
such as Power Save, and display ON/OFF
command, display normal rotation/reverse
command, display all ON command, output
status select command and DUTY + 1 clear
command can accept another command
without any problem. RAM read and write
operations can be freely performed.
120
(mS)
100
80
Waiting
time
60
V5 voltage conditions
1/9 bias V5 = –6.0 to –16.0 V
1/7 bias V5 = –5.0 to –12.0 V
1/5 bias V5 = –4.5 to –8.0 V
1/9 bias
1/7 bias
40
20
1/5 bias
0
0.5
Capacitance C2
1.0
(µF)
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174-3.0
5.3 Software Contrast Control Register
5.3 SOFTWARE CONTRAST CONTROL
REGISTER
Through these commands, the liquid crystal driving
voltage V5 is output from the voltage regulation circuit
of the built-in liquid crystal power supply, in order to
adjust the contrast of the liquid crystal display.
By setting data to the 5-bit register, one of the 32
voltage statuses may be selected for the liquid crystal
driving voltage V5. External resistors are used for
setting the voltage regulation range of the V5. For
details refer to the paragraph of the voltage regulation
circuit in the clause for the explanation of functions.
R/W
A0 RD WR D7 D6
D5
D4
D3
D2 D1
D0
0
A4
A3
A2
A0
0
1
0
1
0
A4
0
A3
0
A2
0
A1
0
A0
| V5 |
0
Small (as the absolute value)
↓
1
1
1
A1
↓
1
1
Large (as the absolute value)
When not using the electronic contrast control function, set to (0, 0, 0, 0).
5.3 – 5.3.2
(a) The oscillator and power supply circuits are
stopped.
(b) The LCD driver is stopped and segment and
common driver outputs output the VDD level.
(c) An input of an external clock is inhibited and
OSC2 enters the high-impedance state.
(d) The display data and operation mode before execution of the power save command are held.
(e) All LCD driver voltages are fixed to the
VDD level.
The power save mode is cancelled by entering either
the Display ON command or the Display All Points
OFF command (display operation state). When external voltage driver resistors are used to supply the LCD
driver voltage level, the current through them must be
cut off by the power save signal.
If an external power supply is used, it must be
turned OFF using the power save signal in the
same manner, and voltage levels must be fixed to
the floating or VDD level.
5.3.2 Connection between LCD Drivers
5.3.1 Power Save (Complex Command)
If the Display All Points ON command is specified in
the display OFF state, the system enters the power
save status, reducing the power consumption to approximate the static power consumption value. The
internal state in the power save status is as follows:
The LCD display area can be increased by using
the SED1560 Series in a multiple-chip configuration or with the SED1560 Series special common
driver (SED1630).
VDD
SED1630
DIO
YSCL
FR
FR
SYNC
SED156X
(Master)
OSC1 OSC2 CL
M/S
CLO DYO
Rf
VSS
Figure 5.3 Application with external driver: SED156X – SED1630
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5.3.2
5.3 Electronic Contrast Control Register
VDD
M/S
SED156X
(Master)
FR
SYNC
OSC1 OSC2 CL
CLO DYO
Rf
VSS
FR
SYNC
SED156X
(Slave)
OSC1 OSC2 CL
M/S
VSS
CLO DYO
VSS
VDD
M/S
SED156X
(Master)
OSC1 OSC2 CL
VSS
Rf
FR
SYNC
CLO DYO
FR
SYNC
VDD
SED156X
(Slave)
OSC1 OSC2 CL
VSS
M/S
CLO DYO
Figure 5.4 SED156X – SED156X (when oscillator circuit is used)
VDD
M/S
SED156X
(Master)
OSC1 OSC2 CL
VSS
FR
SYNC
FR
SYNC
CLO DYO
VDD
SED156X
(Slave)
OSC1 OSC2 CL
VSS
M/S
VSS
CLO DYO
External clock
Figure 5.5 SED156X – SED156X (External clock)
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174-3.0
5.4 Microprocessor Interface
5.4
5.4 MICROPROCESSOR INTERFACE
The SED1560 Series communicates with a highspeed microprocessor, such as the Intel 80XX family
or the Motorola 68XX family, through 8-bit parallel
data transfer. The number of connections to the
VCC
microprocessor can be minimized by using a serial
interface. When used in a multiple-chip configuration,
the SED1560 Series is controlled by the chip select
signals from the microprocessor.
A0
A0
VDD
C86
A0 to A7
MPU
Decoder
IORQ
SED156X
D0 to D7
D0 to D7
GND
CS1
CS2
RD
WR
RES
RD
WR
RES
P/S
VSS
RESET
Figure 5.6 8080-series microprocessors
VCC
A0
A0
VDD
C86
A0 to A15
MPU
Decoder
VMA
SED156X
D0 to D7
D0 to D7
GND
CS1
CS2
E
R/W
RES
E
R/W
RES
P/S
VSS
RESET
Figure 5.7 6800-series microprocessors
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5.4 – 5.5
5.4 Microprocessor Interface
VCC
A0
A0
VDD
C86
A0 to A7
CS1
CS2
Decoder
MPU
PORT1
PORT2
VDD
or
GND
SED156X
SI
SCL
P/S
GND
RES
RES
VSS
RESET
Figure 5.8 Serial interface
5.5 LCD PANEL INTERFACE EXAMPLES
65 × 102
Segments
Commons
SED1560
(Master)
Case 1
33 × 134
17 × 150
Segments
Commons
SED1561
(Master)
Segments
Commons
SED1562
Case 4
Figure 5.9 Single-chip configurations
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174-3.0
5.5 LCD Panel Interface Examples
5.5
65 × 268
Segments
Commons
Segments
SED1560
(Master)
SED1560
(Slave)
Case 1
Case 6
33 × 300
Segments
Segments
Commons
SED1561
(Master)
SED1561
(Slave)
Case 4
Case 6
Figure 5.10 Multiple-chip combinations
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5.6
5.6 Special Common Driver Configurations
5.6 SPECIAL COMMON DRIVER CONFIGURATIONS
SED1630
Commons
65 × 166
Segments
SED1560
(Master)
Case 6
Case 6
SED1560
(Master)
Segments
Commons
128 × 166
SED1631
Commons
Segments
SED1560
(Slave)
Case 6
Figure 5.11 Special common driver configurations
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174-3.0
6.0
Packaging
174-3.0
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THIS PAGE INTENTIONALLY BLANK
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174-3.0
6.0 Pad Layout
6.1
O0
O45
6.1 PAD LAYOUT
O46
V5
V4
V3
V2
V1
VDD
VR
V5
VOUT
CAP2–
CAP2+
CAP1–
CAP1+
VSS
T1
T2
OSC1
OSC2
CL
FR
SYNC
CLO
DYO
D7
D6
D5
D4
D3
D2
D1
D0
VSS
RD
WR
A0
C86
CS2
CS1
P/S
SI
SCL
RES
M/S
VDD
V1
V2
V3
V4
V5
SED156X
Chip Size
Pad Pitch
Chip thickness
: 8.08 × 5.28 mm
: 100 µm (min)
: 625 µm ± 25 µm
O165
COM1
O121
O120
Figure 6.1 Pad layout
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6.1
6.0 Pad Layout
Table 6.1 SED1560 Series Pad Center Coordinates
Pad
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
Pin
Name
V5
V4
V3
V2
V1
VDD
M/S
RES
SCL
SI
P/S
CS1
CS2
C86
A0
WR
RD
VSS
D0
D1
D2
D3
D4
D5
D6
D7
DYO
CLO
SYNC
FR
CL
OSC2
OSC1
T2
T1
VSS
CAP1+
CAP1–
CAP2+
CAP2–
VOUT
V5*
VR
VDD
V1
V2
V3
V4
V5
O0
O1
O2
O3
O4
X
Y
3640
3489
3339
3188
3037
2889
2755
2604
2453
2302
2151
2001
1850
1699
1548
1397
1247
1077
945
794
643
493
342
191
40
–111
–261
–412
–563
–714
–865
–1015
–1166
–1317
–1468
–1638
–1789
–1939
–2090
–2241
–2392
–2543
–2674
–2844
–2995
–3146
–3297
–3447
–3598
–3887
–3887
–3887
–3887
–3887
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2487
2294
2194
2094
1994
1894
Pad
No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
Pin
Name
O5
O6
O7
O8
O9
O10
O11
O12
O13
O14
O15
O16
O17
O18
O19
O20
O21
O22
O23
O24
O25
O26
O27
O28
O29
O30
O31
O32
O33
O34
O35
O36
O37
O38
O39
O40
O41
O42
O43
O44
O45
O46
O47
O48
O49
O50
O51
O52
O53
O54
O55
O56
O57
O58
X
Y
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3887
–3711
–3611
–3511
–3411
–3311
–3211
–3111
–3011
–2911
–2811
–2711
–2611
–2511
1794
1694
1594
1494
1394
1294
1194
1094
994
894
794
694
594
494
394
294
194
94
–6
–106
–206
–306
–406
–506
–606
–706
–806
–906
–1006
–1106
–1206
–1306
–1406
–1506
–1606
–1706
–1806
–1906
–2006
–2106
–2206
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
Pad
No.
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
Pin
Name
O59
O60
O61
O62
O63
O64
O65
O66
O67
O68
O69
O70
O71
O72
O73
O74
O75
O76
O77
O78
O79
O80
O81
O82
O83
O84
O85
O86
O87
O88
O89
O90
O91
O92
O93
O94
O95
O96
O97
O98
O99
O100
O101
O102
O103
O104
O105
O106
O107
O108
O109
O110
O111
O112
X
Y
–2411
–2311
–2211
–2111
–2011
–1911
–1811
–1711
–1611
–1511
–1411
–1311
–1211
–1111
–1011
–911
–811
–711
–611
–511
–411
–311
–211
–111
–11
89
189
289
389
489
589
689
789
889
989
1089
1189
1289
1389
1489
1589
1689
1789
1889
1989
2089
2189
2289
2389
2489
2589
2689
2789
2889
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
Pad
No.
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
Pin
Name
O113
O114
O115
O116
O117
O118
O119
O120
O121
O122
O123
O124
O125
O126
O127
O128
O129
O130
O131
O132
O133
O134
O135
O136
O137
O138
O139
O140
O141
O142
O143
O144
O145
O146
O147
O148
O149
O150
O151
O152
O153
O154
O155
O156
O157
O158
O159
O160
O161
O162
O163
O164
O165
COMI
X
Y
2989
3089
3189
3289
3389
3489
3589
3689
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
3887
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2487
–2206
–2106
–2006
–1906
–1806
–1706
–1606
–1506
–1406
–1306
–1206
–1106
–1006
–906
–806
–706
–606
–506
–406
–306
–206
–106
–6
94
194
294
394
494
594
694
794
894
994
1094
1194
1294
1394
1494
1594
1694
1794
1894
1994
2094
2194
2294
* One V5 output is used for the LCD driver supply voltage; the other is used for the electronic volume control.
76 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
174-3.0
6.2 SED1560 Series TAB Pin Layout
6.2
6.2 SED1560/1/2 TAB PIN LAYOUT
This drawing is not for specifying the TAB outline shape.
O0
SED156X
TOP
VIEW
V5
V4
V3
V2
V1
VDD
VR
V5
VOUT
CAP2–
CAP2+
CAP1–
CAP1+
VSS
T1
T2
OSC1
OSC2
CL
FR
SYNC
CLO
DYO
D7
D6
D5
D4
D3
D2
D1
D0
VSS
RD
WR
A0
C86
CS2
CS1
P/S
SI
SCL
RES
M/S
VDD
V1
V2
V3
V4
V5
O165
COMI
Figure 6.2 SED1560 Series TAB pin layout
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
77
6.3
6.3 TCP Dimensions (2-sided)
X(+)
MAX 1.0
MAX 0.8
MAX 0.15
SED1560T0B
6.3 TCP DIMENSIONS (2-SIDED) SED156XT0B
NC x 2
00
8.8
ø1.7
NC
V5
V4
V3
60
V2
D1
5
1.5
V1
VDD
VR
V5
VOUT
CAP2–
CAP2+
CAP1–
VSS
T1
T2
OSC1
OSC2
CL
FR
SYNC
CLO
DYO
D6
D5
0.28
D4
0.80
D3
D2
D1
D0
VSS
RD
WR
40.00
44.00
36.00
Y(+)
47.5
D7
Note 1: Resist position tolerance: ±0.3
2: Product pitch: 52.25mm
CAP1+
A0
C86
CS2
CS1
P/S
SI
SCL
RES
ø2.10 SR
ø1.50 PI
M/S
VDD
V1
V2
V3
V4
V5
NC
4.40
NC x 2
COM1
0165
0.5
5.34
15.16
2.70
28.98 ± 0.04
Figure 6.3 TCP dimensions (2-sided)
78 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
174-3.0
6.4 TCP Dimensions (4-sided)
6.4
4 – RO. 2
X(+)
4 – RO. 2
MAX 1.0
MAX 0.8
MAX 0.15
6.4 TCP DIMENSIONS (4-SIDED) SED156XT0A
0.30
0
56
22.50
26.95
D
15
60
0.30
18.00
Y (+)
D1
D1560
0.60
25.95
31.82
34.9750
Figure 6.4 TCP dimensions (4-sided)
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
79
6.5
6.5 TCP Dimensions (D1561TOC)
6.5 TCP DIMENSIONS (SED1561TOC)
0.01
28.98±0.07
8.50 (SR)
6.66 (SR)
10.23 (SR)
2.54
(SR)
5.34
2.39
(SR)
0.11±0.02
0.14±0.02
NCX2
COM1
0165
•
•
•
4.40
0.14
NC
V5
V4
ø 2.10 SR
ø 1.50 PI
V3
V2
V1
VDD
M/S
RES
SCL
SI
P/S
CS1
CS2
C86
A0
D0
D1
D2
D6
D7
MAX 8.28
DYO
1.98±0.01
CLO
SYNC
FR
4.75 ± 0.01
CL
OSC2
OSC1
T2
T1
Y (+)
D5
MAX 11.08
D4
0.28
0.14
5.28 (IC)
D3
8.08 (IC)
0.40
0.80
36.00
PO. 80 x 51 – 1 = 40.00 (W 0.4, G 0.4)
41.00 (SR)
RD
VSS
48.34 (SR)
PO. 28 x 171 – 1 = 47.60±0.06 (W 0.14, G 0.14)
WR
VSS
CAP1+
CAP1–
CAP2+
CAP2–
VOUT
V5
VR
VDD
V1
1.5
V2
V3
V4
V5
ø 1.7
NC
•
•
•
00
NCX2
ø 2.0
X (+)
MAX 1.50
MAX 1.50
MAX 1.0
MAX 0.8
MAX 1.50
IC : SED1561DOB
MAX 1.50
Figure 6.5 TCP dimensions (D1561TOC)
80 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
174-3.0
6.6 Pad Profile
6.6
6.6 PAD PROFILE
TBD
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
81
6.7
6.7 BGA Package Dimensions
6.7 BGA PACKAGE DIMENSIONS
D
SED1560BOA
E
E1
D1
INDEX
4–C2
4–C1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Q P N M L K J H G F E D C B A
Ø2
A2
A
e
øb
A1
Figure 6.7 Plastic BGA 225pin
Table 6.2 BGA 225pin package dimensions
Symbol
øb
A
A1
A2
θ2
C1
C2
e
D1
E1
D
E
Dimension in Millimeters
Min.
Nom.
Max.
0.6
0.75
0.90
2.13
Dimension in inches*
Min.
Nom.
Max.
(0.024)
(0.030)
(0.035)
(0.084)
0.5
1.43
0.7
1.63
(0.020)
(0.057)
24.1
24.1
(0.941)
(0.941)
23.9
23.9
0.6
1.53
25°
1.5
1.2
1.5
24
24
27
27
(0.024)
(0.060)
(25°)
(0.059)
(0.047)
(0.059)
(0.945)
(0.945)
(1.063)
(1.063)
(0.027)
(0.064)
(0.948)
(0.948)
* for reference
82 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
174-3.0
6.8 BGA Pin Assignment
6.8
6.8 BGA PIN ASSIGNMENT
SED1560 SED1560 BGA225 SED1560 SED1560 BGA225 SED1560 SED1560 BGA225 SED1560 SED1560 BGA225
pad# pin name
pin#
pad# pin name
pin#
pad# pin name
pin#
pad# pin name
pin#
1
V5
B-2
55
05
R-2
109
059
K-10
163
0113
D-12
2
V4
D-4
56
06
P-3
110
060
M-13
164
0114
B-14
B-1
57
07
K-6
111
061
N-15
165
0115
A-15
3
V3
C-2
58
08
N-4
112
062
M-14
166
0116
C-13
4
V2
5
V1
F-6
59
09
R-3
113
063
J-10
167
0117
A-14
D-3
60
010
P-4
114
064
L-12
168
0118
B-13
6
VDD
7
M/S
C-1
61
011
K-7
115
065
M-15
169
0119
E-11
8
/RES
D-2
62
012
M-5
116
066
L-13
170
0120
C-12
9
SCL
G-6
63
013
R-4
117
067
L-14
171
0121
A-13
10
SI
E-4
64
014
N-5
118
068
K-11
172
0122
B-12
11
P/S
D-1
65
015
P-5
119
069
L-15
173
0123
F-9
12
/CS1
E-3
66
016
L-6
120
070
K-12
174
0124
D-11
13
CS2
E-2
67
017
R-5
121
071
K-13
175
0125
A-12
14
C86
F-5
68
018
M-6
122
072
K-14
176
0126
C-11
15
A0
E-1
69
019
N-6
123
073
K-15
177
0127
B-11
16
/WR
F-4
70
020
P-6
124
074
J-12
178
0128
E-10
17
/RD
F-3
71
021
R-6
125
075
J-13
179
0129
A-11
F-2
72
022
M-7
126
076
J-14
180
0130
D-10
18
VSS
19
D0
F-1
73
023
N-7
127
077
J-15
181
0131
C-10
20
D1
G-4
74
024
P-7
128
078
J-11
182
0132
B-10
21
D2
G-3
75
025
R-7
129
079
L-8
183
0133
A-10
22
D3
G-2
76
026
L-7
130
080
K-8
184
0134
D-9
23
D4
G-1
77
027
M-8
131
081
H-10
185
0135
C-9
24
D5
G-5
78
028
P-8
132
082
H-11
186
0136
B-9
25
D6
H-3
79
029
R-8
133
083
H-6
187
0137
A-9
26
D7
H-1
80
030
N-8
134
084
H-5
188
0138
E-9
27
DYO
H-2
81
031
L-9
135
085
F-8
189
0139
D-8
28
CLO
H-4
82
032
R-9
136
086
E-8
190
0140
B-8
29
SYNC
J-5
83
033
P-9
137
087
H-12
191
0141
A-8
30
FR
J-1
84
034
N-9
138
088
H-14
192
0142
C-8
31
CL
J-2
85
035
M-9
139
089
H-15
193
0143
E-7
32
OSC2
J-3
86
036
R-10
140
090
H-13
194
0144
A-7
33
OSC1
J-4
87
037
P-10
141
091
G-11
195
0145
B-7
34
T2
K-1
88
038
N-10
142
092
G-15
196
0146
C-7
35
T1
K-2
89
039
M-10
143
093
G-14
197
0147
D-7
K-3
90
040
R-11
144
094
G-13
198
0148
A-6
36
VSS
37
CAP1+
K-4
91
041
L-10
145
095
G-12
199
0149
B-6
38
CAP1−
L-1
92
042
P-11
146
096
F-15
200
0150
C-6
39
CAP2+
K-5
93
043
N-11
147
097
F-14
201
0151
D-6
40
CAP2−
L-2
94
044
R-12
148
098
F-13
202
0152
A-5
L-3
95
045
M-11
149
099
F-12
203
0153
E-6
41
VOUT
42
V5
M-1
96
046
K-9
150
0100
E-15
204
0154
B-5
L-4
97
047
P-12
151
0101
F-11
205
0155
C-5
43
VR
J-6
98
048
R-13
152
0102
E-14
206
0156
A-4
44
VDD
45
V1
M-2
99
049
N-12
153
0103
E-13
207
0157
D-5
N-1
100
050
L-11
154
0104
D-15
208
0158
F-7
46
V2
47
V3
M-3
101
051
P-13
155
0105
E-12
209
0159
B-4
L-5
102
052
R-14
156
0106
G-10
210
0160
A-3
48
V4
N-2
103
053
N-13
157
0107
D-14
211
0161
C-4
49
V5
50
00
P-1
104
054
R-15
158
0108
C-15
212
0162
E-5
51
01
N-3
105
055
P-14
159
0109
D-13
213
0163
B-3
52
02
R-1
106
056
M-12
160
0110
F-10
214
0164
A-2
53
03
P-2
107
057
P-15
161
0111
C-14
215
0165
C-3
54
04
M-4
108
058
N-14
162
0112
B-15
216
COMI
A-1
174-3.0
S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
N/C
J-7
H-7
G-7
J-8
H-8
G-8
J-9
H-9
G-9
83
6.9
6.9 SED1560TQA OL Dimensions
6.9 SED1560TQA OL DIMENSIONS
100% Sn
110 +/– 15uM
[90(+10,–20uM)]
190uM
0.5 +/–0.1uM
CU
CU
25 +/–1uM
Adhesive
300uM
Polymide Film
Figure 6.8 SED1560TQA OL Dimensions
S-MOS assumes no responsibility or liability for (1) any errors or inaccuracies contained in the
information herein and (2) the use of the information or a portion thereof in any application,
including any claim for (a) copyright or patent infringement or (b) direct, indirect, special or
consequential damages. There are no warranties extended or granted by this document. The
information herein is subject to change without notice from S-MOS.
October 1996
© Copyright 1996 S-MOS Systems, Inc.
Printed in U.S.A.
84 S-MOS Systems, Inc. • 150 River Oaks Parkway • San Jose, CA 95134 • Tel: (408) 922-0200 • Fax: (408) 922-0238
174-3.0
174-3.0