SED1520 CMOS Dot Matrix LCD Driver Data Sheet and Design Guide S-MOS SYSTEMS, INC. 1 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 2 Table of Contents SED1520 Contents 1.0 Overview .................................................................................................................................................. 7 1.1 Description .................................................................................................................................... 7 1.2 Features ........................................................................................................................................ 7 1.2.1 SED1520 family specifications ....................................................................................... 7 1.3 Block Diagram ............................................................................................................................... 8 1.4 Package ........................................................................................................................................ 9 1.4.1 Pin Configuration Table .................................................................................................. 9 2.0 Pin Description ...................................................................................................................................... 13 2.1 Power Signals ............................................................................................................................. 13 2.2 System Bus Interface Signals ..................................................................................................... 13 2.3 LCD Drive Circuit Signals ............................................................................................................ 13 3.0 Description of Circuit Blocks ............................................................................................................... 17 3.1 MPU Interface ............................................................................................................................. 17 3.1.1 Selection of Interface Type ........................................................................................... 17 3.1.2 Identification of Data Bus Signals ................................................................................. 17 3.1.3 Access to Display Data RAM and Internal Register ..................................................... 17 3.2 Busy Flag .................................................................................................................................... 17 3.3 Display Start Line Register .......................................................................................................... 17 3.4 Column Address Counter ............................................................................................................ 18 3.5 Page Register .............................................................................................................................. 18 3.6 Display Data RAM ....................................................................................................................... 19 3.7 Common Timing Generator ......................................................................................................... 19 3.8 Display Data Latch Circuit ........................................................................................................... 19 3.9 LCD Driver Circuit ....................................................................................................................... 19 3.10 Display Timing Generator .......................................................................................................... 19 3.11 Oscillation Circuit ....................................................................................................................... 19 3.12 Reset Circuit .............................................................................................................................. 22 4.0 Commands ............................................................................................................................................. 27 4.1 Display ON/OFF .......................................................................................................................... 28 4.2 Display Start Line ........................................................................................................................ 28 4.3 Set Page Address ....................................................................................................................... 28 4.4 Column Address .......................................................................................................................... 28 4.5 Read Status ................................................................................................................................. 28 4.6 Write Display Data ....................................................................................................................... 29 4.7 Read Display Data ...................................................................................................................... 29 4.8 Select ADC .................................................................................................................................. 29 4.9 Static Drive ON/OFF ................................................................................................................... 29 4.10 Select Duty ................................................................................................................................ 29 4.11 Read Modify Write ..................................................................................................................... 29 4.12 End ............................................................................................................................................ 30 4.13 Reset ......................................................................................................................................... 30 4.14 Save Power (Combined Command) .......................................................................................... 30 (continued) S-MOS SYSTEMS, INC. 3 SED1520 Table of Contents 5.0 Electrical Characteristics ..................................................................................................................... 35 5.1 Absolute Maximum Ratings ......................................................................................................... 35 5.2 DC Characteristics ...................................................................................................................... 36 5.3 Timing Characteristics ................................................................................................................. 38 5.3.1 System Bus Read/Write I (80 family MPU)................................................................... 38 5.3.2 System Bus Read/Write II (68 family MPU).................................................................. 39 5.3.3 Display Control Timing ................................................................................................. 40 6.0 MPU Interface (Reference) ................................................................................................................... 43 7.0 LCD Driver Interconnections ............................................................................................................... 47 8.0 Typical Connections with LCD Panel .................................................................................................. 51 9.0 Package Dimensions (Reference) ....................................................................................................... 55 S-MOS SYSTEMS, INC. 4 1.0 Overview S-MOS SYSTEMS, INC. 5 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 6 1.0 – 1.2.1 1.0 Overview 1.0 Overview 1.2 Features 1.1 Description • Direct display of data read from display data RAM RAM bit data: ‘0’ — LCD off ‘1’ — LCD on The SED1520 is a dot matrix LCD driver LSI intended for display of characters and graphics. It generates LCD driving signals based on bit image display data supplied from an 8-bit or 16-bit microcomputer and stored in the on-chip display data RAM. • Fast 8-bit MPU interface; direct interface with 80- or 68-family microcomputer • On-chip LCD driving circuits — 80 (segment + common) driver sets The SED1520 incorporates innovative circuit design strategies to assure very low current dissipation and a wide range of operating voltages. With these features, the SED1520 permits the user to implement high-performance handy systems operating from a miniature battery. • Duty ratios to choose from: Command setup (SED1520F) External input sync (SED1521F) In order for the user to adaptively configure his system, the SED1520 family offers two application forms. One form allows an LCD display of 12 characters × 2 lines with an indicator with a single chip. The other is dedicated to driving a total of 80 segments, enabling a medium-size display to be achieved by using a minimum number of drivers. 1/16, 1/32 1/8 to 1/32 • A variety of command functions, including: Read/Write Display Data, Display ON/ OFF, Set Address, Set Display Start Line, Set Column Address, Read Status, Static Drive ON/OFF, Select Duty, Read Modify Write, Select Segment Driving Selection, Save Power, etc. • Very low power dissipation — 30 µW maximum (External clock operation: 2 kHz) • Wide spectrum of supply voltages VDD – VSS VDD – V5 • CMOS process –2.4V to –7.0V –3.5V to –13.0V 1.2.1 SED1520 family specifications Product Name SED1520F0A SED1521F0A SED1520FAA SED1521FAA Clock Frequency On-chip External 18 kHz 18 kHz — — — 18 kHz 2 kHz 2 kHz Applicable Driver No. of SEG Drivers No. of COM Drivers SED1520F 0A, SED1521F0A 61 16 80 61 80 0 16 0 SED1520FAA, SED1521FAA, HD44103CH S-MOS SYSTEMS, INC. 7 1.0 Overview 1.3 CL (OSC2) FR 1.3 Block Diagram DISPLAY START LINE REGISTER BUS HOLDER COMMON COUNTER CM0 ~ CM15 LINE ADDRESS DECODER I/O BUFFER LOW ADDRESS REGISTER INTERNAL BUS S-MOS SYSTEMS, INC. 8 LCD DRIVER CIRCUIT DISPLAY DATA RAM 2560 BITS V1, V4, M/S DISPLAY DATA LATCH CIRCUIT COLUMN ADDRESS DECODER RES V2, V3, V5 (SG61 ~ SG76) COLUMN ADDRESS COUNTER E , R/W (RD)(WR) STATUS A0, CS (OSC1) MPU INTERFACE D0 ~ D7 LINE COUNTER GENERATOR COLUMN ADDRESS REGISTER COMMAND DECODER DISPLAY TIMING (SG77 ~ SG79) SG0 ~ SG60 VDD VSS 1.4 1.0 Overview 85 90 1 95 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG60 SEG59 SEG58 SEG57 SEG56 SEG55 SEG54 SEG53 SEG52 SEG51 SEG50 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 100 COM4 COM3 COM2 COM1 COM0 V1 V4 M/S V2 V3 V5 FR RES VDD DB7 DB6 DB5 DB4 DB3 DB2 1.4 Package DB1 DB0 VSS R/W, (WR) E(RD) CL(OSC2) CS(OSC1) A0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 80 5 75 10 70 15 65 20 60 25 50 45 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 30 40 35 55 * The pin configuration on the SED1520F is shown here. 1.4.1 Pin Configuration Table Product Name Pin Number SED1520F0A 74 OSC1 75 OSC2 96 ~ 100, 1 – 1j COM0 ~ COM15 93 M/S 94 V4 95 V1 SED1521F0A SED1520FAA SED1521FAA CS CS CS CL CL CL SEG76 ~ SEG61 COM0 ~ COM15* SEG76 ~ SEG61 SEG79 M/S SEG79 SEG78 V4 SEG78 SEG77 V1 SEG77 * Master LSI common outputs COM0 — COM15 correspond to slave LSI outputs COM31 — COM16. S-MOS SYSTEMS, INC. 9 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 10 2.0 Pin Description S-MOS SYSTEMS, INC. 11 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 12 2.0 – 2.3 2.0 Pin Description 2.0 Pin Description 2.1 Power Signals • CS Chip Select input signal which is normally obtained by decoding an address bus signal. Effective with “L” active and a chip operating with external clocks. For a chip containing an oscillator, CS works as an oscillation amplifier input pin to which an oscillation resistor (Rf) is connected. In this case, RD, WR and E must be a signal ANDed with CS. • VDD Connected to +5V power. Common to MPU power pin VCC. • VSS 0V, connected to system GND. • V1 – V5 • E (RD) • Chip interfaced with 68-family MPU: Enable Clock signal input for the 68family MPU. • Chip interfaced with 80-family MPU: “L” active input pin to which the 80-family MPU RD signal is connected. With this signal held at “L”, the SED1520 data bus works as output. Multi-level power used to drive LCDs. Voltage specified to each LCD cell is divided by resistors or impedance-converted by an operational amplifier before being applied. Each voltage to be applied must be based on VDD, while fulfilling the following conditions: VDD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 2.2 System Bus Interface Signals • R/W (WR) • D7 – D0 • Chip interface with 68-family MPU: Read/write control signal input pin. R/W = “H” : Read 8-bit, tri-state, bi-directional I/O bus. Normally, connected to the data bus of an 8-/16-bit standard microcomputer. R/W = “L” : Write • Chip interfaced with 80-family MPU: “L” active input pin to which the 80-family WR is connected. The signal on the data bus is fetched by the leading edge of WR. • A0 Input pin. Normally, the LSB of the MPU address bus is connected to this input pin to provide data/command selection. 0 : Display control data on D0 — D7 1 : Display data on D0 — D7 2.3 LCD Drive Circuit Signals • RES Input pin. The SED1520 can be reset or initialized by setting RES to low level (if it is interfaced with a 68-family MPU) or high level (if with an 80-family MPU). This reset operation occurs when an edge of the RES signal is sensed. The level input selects the type of interface with the 68- or 80-family MPU: • CL Input signal effective with a chip using external clocks. This display data latch signal increments the line counter (at the trailing edge) or the common counter (at the leading edge). CL is connected to CL2 of the common driver. For a chip containing an oscillator, this pin works as the oscillation amplifier output pin to which an oscillation resistor (Rf) is connected. High level : Interface with 68-family MPU Low level : Interface with 80-family MPU S-MOS SYSTEMS, INC. 13 2.0 Pin Description 2.3 counter and the FR signal. The common (row) scanning order for the slave LSI is reverse to that for the master LSI. • FR LCD AC signal I/O pin. Connected to pin M of the common driver. • I/O selection: Chip containing commons M/S = 1: Output 1 FR M/S = 0: Input Chip containing segments alone : Input Counter Output Output Level • SEG0 – SEG79 LCD column (segment) driving output. One of the VDD, V2, V3 and V5 levels is selected by a combination of the content of display RAM and the FR signal. 1 FR DATA Output Level 1 0 1 0 V2 V5 V3 1 0 1 0 VS V1 VDD V4 • M/S (SEG79) Input signal which selects the master or slave LSI. Connected to VDD or VSS. M/S = VDD : Master M/S = VSS : Slave M/S selection changes the function of pins FR, COM0 – COM15, OSC1 (CS) and OSC2 (CL): 0 VDD 0 M/S FR VDD Output VSS Input • COM0 – COM15 (COM31 – COM16) LCD common (row) driving output. One of the VDD, V1, V4 and V5 levels is selected by a combination of the output of the common COM output COM0 – COM15 COM31 – COM16 OSC1 OSC2 Input Output NC Input * The common scanning order for the slave driver is reverse to that for master. S-MOS SYSTEMS, INC. 14 1.4 2.0 Pin Description 3.0 Description of Circuit Blocks S-MOS SYSTEMS, INC. 15 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 16 3.0 – 3.3 3.0 Description of Circuit Blocks 3.0 Description of Circuit Blocks 3.1 MPU Interface data read cycle (dummy), the data is stored on the bus holder. In the next data read cycle, the data is read from the bus holder to the system bus. Also consider the case where the MPU writes data to the display data RAM. In the first data write cycle, the data is held on the bus holder. The data is written to the display data RAM before the next data write cycle begins. Therefore, MPU’s access to the SED1520 is affected not by display data RAM access time (t ACC, t DS) but by cycle time (t CYC). This leads to faster transfer of data to and from the MPU. If the cycle time requirement is not met, the MPU has only to execute the NOP instruction and this is apparently equivalent to execution of a waiting operation. However, there is a restriction on the read sequence of the display data RAM; when an address is set, its data is output not to the first read instruction (immediately following the address setting operation) but to the second read instruction. Thus, one dummy read cycle is necessary after an address set or write cycle. This relation is shown in Figure 3.1. 3.1.1 Selection of Interface Type The SED1520 Series uses 8 bits of bi-directional data bus (D0 – D7) to transfer data. The reset pin is capable of selecting MPU interface; setting the polarity of RES to either “H” or “L” can provide direct interface of the SED1520 with a 68- or 80-family MPU (see Table 3.1 below). With CS at high level, the SED1520 is independent from the MPU bus and stays in standby mode. In this mode, however, the reset signal is input independently of the internal status. Table 3.1 Polarity of Type A0 RES “L” active 68 MPU ↑ “H” active 80 MPU ↑ R R/W CS D0 – D7 ↑ ↑ RD WR ↑ ↑ ↑ ↑ 3.2 Busy Flag 3.1.2 Identification of Data Bus Signals Busy flag being “1” means that the SED1520 is performing its internal operation and any instruction other than Read Status is disabled. The busy flag is output to pin D7 by a Read Status instruction. As long as the cycle time (t CYC) requirement is met, the flag need not be checked before each command and this dramatically improves the MPU performance. The SED1520 uses a combination of A0, E, R/W, (RD, WR) to identify a data bus signal. Table 3.2 Common 68 MPU A0 R/W RD 80 MPU WR 1 1 0 1 Read display data 1 0 1 0 Write display data 0 1 0 1 Read status 0 0 1 0 Function 3.3 Display Start Line Register Write to internal register (command) This register is a pointer which determines the start line corresponding to COM0 (normally, the uppermost line of display) for display of data in the display data RAM. It is used for scrolling the display or changing the page from one to another. 3.1.3 Access to Display Data RAM and Internal Register Executing the Set Display Start Line command sets 5 bits of display start address in this register. Its content is preset in the line counter at each timing the FR signal changes. The line counter is incremented synchronously to a CL input, thus, generating a line address for sequential reading of 80 bits of data from the display data RAM to the LCD driver circuit. In order to make matching of operating frequencies between the MPU and the display data RAM or internal register, the SED1520 performs a sort of LSILSI pipelining via the bus holder attached to the internal data bus. Consider the case where the MPU reads the content of the display data RAM. In the first S-MOS SYSTEMS, INC. 17 3.0 Description of Circuit Blocks 3.3 – 3.5 ❍ Write WR MPU DATA Internal Timing N N+1 Bus Holder N+2 N N+1 N+3 N+2 N+3 WR ❍ Read WR RD MPU DATA N N n n+1 Address set at N Dummy read Data read at N Data read at N+1 WR Internal Timing RD Column Address N Bus Holder N+1 N n N+2 n+1 n+2 Figure 3.1 3.4 Column Address Counter 3.5 Page Register The column address counter is a 7-bit presettable counter which gives column addresses of the display data RAM as shown in Figure 3.3. When a Read/Write Display Data command comes in, the counter is incremented by 1. For any nonexisting address over 50H, the counter is locked and not incremented. This register gives a page address of the display data RAM as shown in Figure 3.3. The Set Page Address command permits the MPU to access a new page of the display data RAM. The column address counter is independent from the page register. S-MOS SYSTEMS, INC. 18 3.6 – 3.11 3.0 Description of Circuit Blocks 3.6 Display Data RAM 3.9 LCD Driver Circuit Dot data for display is stored in this RAM. Since the MPU and LCD driver circuit operate independently of each other, data can be changed asynchronously without adverse effect on the display. This circuit generates 80 sets of multiplexer that generate quartet levels for LCD driving. Display data in the display data latch, common timing generator output and FR signal are combined to output an LCD driving waveform. One bit of the display data RAM is assigned to one bit of LCD: LCD on = “1” LCD off = “0” 3.10 Display Timing Generator This circuit generates an internal display timing signal from the basic clock (CL) and frame signal (FR). The ADC command inverts the assignment relationship between a display data RAM column address and a segment output (see Figure 3.3). The frame signal FR makes the LCD driver circuit generate a dual frame AC driving waveform (type B) to drive LCD, while making both the line counter and common timing generator synchronized to the FR signal output LSI (dedicated common driver or the SED1520 master LSI). To achieve these functions, the FR signal must be a clock with a duty of 50% which is synchronized to the frame period. The clock CL is a clock used to operate the line counter. For a system in which both the SED1520 and SED1521F coexist, they should be of LSI types having the same clock frequency to be applied to pin CL. 3.7 Common Timing Generator This circuit generates common timing and frame (FR) signals from the basic clock (CL). The Select Duty command selects a duty of 1/16 or 1/32. The 1/32 duty is achieved by a two-chip (master and slave) configuration (common multi-chip system). 3.8 Display Data Latch Circuit 3.11 Oscillation Circuit The display data latch circuit temporarily stores the data which will be output from the display data RAM to the LCD driver circuit at one-common intervals. The Display ON/OFF and Static Driver ON/OFF commands control the latched data so that the data in the display data RAM remains unchanged. This circuit is a low-power CR oscillator which uses an oscillation resistor Rf alone to adjust the oscillation frequency. It generates display timing signals. The SED1520 is available in two LSI types if classified by oscillation: one LSI type contains an oscillation circuit and the other uses an externally provided clock. FR (Master Output) Master Common Slave Common 0 1 2 14 15 0 16 17 1 30 31 Figure 3.2 S-MOS SYSTEMS, INC. 19 15 16 17 31 DATA Column Address Page address D1,D2=0,0 Line address Associated Assignment Line (ex.) Start 1/16 Common output COM 0 COM 1 COM 2 COM 3 COM 4 COM 5 COM 6 COM 7 COM 8 COM 9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 COM31 S-MOS SYSTEMS, INC. Page 0 Page 1 Page 2 Page 3 00H 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Display Area (In this example, the display start line is set at address 08.) 20 0,1 1,0 1,1 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 4D 4E 4F 02 01 00 SEG77 SEG78 SEG79 D0 = 1 D0 = 0 4F 00H 4E 01 4D 02 4C 03 4B 04 4A 05 49 06 48 07 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 ADC SEG Pin 3.6 – 3.11 3.0 Description of Circuit Blocks Figure 3.3. Relationship between Display Data RAM Locations and Addresses (Display Start Line: 08) 3.6 – 3.11 3.0 Description of Circuit Blocks VDD Master LSI Slave LSI M/S M/S (CS) OSC1 (CL) OSC2 Rf VDD (CS) OSC1 (CL) OSC2 Open *2 *1 *1 As the parasitic capacitance in this portion increases, the oscillation frequency will shift to a lower level. The Rf must have a smaller value than the specification. *2 For a system having two or more slave LSIs, a CMOS buffer is necessary. Figure 3.4. LSI containing oscillator Y–Driver SED1521FAA CL2 CL Figure 3.5. LSI operating with external clock S-MOS SYSTEMS, INC. 21 3.0 Description of Circuit Blocks 3.11 – 3.12 The oscillation resistor Rf is connected as shown below. Where an LSI containing an oscillation circuit is operated with an external clock, it is necessary to input the clock with the same phase as OSC2 of the master LSI to OSC2 of the slave LSI. The input at pin RES is level-sensed to select an MPU interface mode as shown in Table 3.1. For interfacing with an 80-family MPU, an “H” active reset signal is input to pin RES. For interfacing with a 68-family MPU, an “L” active reset signal is input to the pin (see Figure 6.1). 3.12 Reset Circuit As exemplified in chapter 6.0, “Interface with MPU,” pin RES is connected to the MPU reset pin. Thus, the SED1520 and the MPU are initialized at the same time. If system is initialized by pin RES at power-on, it may no longer be reset. This circuit senses the leading edge or trailing edge of RES and initializes the system when its power is switched on. Initialization: (a) Display off The Reset command causes initialization (b), (d) and (e). (b) Display start line register: First line (c) Static drive off (d) Column address counter: Address 0 (e) Page address register: Page 0 (f) Select duty: 1/32 (g) Select ADC: Forward (ADC command D0 = “0”, ADC status flag = “1”) (h) Read modify write off S-MOS SYSTEMS, INC. 22 3.11 – 3.12 3.0 Description of Circuit Blocks 0 1 2 3 0 1 2 3 COM 0 1 2 3 4 5 6 7 8 9 10 15 0 1 2 3 31 0 1 2 3 FR VDD VSS COM 0 VDD V1 V2 V3 V4 V5 COM 1 VDD V1 V2 V3 V4 V5 COM 2 VDD V1 V2 V3 V4 V5 SEG 0 VDD V1 V2 V3 V4 V5 SEG 1 VDD V1 V2 V3 V4 V5 COM 0 – SEG 0 V5 V4 V3 V2 V1 VDD –V1 –V2 –V3 –V4 –V5 COM 0 – SEG 1 V5 V4 V3 V2 V1 VDD –V1 –V2 –V3 –V4 –V5 11 12 4 3 2 1 SEG 0 13 14 15 15 31 Figure 3.6. Examples of LCD Driving Waveform S-MOS SYSTEMS, INC. 23 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 24 4.0 Commands S-MOS SYSTEMS, INC. 25 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 26 4.0 4.0 Commands 4.0 Commands Table 4.1 lists the commands used with the SED1520. This LSI uses a combination of A0, R/W, (RD, WR) to identify a data bus signal. Interpretation and execu- tion of a command depends not on external clock but on internal timing alone. Therefore, a command can be executed so fast that no busy check is needed. Table 4.1. Commands Command (1) Display ON/OFF Code Function A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 1 1 0/1 Turns all display on or off, independently of display RAM data or internal status. Display Start Line 0 1 0 1 1 0 (3) Set Page Address 0 1 0 1 0 1 (4) Set Column (Segment) Address 0 1 0 0 Column Address (0–79) (5) Read Status 0 0 1 0 Display Start Address (0 – 31) RESET 1 ON/OFF ADC (2) Busy 1: ON 0: OFF (Power-saving mode with static drive on)* 1 0 0 Specifies RAM line corresponding to uppermost line (COM0) of display. Page (0–3) 0 Sets display RAM page in page address register. Sets display RAM column address in column address register. 0 Reads the following status: BUSY ADC 1: Internal operation 0: Ready 1: CW output (forward) 0: CCW output (reverse) ON/OFF 1: Display off 0: Display on RESET 1: Being reset 0: Normal (6) Write Display Data 1 1 0 Write Data Writes data from data bus into display RAM. (7) Read Display Data 1 0 1 Read Data Reads data from display RAM onto data bus. (8) Select ADC 0 1 0 1 0 1 0 0 0 0 0/1 Display RAM location whose address has been preset is accessed. After access, the column address is incremented by 1. Used to invert relationship of assignment between display RAM column addresses and segment driver outputs. 0: CW output (forward) 1: CCW output (reverse) (9) Static Drive ON/OFF 0 1 0 1 0 1 0 0 1 0 0/1 Selects normal display or static driving operation. 1: Static drive (power-saving mode) 0: Normal driving (10) Select Duty 0 1 0 1 0 1 0 1 0 0 0/1 Selects LCD cell driving duty 1: 1/32 0: 1/16 (11) Read Modify Write 0 1 0 1 1 1 0 0 0 0 0 Increments column address counter by 1 when display data is written. (This is not done when data is read.) (12) End 0 1 0 1 1 1 0 1 1 1 0 Clears read modify write mode. (13) Reset 0 1 0 1 1 1 0 0 0 1 0 Sets display start line register on the first line. Also sets column address counter and page address counter to 0. * With display off (command (1)), static drive going on (9) invokes power-saving mode. A detailed description of all the commands follows. S-MOS SYSTEMS, INC. 27 4.0 Commands 4.1 – 4.5 4.1 Display ON/OFF 4.4 Column Address This command forces all display to turn on or off. This command specifies a display data RAM column address. The column address is incremented by 1 each time the MPU accesses from the set address to the display data RAM. Thus it is possible for the MPU to gain continuous access to only the data. This incrementing stops with address 80; the page address is not continuously changed. R/W A0 RD WR D7 0 1 0 D6 D5 1 0 D4 D3 1 0 1 D2 D1 1 D0 1 D Note: D = 0 Display OFF D = 1 Display ON R/W A0 RD WR D7 D6 4.2 Display Start Line 0 This command specifies a line address (shown in Figure 3.3) thus marking the display line that corresponds to COM0. Display begins with the specified line address and covers as many lines as match the display duty in address ascending order. Dynamic line address change with the Display Start Line command enables column-wise scrolling or page change. 1 A6 0 A5 A4 0 A6 A3 A2 D5 D4 D3 D2 D1 D0 A5 A3 A1 A4 A2 Column Address A1 A0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ↓ 1 0 0 1 A0 ↓ 1 1 1 79 R/W A0 RD WR D7 0 1 0 D6 D5 1 1 0 D4 D3 D2 D1 D0 A4 A2 A0 A3 A1 4.5 Read Status ← High order bits R/W A4 A3 A2 A1 A0 Line Address 0 0 0 0 0 0 0 0 0 0 1 1 ↓ 1 1 A0 RD WR D7 D6 0 1 1 31 0 D6 D5 1 0 1 0 0 0 0 0 : Inverted (column address 79 – n ↔ segment driver n) 1 : Forward (column address n ↔ segment driver n) ON/OFF Indicates display on or off. 0 : Display on 1 : Display off This bit has polarity reverse to the Display ON/ OFF command. R/W 1 ADC ADC Indicates assignment of column addresses to segment drivers. This command is used to specify a page address equivalent to a row address for MPU access to the display data RAM. A required bit of the display data RAM can be accessed by specifying its page address and column address. Changing the page address causes no change in display. 0 BUSY D1 D0 BUSY BUSY being “1” means that system is performing an internal operation or is reset. No command is accepted before BUSY = “0”. As long as the cycle time requirement is met, no BUSY check is needed. 4.3 Set Page Address A0 RD WR D7 1 D3 D2 Note: ↓ 1 0 D5 D4 ON / OFF RESET D4 D3 1 1 D2 D1 0 A1 D0 RESET Indicates that system is being initialized by the RES signal or the Reset command. A0 0 : Display mode A1 A0 Page A1 A0 Page 0 0 0 1 0 2 0 1 1 1 1 3 1 : Being reset S-MOS SYSTEMS, INC. 28 4.6 – 4.11 4.0 Commands 4.6 Write Display Data 4.9 Static Drive ON/OFF This command allows the MPU to write 8 bits of data into the display data RAM. Once the data is written, the column address is automatically incremented by 1; this enables the MPU to write multi-word data continuously. This command forces all display to be on and, at the same time, all common output to be selected. R/W A0 RD WR D7 0 R/W A0 RD WR D7 1 1 D6 D5 0 D4 D3 D2 D1 1 0 1 D6 D5 0 1 D4 D3 0 0 D2 D1 1 0 D0 D Note: D = 0 Static drive off D = 1 Static drive on D0 WRITE DATA 4.7 Read Display Data 4.10 Select Duty This command allows the MPU to read 8 bits of data from the display data RAM location specified by a column address and a page address. Once the data is read, the column address is automatically incremented by 1; this enables the MPU to read multiword data continuously. This command is used to select the duty (degree of multiplexity) of LCD driving. It is valid for the SED1520F (actively operating LSI) only, not valid for the SED1521F (passively operating LSI). The SED1521F operates with any duty determined by the FR signal. R/W A0 RD WR D7 A dummy read is needed immediately after the column address is set. For details, see 3. (1) – (c). 0 1 0 D6 D5 1 D4 D3 D2 D1 D0 READ DATA This command inverts the relation of assignment between display data RAM column addresses and segment driver outputs. In other words, the Select ADC command can software-invert the order of segment driver output pins, reducing the restrictions on the configuration of ICs at LCD module assembly. For details, see Figure 3.3. 0 Note: D=0 D=1 1 0 1 0 1 0 0 1 0 1 0 0 D This command is used with the End command in a pair. Once it has been entered, the column address will be incremented, not by the Read Display Data command, but by the Write Display Data command only. This mode will stay until the End command is entered. Entry of the End command causes the column address to return to the address which was valid when the Read Modify Write command was entered. This function lessens the load of the MPU when the data in a specific display area are repeatedly updated (as blinking cursor). R/W D4 D3 0 D0 4.11 Read Modify Write Incrementing the column address by 1, which takes place after the MPU writing or reading display data, follows the sequence of column addresses specified in Figure 3.3. D6 D5 1 D2 D1 If the system contains both SED1520F0A (internal oscillation) and the SED1521F0A LSIs, they must have the same duty. 4.8 Select ADC A0 RD WR D7 0 D4 D3 Note: D = 0 Duty 1/16 D = 1 Duty 1/32 R/W A0 RD WR D7 1 D6 D5 D2 D1 0 0 D0 0 R/W Clockwise output (forward) Counterclockwise output (reverse) A0 RD WR D7 0 1 0 1 S-MOS SYSTEMS, INC. 29 D6 D5 1 1 D4 D3 0 0 D2 D1 0 0 D0 0 4.0 Commands 4.11 – 4.14 4.13 Reset * Even in the Read Modify Write mode, any command other than Read/Write Data and Set Column Address may be used. This command initializes the display start line register, column address counter, and page address counter without any effect on the display data RAM. For details, see 6-(12). Page Address Set The reset operation follows entry of the Reset command. Column Address Set R/W Read–Modify–Write Cycle A0 RD WR D7 D6 0 1 0 1 1 D5 D4 1 0 D3 D2 0 D1 D0 0 1 0 Dummy Read Initialization at power-on is performed, not by the Reset command, but by a reset signal applied to the RES pin. Data Read Data Write 4.14 Save Power (Combined Command) No Changes Finished? Static drive going on with display off invokes powersaving mode, reducing current consumption to nearly static current level. During this mode, the SED1520 holds the following conditions: END • It stops driving the LCD; the segment and common driver outputs are at VDD level. • Oscillation and external clock input are disabled; OSC2 is in floating condition. • The display data and operational mode are held. Figure 4.1. Cursor blinking sequence 4.12 End This command cancels the Read Modify Write command, returning the column address to the initial mode address. See Figure 4.2. The power-saving mode is cancelled by display on or static drive off. R/W A0 RD WR D7 0 1 0 Column Address 1 D6 D5 1 D4 D3 1 0 1 D2 D1 1 1 If an external resistor division circuit is used to give LCD driving voltage level, the current flowing into the resistors must be cut off by the power-save signal. D0 0 Return N N+1 N+2 Read modify write mode set Figure 4.2 S-MOS SYSTEMS, INC. 30 N+m N End 4.14 4.0 Commands VDD VDD V1 V2 SED1520 V3 V4 V5 Power save signal VSSH Figure 4.3 S-MOS SYSTEMS, INC. 31 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 32 5.0 Electrical Characteristics S-MOS SYSTEMS, INC. 33 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 34 5.0 – 5.1 5.0 Electrical Characteristics 5.0 Electrical Characteristics 5.1 Absolute Maximum Ratings Parameter Supply voltage (1) Supply voltage (2) Supply voltage (3) Input voltage Output voltage Allowable loss Operating temperature Storage temperature Soldering temperature/time Symbol VSS Condition –8.0 ~ +0.3 Unit V V5 V1, V4, V2, V3 VIN –16.5 ~ +0.3 V5 ~ +0.3 VSS – 0.3 ~ +0.3 V V V V0 PD Topr VSS – 0.3 ~ +0.3 250 –30 ~ +85 V mW °C Tstg Tsolder –65 ~ +150 260 / 10 (at lead) °C °C / Sec Notes: 1. All voltages are based on V DD = 0V. 2. The following condition must always hold true with voltages V1, V2, V3, V4 and V5: V DD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ V5 3. The LSI may be permanently damaged if used with any value in excess of the absolute maximum ratings. During normal operation, the LSI should preferably be used within the specified electrical characteristics. Failure to meet them can cause the LSI to malfunction or lose its reliability. 4. Generally, flat package LSIs may have moisture resistance lowered when solder dipped. In mounting LSIs on a board, it is recommended to use a method which is least unlikely to give thermal stress on the package resin. S-MOS SYSTEMS, INC. 35 5.0 Electrical Characteristics 5.2 5.2 DC Characteristics Parameter Operating voltage (1) Recommended Allowable Recommended Operating voltage (2) Allowable VDD = 0V, Ta = –20 to 75°C Symbol Condition VSS *1 V5 Min Typ Max –5.5 –5.0 –4.5 –7.0 — –2.4 –13.0 — –3.5 –13.0 — — Unit Applicable Pin V VSS V V5 *10 Allowable V1, V2 0.6 × V5 — VDD V V1, V2 Allowable V3, V4 V5 — 0.4 × V5 V V3, V4 VIHT VSS + 2.0 — VDD VIHC 0.2 × VSS — VDD VILT VSS — V SS + 0.8 VILC VSS — 0.8 × VSS High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage VOHT I OH = –3.0 mA VSS + 2.4 — — VOHC1 I OH = –2.0 mA VSS + 2.4 — — VOHC2 I OH = –120 µA V V *2 *3 *2 *3 *4 V *5 0.2 × VSS — — OSC2 VOLT I OL = 3.0 mA — — V SS + 0.4 *4 VOLC1 I OL = 2.0 mA — — V SS + 0.4 VOLC2 I OL = 120 µA V *5 — — 0.8 × VSS Input leakage current ILI –1.0 — 1.0 µA *6 Output leakage current I LO –3.0 — 3.0 µA *7 LCD driver ON resistor RON Ta = 25°C Static current dissipation IDDQ CS = CL = VDD Dynamic current dissipation IDD (1) IDD (2) Input pin capacitance CIN Oscillation frequency fOSC Reset time During display V5 = –5.0V V5 = –5.0V — 5.0 7.5 V5 = –3.5V — 10.0 50.0 1.0 — 0.05 fCL = 2 kHz — 2.0 5.0 Rf = 1 MΩ — 9.5 15.0 OSC2 kΩ µA SEG0~79 *11 COM0~15 VDD VDD *12 µA *13 fCL = 18 kHz — 5.0 10.0 During access tcyc = 200 kHz — 300 500 µA *8 Ta = 25°C — 5.0 8.0 pF All input pins R f = 1.0 MΩ ± 2% VSS = –5.0V 15 18 21 R f = 1.0 MΩ ± 2% VSS = –3.0V 11 16 21 kHz *9 1.0 — 1000 µs RES f = 1 MHz tR Notes: *14 access is nearly proportionate to access frequency (tCYC). Only TDD (1) is consumed while no access is made. *1. Operation over a wide range of voltages is guaranteed, except where a sudden voltage change occurs during access. *9. Relationship between the oscillation frequency, frame and Rf (see Figures 5.1 – 5.3). *2. Pins A0, D0 – D7, E (RD), R/W (WR) and CS *10. Operating voltage ranges of VSS and V5 (see Figure 5.4). *3. Pins CL, FR, M/S and RES *11. Resistance with a voltage of 0.1V applied between the output pin (SEG, COM) and each power pin (V1, V2, V3, V4). It is specified within the operating voltage range. *4. Pins D0 – D7 *5. Pin FR *12, 13, 14. Current consumed by each discrete IC, not including LCD panel and wiring capacitances. *6. Pins A0, E (RD), R/W (WR), CS, CL and RES *7. Applicable when pins D0 – D7 and FR are at high impedance. *12. Applicable to SED1520FAA and SED1521FAA *13. Applicable to SED1520F0A *8. This value is current consumption when a vertical stripe pattern is written at tCYC. Current consumption during *14. Applicable to SED1521F0A S-MOS SYSTEMS, INC. 36 5.2 5.0 Electrical Characteristics *9 Relation between oscillation frequency, frame and R f [SED1520F0A] Rf Ta = 25°C VSS = -5V OSC2 Duty 1/16, 1/32 Ta = 25°C VSS = -5V 200 (Hz) 30 20 Frame f OSC (KHz) 40 OSC1 10 0 0.5 1.0 1.5 2.0 100 2.5 (MΩ ) Rf 0 0.5 1.0 1.5 2.0 (MΩ ) Rf Figure 5.2 Figure 5.1 Relationship between external clock (fCL) and frame [SED1520FAA] 200 Frame (Hz) Duty 1/32 Duty 1/16 100 0 1 2 f CL 3 (KHz) Figure 5.3 *10 Operating voltage range of VSS and V5 (V) -15 V5 -10 Operating Voltage Range -5 0 -2 -4 VSS -6 -8 (V) Figure 5.4 S-MOS SYSTEMS, INC. 37 2.5 5.0 Electrical Characteristics 5.3 – 5.3.1 5.3 Timing Characteristics 5.3.1 System Bus Read/Write I (80-family MPU) Parameter Address hold time Symbol tAH8 Address setup time System cycle time Control pulse width tAW8 tCYC8 tCC Data setup time Data hold time RD access time tDS8 tDH8 tACC8 Output disable time tOH8 Signal Ta = –20 to 75°C, VSS = –5.0V ±10% Condition A0, CS WR, RD Min 10 Typ — Max — Unit ns 20 1000 200 — — — — — — ns ns ns 80 10 — — — — — — 90 ns ns ns 10 — 60 ns D0 – D7 CL = 100 pF *1 Each of the values where VSS = –3.0V is about 200% of that where VSS = –5.0V (i.e., the listed value). *2 The rise or fall time of input signals should be less than 15 ns. tAH8 A0, CS tAW8 tCYC8 tCC WR, RD tDS8 tDH8 D0 ~ D7 (WRITE) tACC8 tOH8 D0 ~ D7 (READ) Figure 5.5. System bus read/write I (80-family MPU) S-MOS SYSTEMS, INC. 38 5.3.2 5.0 Electrical Characteristics 5.3.2 System Bus Read/Write II (68-family MPU) Parameter Symbol *1 System cycle time Address setup time Address hold time tCYC6 tAW6 tAH6 Data setup time Data hold time Output disable time tDS6 tDH6 tOH6 Access time Enable pulse width: Read Enable pulse width: Write tACC6 Signal Ta = –210 to 75°C, VSS = –5.0V ±10% Condition A0, CS R/W Min Typ Max Unit 1000 20 10 — — — — — — ns ns ns 80 10 10 — — — — — 60 ns ns ns — 100 80 — — — 90 — — ns ns ns D0 – D7 CL = 100 pF E tEW *1 tCYC6 indicates the cycle time during which CS•E = “H”. It does not mean the cycle time of signal E. *2 Each of the values where V SS = –3.0V is about 200% of that where VSS = –5.0V (i.e., the listed value). *3 The rise or fall time of input signals should be less than 15 ns. tCYC6 E tAW6 tEW R/W tAH6 A0, CS tDS6 tDH6 D0 ~ D7 (WRITE) tACC6 D0 ~ D7 (READ) Figure 5.6. System bus read/write II (68-family MPU) S-MOS SYSTEMS, INC. 39 tOH6 5.0 Electrical Characteristics 5.3.3 5.3.3 Display Control Timing Input Timing Ta = –20 to 75°C, VSS = –5.0V ±10% Parameter Low level pulse width Symbol tWLCL High level pulse width Rise time Fall time tWHCL tr tf FR delay time tDFR Signal Condition CL FR Output Timing Parameter FR delay time Min 35 Typ — Max — Unit µs 35 — — — 30 30 — 150 150 µs ns ns –2.0 0.2 2.0 µs Ta = –20 to 75°C, VSS = –5.0V ±10% Symbol Signal Condition Min Typ Max Unit tDFR FR CL = 100 pF — 0.2 0.4 µs *1. The listed FR input delay time applies to the SED1521 and 1520 (slave). The listed FR output delay time applies to the SED1520 (master). *2. Each of the values where VSS = –3.0V is about 200% of that where VSS = –5.0V (i.e., the listed value). CL tWHCL tDFR tWLCL tf FR Figure 5.7. Display control timing S-MOS SYSTEMS, INC. 40 tr 6.0 MPU Interface (Reference) S-MOS SYSTEMS, INC. 41 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 42 6.0 6.0 MPU Interface (Reference) 6.0 MPU Interface (Reference) VCC A0 VDD A0 CS A2 ~ A7 Decoder IORQ MPU SED1520FAA D0 ~ D7 GND D0 ~ D7 RD RD WR WR RES RES VSS VS RESET Figure 6.1. 80-family MPU VCC A0 VDD A0 CS A0 ~ A13 Decoder VMA MPU SED1520FAA D0 ~ D7 D0 ~ D7 E GND E R/W R/W RES RES VSS RESET Figure 6.2. 68-family MPU * These examples also apply to the SED1521F 0A / SED1521FAA. * The SED1520F0A (containing an oscillator) does not have pin CS. The output ORed with CS must be applied to pins A0, RD (E) and WR (R/W). S-MOS SYSTEMS, INC. 43 VS 6.0 MPU Interface (Reference) 6.0 A0 Decoder CS SED1520FOA D0 ~ D7 RD(E) WR(R/W) RES Figure 6.3 S-MOS SYSTEMS, INC. 44 7.0 LCD Driver Interconnections S-MOS SYSTEMS, INC. 45 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 46 7.0 7.0 LCD Driver Interconnections 7.0 LCD Driver Interconnections To LCD SEG To LCD SED1520FOA (Master) To LCD COM SEG SED1520FOA (Slave) To LCD COM M/S VDD VSS M/S OSC1 OSC2 FR OSC1 OSC2 FR Rf Figure 7.1. SED1520FOA – SED1520FOA To LCD To LCD SED1520FAA (Master) To LCD COM VDD SEG SEG SED1520FAA (Slave) M/S To LCD COM M/S CL FR CL VSS FR External clock Figure 7.2. SED1520FAA – SED1520FAA To LCD SED1520FOA To LCD COM VDD To LCD SEG SEG SED1521FOA M/S OSC1 OSC2 FR OSC1 OSC2 Rf *2 Figure 7.3 SED1520FOA – SED1521FOA *1 *1. In this connection, the duty of the SED1521FOA must be the same as that of the SED1520FOA. *2. A CMOS buffer is neede for a system having two or more slave LSIs. S-MOS SYSTEMS, INC. 47 FR 7.0 LCD Driver Interconnections To LCD 7.0 To LCD SEG SED1520FAA To LCD COM SEG SED1521FAA M/S VDD CL FR CL FR External clock Figure 7.4. SED1520FAA – SED1521FAA To LCD To LCD COM HD44103CH Common Driver CL SEG SED1521FAA Segment Driver M CL Figure 7.5. HD44103CH – SED1521FAA *1. In this connection, the duty of the SED1521FOA must be the same as that of the SED1520FOA . *2. A CMOS buffer is neede for a system having two or more slave LSIs. S-MOS SYSTEMS, INC. 48 FR 8.0 Typical Connections with LCD Panel S-MOS SYSTEMS, INC. 49 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 50 8.0 8.0 Typical Connections with LCD Panel 8.0 Typical Connections with LCD Panel [Full dot LCD panel: 1 character = 6 × 8 dots] 1 LCD 16 16 x 61 1 61 SEG SED1520F COM Figure 8.1. Duty 1/16, 10 characters × 2 lines 1 LCD 16 1 COM 16 x 141 62 61 141 SEG SEG SED1520F SED1521F Figure 8.2. Duty 1/16, 23 characters × 2 lines 1 LCD 16 32 x 202 17 1 COM 61 62 141 142 202 SEG SEG SEG SED1520F Master SED1521F * SED1520F Slave 32 * SED1521F may be omitted. If it is not used, the panel consists of 32 × 122 dots. Figure 8.3. Duty 1/32, 33 characters × 4 lines Note: Type AA (using external clock) and type 0A (containing an oscillator) cannot coexist for the same panel. S-MOS SYSTEMS, INC. 51 COM 8.0 1 LCD COM HD44103CH 8.0 Typical Connections with LCD Panel 32 1 80 32 x 320 81 160 161 240 241 320 SEG SEG SEG SEG SED1521FAA (1) SED1521FAA (2) SED1521FAA (3) SED1521FAA (4) Figure 8.4. Duty 1/32, 20 kanji characters × 2 lines (kanji character 16 × 16 dots) (5) SED1521FAA (6) SED1521FAA (7) SED1521FAA (8) SED1521FAA SEG SEG SEG SEG COM LCD 64 x 320 32 33 COM HD44103CH 1 64 1 80 81 160 161 240 241 320 SEG SEG SEG SEG SED1521FAA (1) SED1521FAA (2) SED1521FAA (3) SED1521FAA (4) Figure 8.5. Duty 1/32, 2-screen display, 20 kanji characters × 4 lines S-MOS SYSTEMS, INC. 52 9.0 Package Dimensions (Reference) S-MOS SYSTEMS, INC. 53 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 54 9.0 9.0 Package Dimensions (Reference) 9.0 Package Dimensions (Reference) 25.6 ± 0.4 20 80 51 19.6 ± 0.4 50 14 81 Index 100 31 2.7 ± 0.1 0.15± 0.05 1 30 0.65 0.30 0 – 12° 1.5 ± 2.8 Figure 9.1. Package Dimensions S-MOS SYSTEMS, INC. 55 0.3 THIS PAGE INTENTIONALLY BLANK S-MOS SYSTEMS, INC. 56