AMICC A31W65132

A31W65132 Series
Preliminary
LCD Controller-Driver
Document Title
LCD Controller-Driver
Revision History
Rev. No.
History
Issue Date
Remark
0.0
Initial issue
April 20, 2000
Preliminary
0.1
Error correction:
February 19, 2001
C3- → C3+
C1+ → C1C1- → C1+
C2- → C2+
C2+ → C2Add pad coordinates
Change power supply range:
2.0V to 5.5V → 2.4V to 5.5V
PRELIMINARY
(February, 2001, Version 0.1)
AMIC Technology, Inc.
A31W65132 Series
Preliminary
LCD Controller-Driver
Features
n
n
n
n
n
n
n
n
n
n Power supply range : 2.4V to 5.5V
6.0V to 16.5V (LCD drive)
n Internal LCD drivers :
132 segment signal drivers
65 commons signal drivers
n Power save current (<1uA)
n On chip 132 x 65 Display Data RAM
n 8 BIT 80/68-Series Parallel interface ,Serial interface
n Build-in RC oscillator or external clock input
1:7 / 1:9 Bias Ratio
64 level internal contrast control
8 level internal resistor ratio set (V5 voltage)
Build-in temperature compensation circuit
Internal bias divider circuit
On chip internal DC/DC converter / External Power supply
Dual/ Triple/ Quad booster
Internal icon common Output system for indicators
TCP package, Gold bumps
The A31W65132 series is a CMOS LCD driver, which has 132 segment, and 65 common graphic display. It has 80/68series 8 bit parallel and serial interface capability for operating with general CPU. The internal 65 x 132 display data RAM
makes the display of both graphics and characters possible. Besides the general LCD driver features, it has on chip LCD
bias divider circuit such that minimize external component required in system application.
PRELIMINARY
(February, 2001, Version 0.1)
1
AMIC Technology, Inc
A31W65132 Series
Block Diagram
1. Block Overview
COMINC1 COMINC2 COM1 to 64
SEG1 to 132
VDD
V1 to V5
C3+
C1C1+
C2+
C2VOUT
VCNT
VRS
IRS
LCD Driver
Display Data
Control
LCD
Power
Supply
Circuit
Data
Input/
Output
Page
Address
Decode
Data Latch
Start
Line
Address
Decoder
Display RAM
8580 bits
HPM
CLS
CL
FRS
FR
DOF
M/S
Oscillating
Circuit
LCD
Timing
Circuit
Start
Line
Register
& Counter
Line
Control
Column Address
Decoder
Page
Address
Register
Start
Line
Register
Column Address
Register & Counter
Status
Register
Command
Decoder
VSS
Power on
Reset
MPU interface
For 68-Series & 80-Series
D0 to D7
PRELIMINARY
(February, 2001, Version 0.1)
A0 P/S C68/80 CS2 R/W
2
E
RES CS1
AMIC Technology, Inc
A31W65132 Series
Block Diagram
2. LCD Power Supply Circuit Block Diagram
VOUT
HPM VRS VCNT IRS
V5
C3+
C1C1+
Quad Booster,
Triple Booster &
Double Booster
C2+
Voltage Regular
Bias
Resister
C2-
Adjustment
Circuit
Reference
Regular
V4
Voltage
Follower
CLK
V3
V2
V1
Reference
Voltage
Command
Register
PRELIMINARY
(February, 2001, Version 0.1)
3
AMIC Technology, Inc
A31W65132 Series
NC
COMINC2
COM64
COM63
COM62
COM61
COM60
COM59
COM58
COM57
COM56
COM55
COM54
COM53
COM52
COM51
COM50
COM49
COM48
COM47
COM46
COM45
Pad Assignment
287
NC
FRS
FR
CL
DOF
NC
VSS
CS1
CS2
VDD
RES
A0
VSS
WR,R/W
RD, E
VDD
D0
D1
D2
D3
D4
D5
D6, SCL
D7, SI
NC
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VOUT
VOUT
C3+
C3+
C1C1C1+
C1+
C2+
C2+
C2C2VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
NC
V3
V3
V4
V4
V5
V5
NC
VCNT
VCNT
VDD
VDD
VDD
M/S
CLS
VSS
C68/80
P/S
VDD
HPM
VSS
IRS
VDD
NC
1
266
265
NC
NC
COM44
COM43
COM42
COM41
COM40
COM39
COM38
COM37
COM36
COM35
COM34
COM33
SEG132
SEG131
SEG130
SEG129
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
.
83
106
105
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
..
.
(The identification marks are larger than the actual scaling)
50 50
50
50
Unit : um
50
50
50 50
(The identification marks are made of AI patterns)
SEG4
SEG3
SEG2
SEG1
COMINC1
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
NC
NC
. Pad pitch
Segment driver
Comon driver
Control pad
. Gold bump size
Drive
Input pin
. Gold bump height
65um
65um
100um
43x85um
73x85um
18um (Typ.)
NC
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
84
Chip Identification Marks
PRELIMINARY
(February, 2001, Version 0.1)
4
AMIC Technology, Inc
A31W65132 Series
Pad Coordinates
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
PRELIMINARY
Pin Name
NC
FRS
FR
CL
DOF
NC
VSS
CS1
CS2
VDD
RES
A0
VSS
W/R, R/ W
RD, E
VDD
D0
D1
D2
D3
D4
D5
D6, SCL
D7, SI
NC
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
VOUT
VOUT
C3+
C3+
C1C1C1+
C1+
C2+
C2+
C2-
X
-5152.5
-4971.2
-4706
-4445.8
-4180.6
-3999.3
-3899.3
-3785.7
-3685.7
-3572.7
-3459.7
-3359.7
-3246.7
-3133.7
-3033.7
-2920.7
-2739.1
-2473.9
-2213.7
-1948.1
-1687.9
-1422.7
-1162.5
-896.9
-715.6
-615.6
-515.6
-415.6
-315.6
-215.6
-115.6
-15.6
84.4
184.4
284.4
384.4
484.4
584.4
684.4
784.4
884.4
984.4
1084.4
1184.4
1284.4
1384.4
1484.4
1584.4
(February, 2001, Version 0.1)
Y
No.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
5
Unit: µm (The origin is the center of the chip)
Pin Name
X
Y
C2VSS
VSS
VRS
VRS
VDD
VDD
V1
V1
V2
V2
NC
V3
V3
V4
V4
V5
V5
NC
VCNT
VCNT
VDD
VDD
VDD
M/S
CLS
VSS
C68/80
P/S
VDD
HPM
VSS
IRS
VDD
NC
NC
COM32
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
1684.4
1784.4
1884.4
1984.4
2084.4
2184.4
2284.4
2384.4
2484.4
2584.4
2684.4
2784.4
2884.4
2984.4
3084.4
3184.4
3284.4
3384.4
3484.4
3584.4
3684.4
3784.4
3884.4
3984.4
4097.4
4197.4
4310.4
4423.4
4523.4
4636.4
4736.4
4836.4
4936.4
5036.4
5136.4
5146.5
5146.5
5146.5
5146.5
5146.5
5146.5
5146.5
5146.5
5146.5
5146.5
5146.5
5146.5
5146.5
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-910
-726.3
-661.3
-596.3
-531.3
-466.3
401.3
-336.3
-271.3
-206.3
-141.3
-76.3
-11.3
53.7
AMIC Technology, Inc
A31W65132 Series
Pad Coordinates (continued)
No.
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
PRELIMINARY
Pin Name
COM20
COM19
COM18
COM17
COM16
COM15
COM14
COM13
COM12
NC
NC
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COMINC1
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
X
Y
5146.5
5146.5
5146.5
5146.5
5146.5
5146.5
5146.5
5146.5
5146.5
5167.5
5102.5
5037.5
4972.5
4907.5
4842.5
4777.5
4712.5
4647.5
4582.5
4517.5
4452.5
4387.5
4322.5
4257.5
4192.5
4127.5
4062.5
3997.5
3932.5
3867.5
3802.5
3737.5
3672.5
3607.5
3542.5
3477.5
3412.5
3347.5
3282.5
3217.5
3152.5
3087.5
3022.5
2957.5
2892.5
2827.5
2762.5
2697.5
(February, 2001, Version 0.1)
No.
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
118.7
183.7
248.7
313.7
378.7
443.7
508.7
573.7
638.7
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
6
Unit: µm (The origin is the center of the chip)
Pin Name
X
Y
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
SEG57
SEG58
SEG59
SEG60
SEG61
SEG62
SEG63
SEG64
SEG65
SEG66
SEG67
SEG68
SEG69
SEG70
SEG71
SEG72
SEG73
2632.5
2567.5
2502.5
2437.5
2372.5
2307.5
2242.5
2177.5
2112.5
2047.5
1982.5
1917.5
1852.5
1787.5
1722.5
1657.5
1592.5
1527.5
1462.5
1397.5
1332.5
1267.5
1202.5
1137.5
1072.5
1007.5
942.5
877.5
812.5
747.5
682.5
617.5
552.5
487.5
422.5
357.5
292.5
227.5
162.5
97.5
32.5
-32.5
-97.5
-162.5
-227.5
-292.5
-357.5
-422.5
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
AMIC Technology, Inc
A31W65132 Series
Pad Coordinates (continued)
No.
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
PRELIMINARY
Pin Name
SEG74
SEG75
SEG76
SEG77
SEG78
SEG79
SEG80
SEG81
SEG82
SEG83
SEG84
SEG85
SEG86
SEG87
SEG88
SEG89
SEG90
SEG91
SEG92
SEG93
SEG94
SEG95
SEG96
SEG97
SEG98
SEG99
SEG100
SEG101
SEG102
SEG103
SEG104
SEG105
SEG106
SEG107
SEG108
SEG109
SEG110
SEG111
SEG112
SEG113
SEG114
SEG115
SEG116
SEG117
SEG118
SEG119
SEG120
SEG121
X
-487.5
-552.5
-617.5
-682.5
-747.5
-812.5
-877.5
-942.5
-1007.5
-1072.5
-1137.5
-1202.5
-1267.5
-1332.5
-1397.5
-1462.5
-1527.5
-1592.5
-1657.5
-1722.5
-1787.5
-1852.5
-1917.5
-1982.5
-2047.5
-2112.5
-2177.5
-2242.5
-2307.5
-2372.5
-2437.5
-2502.5
-2567.5
-2632.5
-2697.5
-2762.5
-2827.5
-2892.5
-2957.5
-3022.5
-3087.5
-3152.5
-3217.5
-3282.5
-3347.5
-3412.5
-3477.5
-3542.5
(February, 2001, Version 0.1)
Y
No.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
7
Unit: µm (The origin is the center of the chip)
Pin Name
X
Y
SEG122
SEG123
SEG124
SEG125
SEG126
SEG127
SEG128
SEG129
SEG130
SEG131
SEG132
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
NC
NC
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COMINC2
NC
-3607.5
-3672.5
-3737.5
-3802.5
-3867.5
-3932.5
-3997.5
-4062.5
-4127.5
-4192.5
-4257.5
-4322.5
-4387.5
-4452.5
-4517.5
-4582.5
-4647.5
-4712.5
-4777.5
-4842.5
-4907.5
-4972.5
-5037.5
-5102.5
-5167.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
-5146.5
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
910
638.7
573.7
508.7
443.7
378.7
313.7
248.7
183.7
118.7
53.7
-11.3
-76.3
-141.3
-206.3
-271.3
-336.3
-401.3
-466.3
-531.3
-596.3
-661.3
-726.3
AMIC Technology, Inc
A31W65132 Series
Input/Output Pin Function
Pin No.
Symbol
Type
Description
7, 13,
30-36,
50-51,
75, 80
VSS
Supply
GROUND
10, 16,
26-29,
54-55,
70-72,
78, 82
VDD
Supply
Power supply pin
52-53
VRS
Supply
External VREG voltage supply for LCD voltage regulator.
74
CLS
Input
CLS = High : Internal oscillator is enabled
CLS = Low : Internal oscillator is disabled
4
CL
In/out
Display clock input
M/S
CLS
CL
H
H
Output
H
L
Input
L
H
Input
L
L
Input
The CL pins must be connected in Master/Slave mode.
73
M/S
Input
M/S = High : Master mode
M/S = Low : Slave mode
M/S
CLS
Power
Oscillator
Supply Circuit
CL
FR
DOF
FRS
Circuit
H
H
Enable
Enable
Output Output Output
H
L
Enable
Disable
Input
L
H
Disable
Disable
Input
Input
Input
Output
L
L
Disable
Disable
Input
Input
Input
Output
Output Output
Output
Output
The signals FR, DOF, CL of slave chips must be supplied from the master chip.
3
FR
In/out
LC alternating current signal pin
M/S = High : Output
M/S = Low : Input
The FR pins must be connected in Master/Slave mode.
5
DOF
In/out
LCD blanking control pin
M/S = High : Output
M/S = Low : Input
The DOF pins must be connected in Master/Slave mode
2
PRELIMINARY
FRS
Output
The FRS output for the static icon drive and is used in conjunction with the FR
pin, one of the static icon electrodes is connected to the FR pin, and the other is
connected to FRS pin.
(February, 2001, Version 0.1)
8
AMIC Technology, Inc
A31W65132 Series
Input/Output Pin Function (continued)
Pin No.
Symbol
Type
81
IRS
Input
Description
The IRS is used in V5 voltage adjustment
IRS = High : used the internal resistors
IRS = Low : used the external resistors
This pin is used in master mode. When in slave mode, it can fixed to either High or
Low level
79
HPM
Input
HPM = High : Normal mode power supply
HPM = Low : High power mode power supply
This pin is used in master mode. When in slave mode, it can fixed to either High or
Low level
8, 9
CS1
Input
Chip select input. When CS1 = Low, CS2 = High, enable the chip select
Reset pin, Low enable
CS2
11
RES
Input
12
A0
Input
A0=Low: Command input.
A0=High: Display data input and outputs
14
R/ W
Input
( WR )
15
E
80-Series : Write enable, Active Low
Input
( RD)
77
P/S
68-Series R/ W =High: Read, R/ W =Low : Write
68-Series : Enable clock signal input, Active High
80-Series : Read enable, Active Low
Input
Parallel/serial interface select input
High : 8-bit parallel interface
Low : Serial interface , display data RAM reading is not supported
76
C68/80
Input
Microprocessor interface select input
High : 68-Series interface is selected
Low : 80-Series interface is selected
17-24
D0-7
Input/
(SI, SCL)
Output
8bit bi-directional data bus to be connected to microprocessor’s data bus
P/S = High : 8-bit configuration data bus connection
P/S = Low : Serial interface connection
D6 Serial data input SCL
D7 Serial clock input SI
120-251
SEG1SEG132
Output
Provide the LCD segment driving signal
85-105,
108-118,
252-263,
266-285
COM1COM64
Output
Provide the LCD common driving signal
119,
286
COMINC1
COMINC2
Output
Provide the icon common driving signal, the same signal is output in master/slave
mode
38-39
VOUT
Output
Boosting voltage output
40-41
C3+
Input
PRELIMINARY
3rd- step boosting capacitor negative connection
(February, 2001, Version 0.1)
9
AMIC Technology, Inc
A31W65132 Series
Input/Output Pin Function (continued)
Pin No.
Symbol
Type
Description
46-47
C2+
Input
2nd-step boosting capacitor negative connection
48-49
C2-
Input
2nd-step boosting capacitor positive connection
44-45
C1+
Input
1 st-step boosting capacitor negative connection
42-43
C1-
Input
1 st-step boosting capacitor positive connection
68-69
VCNT
Input
External LCD power regulator voltage control through a resistive voltage divider.
IRS = Low: These can be used, because the internal resistors are disabled.
IRS = High: These can not be used.
56-57
V1
Input
58-59
V2
Input
61-62
V3
Input
63-64
V4
Input
65-66
V5
Input
1, 6, 25,
37, 60, 67,
83-84 ,
106-107,
264-265,
287
NC
Open
PRELIMINARY
LCD driver bias voltage. They can be supplied externally or generated by the
internal bias divider.
1: 7 bias
1: 9 bias
V1
1/7 x V5
1/9 x V5
V2
2/7 x V5
2/9 x V5
V3
5/7 x V5
7/9 x V5
V4
6/7 x V5
8/9 x V5
• Inputs LCD drive bias voltage when using an external LCD power supply circuit.
V5 ≥ V4, V3, V2, V1 > VSS
No Connection
(February, 2001, Version 0.1)
10
AMIC Technology, Inc
A31W65132 Series
Commands Table
Command
A0
Set Display ON/OFF
0
Set Display Start Line
0
Page Address Set
0
Upper 4 bits of Column 0
Address Set
Lower 4 bits of the
0
Column Address Set
Status Read
0
Bit pattern
Comment
E R/ W D7 D6 D5 D4 D3 D2 D1 D0
1
0
1 0 1 0 1 1 1 0 D0:0 Display OFF: Display goes out, regardless
of the content of the display
data RAM
1 D0:1 Display ON: Normal Display
1
0
0 1 Display start line address Sets the line address of the display data
RAM output to COM1
(0-63)
1
0
1 0 1 1 Page Address Sets the page address of the display data
RAM. Page 8 is assigned to the icon display
(0-8)
Upper
4
bits
of
1
0
0 0 0 1
Sets upper 4 bits of the display data RAM
Column Address
Column Address
1
0
0 0 0 0 Lower 4 bits of the Lower 4 bits of display data RAM column
Column Address
Address
0
1
Status
Status Read
Write Data in
1
0
Writes data of D0 to D7 in the display data RAM
Display Data RAM
Read Data from
Reads data from D0 to D7 from the display data
0
1
RAM
Display Data RAM
1
0
1 0 1 0 0 0 0 0 Reverses upper or lower display data RAM
1 column address
D0:0 Normal: Column addresses 00 to 83H
correspond to segment outputs 1
to 132
D0:1 Reverse: Column addresses 00 to 83H
correspond to segment outputs
132 to 1
1
0
1 0 1 0 0 1 1 0 D0:0 Normal : “1” makes the display be lit
1 D0:1 Reverse : “0” makes the display be lit
The icon display is not reversed
1
0
1 0 1 0 0 1 0 0 D0:0 Normal Display
1 D0:1 Display All-Lit ON
1
0
1 1 0 0 0 *
* * D3:0 In a normal order COM1 to COM64
D3:1 In a reverse order COM64 to COM1
1
Display Data Write
1
Display Data Read
1
ADC Select
0
Display Normal/
Reverse
0
Display All-Lit ON/OFF
0
Common Output
Sequence Select
0
Read Modify Write
0
1
0
1
1
1
0
0
End
Icon Only Display
0
0
1
1
0
0
1
1
1
1
1
0
0
1
1
1
PRELIMINARY
(February, 2001, Version 0.1)
Increments display data RAM column
address only during writing
1 1 0 Read Modify Write Release.
0 Boosting D2:0 Normal Display (default)
1 Control D2:1 Icon Only Display
Data
Boosting control data:
D1 D0: 00 FOSC
01 fOSC/2
10 fOSC/4 (default)
11 fOSC/8
0
11
0
0
AMIC Technology, Inc
A31W65132 Series
Commands Table (continued)
Command
A0
0
E
1
Bias Selection
0
1
Power Supply Circuit
Operation Control
0
1
LCD Voltage Command
0
1
V5 Voltage Regulator
Internal Resistor Ratio
0
1
Static Icon Display
Command Set
0
1
0
1
0
1
Reset
LCD Voltage Command
Fine Adjustment Data
Static Icon Display Register
Set
(Double Byte Command)
Reference Voltage
Temperature
Coefficient Select
Power Save
NOP
PRELIMINARY
Bit pattern
Comment
R/ W D7 D6 D5 D4 D3 D2 D1 D0
0
1 1 1 0 0 0 1 0 It does not affect the contents of the display data
RAM.
After resetting, display starts according to the
reset value:
1.Resets the display start line register to the
1st line.
2.Resets the column address counter to
address 0.
3.Resets the page address counter to page 0.
4.Turns OFF the Read Modify Write.
5.Static icon off, static icon display register
off. D1, D0 = 0, 0
6.Common output sequence in normal order
7.V5 voltage regulator internal resistor ratio
set mode clear. D2~D0 = 1, 0, 0
8.LCD voltage command fine adjustment
data D5~D0 = 1, 0, 0, 0, 0, 0
0
1 0 1 0 0 0 1 0 D0 = 0 : 1/9 Bias Selection (default)
1 D0 = 1 : 1/7 Bias Selection
Control LCD power supply circuit operation mode select
0
0 0 1 0 1
mode
0
1 0 0 0 0 0 0 1 The LCD Voltage Command Fine Adjustment
Data must set after the LCD Voltage Command
set
* * 0 0 0 0 0 0 Minimum value
.
.
.
.
.
.
1 1 1 1 1 1 Maximum value (Total 64 level)
0
0 0 1 0 0 0 0 0 Small
.
.
.
1 1 1 Large
Voltage regulator internal resistor (Ra/Rb) ratio,
total 8 level
0
1 0 1 0 1 1 0 0 Static icon display command set :
1 D0 = 0 Static icon display OFF
D0 = 1 Static icon display ON
(The static icon display register set command
must set after the static icon display ON
command set)
* *
* * *
*
Mode Static icon display register set :
D1 D0 = 0 0 :OFF
0 1 : Blinking , one second intervals
1 0 : Blinking , 0.5 second intervals
1 1 : ON
0
1 1 1 0 0 1 0 0 D0 : 0 0.05%/°C (default)
1 1 D0 : 1 0.2%/°C
D1 : 0 Internal VREG (default)
D1 : 1 External VREG
Set Display OFF then set Display all-lit ON
command
0
1 1 1 0 0 0 1
1 Non operation command
(February, 2001, Version 0.1)
12
AMIC Technology, Inc
A31W65132 Series
Operation of LCD Display Driver
1. Powering ON setting sequence
Recommended Command Setting Sequence:
(1) Set Display OFF : In order to prevent unnecessary characters from being displayed during powering ON of
the power .
When the master is turned on, the oscillator circuit is operable immediately. After the
powering on, it will be in All-OFF state.
(2) Set Display All-Lit OFF: Normal display operation.
(3) Set LCD Power Supply operation control
(4) Set Bias Select: 1. Bias selection setting
2. V5 voltage regulator internal resistor ratio setting
3. LCD voltage command and LCD voltage command fine adjustment data setting
(5) Set Reference Voltage Temperature Compensation Coefficient
(6) End Command Input
(7) ADC Select setting
(8) Set Display Normal/Reverse:
D0 : 0 Normal Display data "1" makes the display be lit.
D0 :
1 Reverse Display data "0" makes the display be lit.
(9) Set Display Start Line address: Changing the display start line allows for page change on the display screen
as well as vertical smooth scroll.
(10) Set Common Output Sequence
(11) Icon Only Display
(12) Static Icon Display select
(13) Display Data Write: After writing the display data, the column address is automatically incremented. To write
the display data in succession after setting the 1st column address to be written by the COLUMN ADDRESS
SETTING command, the column address is not needed to be set each time. The icon display data is valid for
only D0.
Write “L” or data to be displayed in all display data RAM before turning the display ON.
(14) Display ON
2. Set Powering OFF, Power Save Mode
Set Powering OFF sequence:
(1) Set Display OFF
(2) Set Display All-Lit ON
(3) Set LCD Power Supply Circuit OFF
Power Save Mode:
The power save mode has two modes, one is sleep mode and the other is standby mode.
The MPU is still able to access the display data RAM when in power save mode.
Combination of Commands
Display ON
Display All-Lit OFF
State
Normal display operation
Display ON
Display All-Lit ON
All-lit display
Display OFF
Display All-Lit OFF
AII-OFF
Static Icon Display ON
Display OFF
Display All-Lit ON
Standby mode (Power save)
Static Icon Display OFF
Display OFF
Display All-Lit ON
Sleep mode (Power save)
PRELIMINARY
(February, 2001, Version 0.1)
13
AMIC Technology, Inc
A31W65132 Series
When in sleep mode, the command sleeps the system:
• Internal oscillating circuit and LCD power supply circuit are stopped.
• All LC drive circuit are stopped, the Segment and Common outputs are fixed at VSS level.
When in standby mode:
• Internal oscillating circuit continues to operate and LCD power supply circuits are stopped.
• The duty drive system LC circuits are stopped, the Segment and Common outputs are fixed at VSS level.
• The static icon drive system continues to operate.
When a reset command is set in the standby mode, the LCD system will enter the sleep mode.
When using an external power supply circuit, stop the external power supply circuit and float the LCD power supply
when the power save mode is started. When using an external bias resistor in order to reduce the current of power
save mode, attach a switching transistor which cuts the current flowing through the bias resistor. The LCD blinking
control pin DOF will output Low signal when the power save mode is start. We can use the DOF to stop the
external power supply.
3. MPU Interface Select
The parallel 68-series, 80-series interface or serial interface can be selected by P/S, C68/80 pin setup:
P/S Pin
H
C68/80 Pin
L
H
MPU Interface
80-series Interface selected
68-series Interface selected
L
don't care
Serial Interface selected
3.1 MPU Parallel 68-Series and 80-Series Interface
The parallel interface consists of 8 bi-directional data pins (D0-D7), R/ W ( WR ), A0, E( RD ), CS In order to match
the operating frequency of display RAM with that of the microprocessor, some pipeline processing is internally
performed which requires the insertion of a dummy read before the first actual display data read.
A31W65132 Pin Name
A0
E
R/ W
CS1
CS2
D0 - D7
68-Series MPU Signal
A0
E
R/ W
CS1
CS2
D0 - D7
80-Series MPU Signal
A0
RD
WR
CS1
CS2
D0 - D7
3.2 MPU Serial Interface
The serial interface consists of serial clock input SCL, serial data input SI and chip select CS1, CS2, A0. When the
serial interface is selected by setting P/S to “L”, the instruction code is the same as for the parallel interface .By
setting CS1 to “L”, CS2 to “H”. the serial interface circuit enters an operating state. And by setting CS1 to “H’, or
setting CS2 to “L”, it will reset the serial interface circuit and initialized the counter.
Data is input in the order of D7, D6, D5,....D0. The displayed data and commands are written at the rising edge of
the SCL. The A0 is detected every 8 rising edge of SCLK serial clock after the chip select pins is enabled.
D7 (SI)
D6 (SCL)
D5 to D0
A0
: Serial Data Input
: Serial Clock Input
: Open
: Select the command data or display data
A0
L
H
PRELIMINARY
Operation
Command write
Display data write
(February, 2001, Version 0.1)
14
AMIC Technology, Inc
A31W65132 Series
4. Command Execution
When the input at D0-D7 is interpreted as a command and it will be decoded and written to the corresponding command
register. The user can input the commands continuously without confirming the busy flag of status command register
because the command is completely executed within the cycle time (tCYC) according to the timing characteristics of the
command input. But that re-inputting the command within the executed cycle time is inhibited. The busy flag is outputted
to D7 pin with the read instruction, “H” indicates the chip is in busy state.
5. Data Bus Select
When CS1 is held at “H” level or CS2 is held at “L” level, the D0-D7 is in high impedance state.
68/80-Series
shared
A0
1
1
0
0
68-Series
R/ W
1
0
1
0
80-Series
E
0
1
0
1
R/ W
1
0
1
0
Description
Reads from Display Data RAM
Writes to Display Data RAM
Reads Status
Command Write to internal register
6. Display Data RAM
The Display Data RAM is made of dual port RAM. The size of the RAM is 64 x 132 + 132 = 8580 bits.
Write “L” or data to be displayed in all display data RAM before turning the display ON.
7. Accessing the Display Data RAM From MPU
In order to match the operating frequency of Display Data RAM with that of the MPU, a dummy read is required before the
first actual display data read. When the MPU reads the Display Data RAM, the first dummy read cycle stores the first read
data in the bus holder, and then at the next read cycle the MPU read the first read data from the bus holder.
It does not need a dummy cycle when MPU writes data to the Display Data RAM. When the MPU write data to Display
Data RAM, once the data is stored in the bus holder, then it is written to Display Data RAM before the next data write
cycle.
8. Set Column Address (higher, lower nibble)
This command specifies the column address (higher and lower nibble) of the Display Data RAM. The column address will
be incremented automatically by each data access after it is pre-set by the MPU. The incrementation of column addresses
stops with 83H.
9. Set Page Address (0-8)
This command positions the page address to 0 of 8 possible positions in Display Data RAM. Page 0-7 are the graphic
display area, and the page 8 are the icon display area. The icon display data is valid for only D0.
10. Set display start line (0-63)
The command is used to change the display page or smooth scroll.
With the display start line value equals to 0, D0 of page 0 is mapped to COM1. The display start line values of 0 to 63
are assigned to page 0 to 7.
PRELIMINARY
(February, 2001, Version 0.1)
15
AMIC Technology, Inc
A31W65132 Series
11. Status Read
This command shows the status of A31W65132
BUSY
: D7
ADC
: D6
ON/OFF : D5
RESET : D4
PSAVE
: D3
ICON
: D2
DREV
: D1
ALON
: D0
=0 :
1:
=0 :
1:
=0 :
1:
=0 :
1:
=0 :
1:
=0 :
1:
=0 :
1:
=0 :
1:
The A31W65132 is not busy
The A31W65132 is in internal operation or reset state.
ADC Reverse : Column addresses 00 to 7FH correspond to segment outputs 132 to 1.
ADC Normal : Column addresses 00 to 7FH correspond to segment outputs 1 to 132.
Display ON
Display OFF
In normal operation state
Internal reset operation state
In normal operation state
In Power Save state
In normal operation state
In icon only display state
Display Normal
Display Reverse
Normal display
Display All-Lit ON
12. Common Output sequence select
Output sequence Common driving signal output in normal mode Common driving signal Output in reverse mode
1
COM1
COM64
2
COM2
COM63
3
COM3
COM62
.
.
.
.
.
.
16
COM16
COM49
17
COM17
COM48
.
.
.
.
.
.
63
COM63
COM2
64
COM64
COM1
13. Icon Only Display
D2 = 0
D2 = 1
Normal Display
Icon Only Display
D1
0
0
1
1
D0
0
1
0
1
Boosting frequency
fOSC
fOSC/2
fOSC/4
fOSC/8
When D2=High, regardless of the content of the display data RAM, display icon only and LCD panel compelled to be off.
When reducing the boosting frequency, the gray scale of icon display differs depending on the panel size or the value of
the boosting capacitor.
14. Read Modify Write , END
Read Modify Write
This command puts the chip in read modify write mode. In this mode the column address is saved before entering the
mode, and is incremented by display data write but not by display data read. During the Read Modify Write mode, all
commands are usable except the Column address set command.
End
This command relieves the A31W65132 from read modify write mode. The column address that is saved before entering
read modify write mode will be restored.
PRELIMINARY
(February, 2001, Version 0.1)
16
AMIC Technology, Inc
A31W65132 Series
15. RC Oscillator Circuit
The built-in RC oscillator generates the clock for the boosting frequency, and is also used in the display timing. When
using the external clock (CLS = Low or M/S = Low), the external clock is input to CL pin.
16. Reference Voltage Temperature Compensation Coefficient Select
This command is to set one out of 2 different temperature coefficients in order to match various liquid crystal
temperature grades.
∆VREF =
IVREF(T2)I − IVREF(T1)I
T 2 − T1
T2 > T1
17. The Reset Circuit
After reset by the RES pin (Low enable), the A31W65132 return to the default status as follows:
1. Display off
2. Display normal
3. ADC select normal
4. Power supply circuit operation control D2, D1, D0 = 0, 0, 0
5. Serial interface internal counter and register clear
6. LCD power supply bias rate selection = 1/9
7. All indicator lamps-on OFF (D0 = Low)
8. Power saving clear
9. V5 voltage regulator internal resistors Ra, Rb separation
10. Turn off the Read Modify Write
11. Resets the display start line register to 1st line
12. Resets the column address counter to address 0
13. Resets the page address counter to page0
14. The SEG and COM output conditions: SEG = V2/V3, COM = V1/V4. While RES = Low, the CL, FR, FRS and DOF
are fixed to High, and the oscillator and display timing generator stop. The VSS level is output from SEG and COM
outputs.
15. Static icon off, and static icon display register = off (D1, D0 = 0, 0)
16. Common output sequence in normal order
17. V5 voltage regulator internal resistor ratio set mode clear D2~D0 = 1, 0, 0
18. LCD voltage command fine adjustment data D5~D0 = 1, 0, 0, 0, 0, 0
19. Reference voltage temperature coefficient select 0.05%/°C
20. Icon Only Display command: Normal display, Boosting control D1, D0 = 1, 0
18. LCD Power Supply Circuit
The LCD power supply circuit generates the LCD voltage needed for display output, which is controlled by power supply
operation control command. It consists of:
1. Double / triple / quad DC-DC voltage converter
2. Internal resistors and voltage command fine adjustment circuit (64 level) for the V5 voltage regulator
3. LCD bias resistor and voltage follower
D2
D1
D0
Double/Triple/
Quad Circuit
Voltage Regulator
Circuit
LCD Bias Resistor/
Voltage Follower Circuit
H
L
L
L
H
L
H
L
H
L
H
H
ON
OFF
OFF
OFF
ON
OFF
ON
OFF
ON
OFF
ON
ON
PRELIMINARY
(February, 2001, Version 0.1)
17
AMIC Technology, Inc
A31W65132 Series
18.1 Double / Tripler / Quad
It is the 2X, 3X , 4X DC-DC voltage converter. Please refer to application notes.
VSS
VSS
C1
VSS
C1
+
+
C1
VOUT
+
C3+
+
C1
VOUT
VOUT
+
C3+
C1C1
+
C1
C3+
C1-
C1-
C1
C1
C1+
+
C1+
C2+
+
C1
C2+
C2-
C2+
C2-
4 x step-up voltage circuit
C1+
+
C2-
OPEN
3 x step-up voltage circuit
2 x step-up voltage circuit
Quad VOUT = 12V
Triple VOUT = 9V
Double VOUT = 6V
VDD=3V
VSS
Example of Booster Output
18.2 LCD Voltage Adjustment
There are two methods of adjusting the LCD voltage as follows:
18.2.1 Voltage Regulator
Voltage regulator output V5 is adjusted by internal Ra/Rb resistors ratio or externally attached Ra and Rb.
VREF(V) = (1-α /162) x VREG
V5=
Ra + Rb
Ra
X VREF (V)
+
VREF
V5
Ra
VCNT
Rb
VSS
PRELIMINARY
(February, 2001, Version 0.1)
18
AMIC Technology, Inc
A31W65132 Series
Temperature Coefficient
VREG
0.05%/°C
0.2%/°C
External VREG input
2.1Voltage
4.9 Voltage
VRS
Ta = 25°°C
V5 Voltage regulator Internal Resistor Ratio Register Value and (Ra+Rb)/Ra Ratio (for reference)
Internal Resistance Ratio Register
D2
0
0
0
0
1
1
1
1
D1
0
0
1
1
0
0
1
1
D0
0
1
0
1
0
1
0
1
Internal (Ra+Rb)/Ra Ratio
0.05
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.4
0.2
1.3
1.5
1.8
2.0
2.3
2.5
2.8
3.0
VREG External Input
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
18.2.2 LCD Voltage Command Fine Adjustment control
Software control of 64 voltage levels (α) adjustment of V5 voltage by set 6 bits of the data bus. It can adjust the
LCD contrast.
LCD voltage command is a two-byte command used as a pair with the LCD voltage command and LCD
voltage command fine adjustment control, and both command must be issued on after the other.
18.3 Static Icon Display
This controls the static drive system display. This is used when one of the static indicator LCD electrodes is
connected to the FR terminal, and the other is connected to the FRS terminal.
The Static Icon Display command set ON is a two-byte command used as a pair with the Static Icon Display
command set and Static Icon Display register set.
The Static Icon Display command set OFF is a single byte command.
18.4 LCD Bias voltage
When use built-in LCD bias resistor, Software can control the 1/9, 1/7 bias ratio to match the characteristic of LCD
panel.
18.5 Voltage Follower
The voltage follower buffers the LCD bias voltage created by the built-in bias resistor, and supplies it to the LCD
drive circuit.
18.6 High power mode
When the LCD with large loads, the high power mode power supply (set HPM = Low) can improve the quality of the
LCD display.
PRELIMINARY
(February, 2001, Version 0.1)
19
AMIC Technology, Inc
A31W65132 Series
Interface
1. Parallel Interface
1.1 Display Data Write ( the 80-Series interface)
R/W
MP
Data
n
Bus Holder
Internal
Timing
n+2
n+1
n
n+3
n+2
n+1
n+3
R/W
Internal Busy Flag
1.2 Display Data Read (the 80-Series interface)
R/W
MP
E
Data
N
n
X
Address set
address N
Dummy
read
n+1
Data read
address N
Data read
address N+1
N+1
N+2
R/W
E
Internal
Timing
N
Column address
Bus Holder
X
n
n+1
n+2
Internal Busy Flag
PRELIMINARY
(February, 2001, Version 0.1)
20
AMIC Technology, Inc
A31W65132 Series
2
Serial Interface
Serial Interface Display Data Write Timing
CS1
CS2
SI (D7)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCL (D6)
A0
Notes:
1. The user can not reading from A31W65132 when in serial interface mode.
2. A0=High, the data is display data, A0=Low, the data is command data.
The A0 signal is sampled every 8th rising edge of SCL clock, when the chip becomes active in serial interface mode.
3. The counter and the shift register are reset to the default value when the chip is not active.
PRELIMINARY
(February, 2001, Version 0.1)
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AMIC Technology, Inc
A31W65132 Series
Display Data RAM vs Address
Line
Address
Page
Address
0, 0, 0, 0
0, 0, 0, 1
0, 0, 1, 0
0, 0, 1, 1
0, 1, 0, 0
0, 1, 0, 1
0, 1, 1, 0
0, 1, 1, 1
1, 0, 0, 0
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
Page0
Page1
Page2
Page3
Page4
Page5
Page6
Page7
Page8
00 01 02 03 04 05 06 07..............
3F 40 ...... 82 83
ADC
D0=
"0"
83 82 81 80 7F 7E 7D 7C..............
.... .... ...... 01 00
ADC
D0=
"1"
1 2 3 4 5 6 7 8...............
.... .... ...... 131 132
Column
Address
SEG Pin
PRELIMINARY
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0F H
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1F H
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2F H
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3F H
40H
(February, 2001, Version 0.1)
22
An example of common output
executing display start from
the line address 30 H.
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
Display
Start
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COMICN
AMIC Technology, Inc
A31W65132 Series
LCD Drive Output Waveform (Waveform B)
The following is an example of how the common and segment drivers may be connected to a LCD panel.
64 65 1
2
3
4
5
61 62 63 64 65 1
2
3
4
5
61 62 63 64 65 1
2
CL
VDD
VSS
FR
COM1
V5
V4
V3
V2
V1
VSS
COM2
V5
V4
V3
V2
V1
VSS
SEG 1
V5
V4
V3
V2
V1
VSS
SEG 2
V5
V4
V3
V2
V1
VSS
COM 1
- SEG 1
V5
V4
V3
V2
V1
VSS
-V1
-V2
-V3
-V4
-V5
COM 1
- SEG 2
V5
V4
V3
V2
V1
VSS
-V1
-V2
-V3
-V4
-V5
PRELIMINARY
(February, 2001, Version 0.1)
23
AMIC Technology, Inc
A31W65132 Series
Examples of External Bias Resistor Connection vs LCD Drive Waveform
1/7 or 1/9 Bias
SEG Waveform
M
COM Waveform
M
M
V5
M
Ra2 = γ Ra 1
Ra1
0≤γ
V4
Ra1
V3
Ra2
Bias
Ra1
V2
=
Ra1
V1
Ra1
=
VSS
PRELIMINARY
(February, 2001, Version 0.1)
24
Ra1+ Ra1+ Ra2 +Ra1 +Ra1
1
4+ γ
AMIC Technology, Inc
A31W65132 Series
Absolute Maximum Ratings
VSS = 0.0V
Parameter
Symbol
Ratings
Unit
VDD
-0.4 to +7.0
V
LCD drive voltage 1
V5, VOUT
-0.4 to +18
V
LCD drive voltage 2
V1, V2, V3, V4
-0.4 to V5
V
VIN
-0.4 to VDD+0.4
V
Output voltage
VOUT
-0.4 to VDD+0.4
V
Operating temperature range
Topr
-40 to +85
°C
-55 to +125
°C
Supply voltage
Input voltage
Note 1
Note 2
Note 3
Storage temperature
Chip
range
TAB
Tstg
-55 to +100
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and the functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
When connecting a bias resistor externally, set the LCD power supply voltage so that the state is changed to V5 ≥VDD.
PRELIMINARY
(February, 2001, Version 0.1)
25
AMIC Technology, Inc
A31W65132 Series
DC Characteristics
Unless otherwise specified, VSS = 0 V, VDD = 3.0 V ± 10%, Ta = -40 to 85°C
Item
Symbol
Operating RecomVoltage (1) mended
Voltage
Possible
Operating
Voltage
Operating Possible
Voltage (2) Operating
Voltage
Possible
Operating
Voltage
Possible
Operating
Voltage
High-level Input
Voltage
Low-level Input
Voltage
High-level Output
Voltage
Low-level Output
Voltage
Input leakage
Current
Output leakage
Current
Liquid Crystal Driver
ON Resistance
VDD
Internal Power
Static Consumption
Current
Output Leakage
Current
Input Terminal
Capacitance
Oscillator Internal
Frequency Oscillator
External
Input
Supply Step-up
Output Voltage
Circuit
Voltage
Regulator Circuit
Operating
Voltage
Voltage Follower
Circuit Operating
Voltage
Base Voltage
PRELIMINARY
Rating
Condition
Units
Applicable
Pin
5.5
V
VDD*1
-
-
V
VDD*1
Min.
Typ.
Max.
2.4
-
-
V5
(Relative to VSS)
4.5
-
16
V
V5
V1, V2
(Relative to VSS)
0
-
0.4 × V5
V
V1, V2
V3, V4
(Relative to VSS)
0.6 × V5
-
V5
V
V3, V4
VIHC
0.8 × VDD
-
VDD
V
*3
VILC
VSS
-
0.2 × VDD
V
*3
VOHC
IOH = -0.5 mA
0.8 × VDD
-
VDD
V
*4
VOLC
IOL = 0.5 mA
VSS
-
0.2 × VDD
V
*4
VIN = VDD or VSS
-1.0
-
1.0
µA
*5
-3.0
-
3.0
µA
*5
ILI
ILO
RON
V5 = 14.0 V
Ta = 25°C
(Relative To VSS) V5 = 8.0 V
-
2.0
3.2
3.5
5.4
KΩ
KΩ
SEGn
COMn*7
ISSQ
V5 = 18.0 V
-
0.01
5
µA
VSS
I5Q
(Relative To VSS)
-
0.01
15
µA
V5
CIN
Ta = 25°C f = 1 MHz
-
5.0
8.0
pF
fOSC
Ta = 25°C
18
22
26
KHz
*8
18
22
26
KHz
CL
fCL
VOUT
(Absolute value referenced to
VSS)
-
-
16.5
V
VOUT
VOUT
(Absolute value referenced to
VSS)
6
-
16.5
V
VOUT
V5
(Absolute value referenced to
VSS)
4.5
-
16
V
V5*9
2.04
4.65
2.10
4.9
2.16
5.15
V
V
*10
*10
VREG0
VREG1
Ta = 25°C
(Relative to VSS)
(February, 2001, Version 0.1)
0.05%/°C
0.2%/°C
26
AMIC Technology, Inc
A31W65132 Series
DC Characteristics (continued)
. Dynamic Consumption Current (1), During Display, with the Internal Power Supply OFF
Current consumed by the total ICs when an external power supply is used
. Dynamic Consumption Current (2), During Display, with the Internal Power Supply ON
Ta = 25°C
Item
Symbol
IDD (1)
Rating
Condition
Min.
Typ.
Max.
-
18
16
23
21
67
30
27
38
35
112
114
81
138
81
127
96
153
0.01
190
135
230
135
212
160
255
5
4
8
VDD=5.0 V, V5=11.0 V
VDD=3.0 V, V5=11.0 V
VDD=5.0 V, V5=11.0 V
VDD=3.0 V, V5=11.0 V
VDD=5.0V, Triple step-up voltage. Normal Mode
V5 =11.0 V
High-Power Mode
VDD=3.0V, Quad step-up voltage. Normal Mode
V5 =11.0 V
High-Power Mode
VDD=5.0V, Triple step-up voltage. Normal Mode
V5 =11.0 V
High-Power Mode
VDD=3.0V, Quad step-up voltage. Normal Mode
V5 =11.0 V
High-Power Mode
Sleep mode
IDDS1
-
-
Standby mode
IDDS2
-
-
A31W65132
IDD (2)
Units Notes
µA
*11
µA
*12
µA
*12
µA
*13
(Consumption Current at Time of Power Saver Mode, VSS=0V, VDD=3.0V±10%)
. The Relationship between Oscillator Frequency fOSC, Display Clock Frequency fCL and the Liquid Crystal Frame Rate
Frequency fFR
Item
fCL
When the internal oscillator circuit is used
fOSC
A31W65132
4
When the internal oscillator circuit is not used
External input
fFR
fOSC
4 x 65
(fFR is the liquid crystal alternating current period, and not the FR signal period.)
PRELIMINARY
(February, 2001, Version 0.1)
27
AMIC Technology, Inc
A31W65132 Series
Notes:
1. While a broad range of operating voltages is guaranteed, performance cannot be guaranteed if there are sudden
fluctuations to the voltage while the MPU is being accessed.
2. This applies when the external power supply is being used.
3. The A0, D0 to D5, D6 (SCL), D7 (SI), RD (E), WR (R/ W ), CS1, CS2, CLS, CL, FR, M/S, C68/80, P/S, DOF , RES ,
IRS, and HPM terminals.
4. The D0 to D7, FR, FRS, DOF , and CL terminals.
5. The A0, RD (E), WR (R/ W ), CS1, CS2, CLS, M/S, C68/80, P/S, RES , IRS, and HPM terminals.
6. Applies when the D0 to D5, D6 (SCL), D7 (SI), CL, FR, and DOF terminals are in a high impedance state.
7. These are the resistance values for when a 0.1 V voltage is applied between the output terminal SEGn or COMn and the
various power supply terminals (V1, V2, V3, and V4). These are specified for the operating voltage (3) range.
RON = 0.1 V/D I (Where D I is the current that flows when 0.1 V is applied while the power supply is ON.)
8. See the relationship between the oscillator frequency and the frame rate frequency.
9. The V5 voltage regulator circuit regulates within the operating voltage range of the voltage follower.
10. This is the internal voltage reference supply for the V5 voltage regulator circuit. In the A31W65132, the temperature
range can come in three types as VREG options: (1) approximately 0.05%/°C
(2) 0.2%/°C
(3) external input.
11., 12. It indicates the current consumed on ICs alone when the internal oscillator circuit and display are turned on.
The A31W65132 is 1/9 biased.
Does not include the current due to the LCD panel capacity and wiring capacity.
Applicable only when there is no access from the MPU.
12. It is the value on a model having the VREG option temperature gradient is 0.05%/°C when the V5 voltage
regulator internal resistor is used.
13. When consumption current in Power Saver Mode is measured, the A0, RD (E), WR (R/ W ), D0~D7 terminals must be
fixed in H or L.
PRELIMINARY
(February, 2001, Version 0.1)
28
AMIC Technology, Inc
A31W65132 Series
Timing Characteristics
System Bus Read/Write Characteristics 1 (for the 8080 Series MPU)
A0
tAW8
tAH8
CS
(CS2="1")
tCYC8
tCCR, tCCLW
WR, RD
tCCHR, t CCHW
tDS8
tDH8
D0 to D7
(Write)
tACC8
tOH8
D0 to D7
(Read)
(VDD = 4.5V to 5.5V Ta=-40 to 85°C)
Item
Signal
A0
Symbol
Condition
Rating
Min.
Max.
0
0
166
30
-
Units
Address hold time
Address setup time
System cycle time
A0
Control L pulse width ( WR )
WR
tAH8
tAW8
tCYC8
tcclw
Control L pulse width ( RD )
RD
tCCLR
70
-
ns
Control H pulse width ( WR )
WR
tCCHW
30
-
ns
Control H pulse width ( RD )
Data setup time
Address hold time
RD
tCCHR
30
-
ns
D0 to D7
tDS8
tDH8
tACC8
30
10
-
70
ns
ns
ns
5
50
ns
RD access time
Output disable time
PRELIMINARY
(February, 2001, Version 0.1)
CL = 100pF
tOH8
29
ns
ns
ns
ns
AMIC Technology, Inc
A31W65132 Series
(VDD = 2.7V to 4.5V Ta=-40 to 85°C)
WR
tAH8
tAW8
tCYC8
tCCLW
Rating
Min.
Max.
0
0
300
60
-
RD
tCCLR
120
-
ns
Control H pulse width ( WR )
WR
tCCHW
60
-
ns
Control H pulse width ( RD )
Data setup time
Address hold time
RD
tCCHR
60
-
ns
D0 to D7
RD access time
tDS8
tDH8
tACC8
40
15
-
140
ns
ns
ns
Output disable time
tOH8
10
100
ns
Item
Signal
Address hold time
Address setup time
System cycle time
A0
A0
Control L pulse width ( WR )
Control L pulse width ( RD )
Symbol
Condition
CL = 100pF
Units
ns
ns
ns
ns
(VDD = 2.4V to 2.7V Ta=-40 to 85°C)
Item
Signal
A0
Symbol
Condition
Rating
Min.
0
0
1000
120
Max.
-
Units
Address hold time
Address setup time
System cycle time
A0
Control L pulse width ( WR )
WR
tAH8
tAW8
tCYC8
tCCLW
Control L pulse width ( RD )
RD
tCCLR
240
-
ns
Control H pulse width ( WR )
WR
tCCHW
120
-
ns
Control H pulse width ( RD )
Data setup time
Address hold time
RD
tCCHR
120
-
ns
D0 to D7
RD access time
tDS8
tDH8
tACC8
80
30
-
280
ns
ns
ns
Output disable time
tOH8
10
200
ns
CL = 100pF
ns
ns
ns
ns
Notes:
1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr + tf) ≤ (tCYC8 - tCCLW - tCCHW) for (tr + tf) ≤ (tCYC8 - tCCLR - tCCHR) are specified.
2. All timing is specified using 20% and 80% of VDD as the reference.
3. tCCLW and tCCLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and WR and RD being at the “L” level.
PRELIMINARY
(February, 2001, Version 0.1)
30
AMIC Technology, Inc
A31W65132 Series
Timing Characteristics (continued)
System Bus Read/Write Characteristics 2 (for the 6800 Series MPU)
A0
R/W
tAW6
tAH6
CS1
(CS2="1")
tCYC6
tEWHR, t EWHW
E
tEWLR, t EWLW
tDS6
tDH6
D0 to D7
(Write)
tACC6
tOH6
D0 to D7
(Read)
(VDD = 4.5V to 5.5V Ta=-40 to 85°C)
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable H pulse time
Enable L pulse time
PRELIMINARY
Signal
A0
A0
D0 to D7
Read
Write
Read
Write
(February, 2001, Version 0.1)
E
E
Symbol
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
31
Condition
CL = 100pF
Rating
Min.
Max.
0
0
166
30
10
70
10
50
70
30
30
30
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AMIC Technology, Inc
A31W65132 Series
(VDD = 2.7V to 4.5V Ta=-40 to 85°C)
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable H pulse time
Enable L pulse time
Signal
A0
A0
D0 to D7
Read
Write
Read
Write
E
E
Symbol
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
Condition
CL = 100pF
Rating
Min.
Max.
0
0
300
40
15
140
10
100
120
60
60
60
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(VDD = 2.4V to 2.7V Ta=-40 to 85°C)
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable H pulse time
Enable L pulse time
Signal
A0
A0
D0 to D7
Read
Write
Read
Write
E
E
Symbol
tAH6
tAW6
tCYC6
tDS6
tDH6
tACC6
tOH6
tEWHR
tEWHW
tEWLR
tEWLW
Condition
CL = 100pF
Rating
Min.
Max.
0
0
1000
80
30
280
10
280
240
120
120
120
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr + tf) ≤ (tCYC6 - tEWLW - tEWHW) for (tr + tf) ≤ (tCYC6 - tEWLR - tEWHR) are specified.
2. All timing is specified using 20% and 80% of VDD as the reference.
3. tEWLW and tEWLR are specified as the overlap between CS1 being “L” (CS2 = “H”) and E.
PRELIMINARY
(February, 2001, Version 0.1)
32
AMIC Technology, Inc
A31W65132 Series
The Serial Interface
tCSS
tCSH
CS1
(CS2="1")
tSAS
tSAH
A0
tSCYC
tSLW
SCL
tSHW
tf
tr
tSDS
tSDH
SI
(VDD = 4.5V to 5.5V Ta=-40 to 85°C)
Item
Serial Clock Period
SCL "H" pulse width
SCL "L" pulse width
Access setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
PRELIMINARY
(February, 2001, Version 0.1)
Signal
SCL
A0
SI
CS
Symbol
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
33
Condition
Rating
Min.
200
75
75
50
100
50
50
100
100
Max.
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
AMIC Technology, Inc
A31W65132 Series
(VDD = 2.7V to 4.5V Ta=-40 to 85°C)
Item
Serial Clock Period
SCL "H" pulse width
SCL "L" pulse width
Access setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
Signal
SCL
A0
SI
CS
Symbol
Condition
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
Rating
Min.
Max.
250
100
100
150
150
100
100
150
150
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
(VDD = 2.4V to 2.7V Ta=-40 to 85°C)
Item
Serial Clock Period
SCL "H" pulse width
SCL "L" pulse width
Access setup time
Address hold time
Data setup time
Data hold time
CS-SCL time
Signal
SCL
A0
SI
CS
Symbol
tSCYC
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
Condition
Rating
Min.
400
150
150
250
250
150
150
250
250
Max.
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The input signal rise and fall time (tr, tf) are specified at 15ns or less.
2. All timing is specified using 20% and 80% of VDD as the standard.
PRELIMINARY
(February, 2001, Version 0.1)
34
AMIC Technology, Inc
A31W65132 Series
Display Control Output Timing
CL
(OUT)
tDFR
FR
(VDD = 4.5V to 5.5V Ta=-40 to 85°C)
Item
FR delay time
Signal
FR
Symbol
Condition
tDFR
CL = 50 pF
Rating
Min.
-
Typ.
10
Max.
40
Units
ns
(VDD = 2.7V to 4.5V Ta=-40 to 85°C)
Item
FR delay time
Signal
FR
Symbol
Condition
tDFR
CL = 50 pF
Min.
-
Rating
Typ.
20
Max.
80
Units
ns
(VDD = 2.4V to 2.7V Ta=-40 to 85°C)
Item
FR delay time
Signal
FR
Symbol
Condition
tDFR
CL = 50 pF
Min.
-
Rating
Typ.
50
Max.
200
Units
ns
Notes:
1. Valid only when the master mode is selected.
2. All timing is based on 20% and 80% of VDD.
PRELIMINARY
(February, 2001, Version 0.1)
35
AMIC Technology, Inc
A31W65132 Series
Reset Timing
RES
tRW
tR
Internal
status
During reset
Reset complete
(VDD = 4.5V to 5.5V Ta=-40 to 85°C)
Item
Signal
Reset time
Symbol
Condition
tR
Reset "L" pulse width
RES
tRW
Rating
Min.
-
Typ.
-
Max.
0.5
0.5
-
-
Units
µs
µs
(VDD = 2.7V to 4.5V Ta=-40 to 85°C)
Item
Signal
Symbol
Reset time
tR
Reset "L" pulse width
tRW
RES
Condition
Min.
-
Rating
Typ.
-
Max.
1
1
-
-
Units
µs
µs
(VDD = 2.4V to 4.5V Ta=-40 to 85°C)
Item
Signal
Symbol
Reset time
tR
Reset "L" pulse width
tRW
RES
Condition
Rating
Min.
-
Typ.
-
Max.
1.5
1.5
-
-
Units
µs
µs
Note: All timing is specified with 20% and 80% of VDD as the standard.
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AMIC Technology, Inc
A31W65132 Series
Examples of Applications of LCD Power Supply
1. When used all of the step-up circuit, voltage regulating circuit and V/F circuit
. When the voltage regulator internal resistor
is used.
(Example 4x step-up)
. When the voltage regulator internal resistor
is not used.
(Example 4x step-up)
VDD
VDD
C1
VSS
C1
C1
C1
IRS
VSS
VOUT
C3+
C1C1+
C2+
C2V5
VCNT
M/S
C1
C1
C1
VSS
VSS
C2
C2
C2
C2
C2
C1
VSS
VSS
V1
V2
V3
V4
V5
R3
R2
R1
C2
C2
C2
C2
C2
IRS
VSS
VOUT
C3+
C1C1+
C2+
C2V5
VCNT
M/S
VSS
V1
V2
V3
V4
V5
2. When the voltage regulator circuit and V/F circuit alone used
. When the V5 voltage regulator internal resistor
is not used.
. When the V5 voltage regulator internal resistor
is used.
VDD
VSS
External
power
supply
VSS
R3
R2
R1
C2
C2
C2
C2
C2
PRELIMINARY
IRS
VSS
VOUT
C3+
C1C1+
C2+
C2V5
VCNT
VDD
M/S
VSS
External
power
supply
IRS
VSS
VOUT
C3+
C1C1+
C2+
C2V5
VCNT
M/S
VSS
VSS
V1
C2
C2
C2
C2
C2
V2
V3
V4
V5
(February, 2001, Version 0.1)
37
VSS
V1
V2
V3
V4
V5
AMIC Technology, Inc
A31W65132 Series
Examples of Applications of LCD Power Supply (continued)
3. When the V/F circuit alone is used
4. When the built-in power is not used
VDD
VSS
VSS
External
power
supply
IRS
VSS
VOUT
C3+
C1C1+
C2+
C2V5
VCNT
M/S
VDD
IRS
VSS
VOUT
C3+
C1C1+
C2+
C2V5
VCNT
VSS
M/S
VSS
VSS
V1
V2
V3
V4
V5
C2
C2
C2
C2
C2
External
power
supply
5. When the built-in power circuit is used to drive a
liquid crystal panel heavily loaded with AC or DC,
it is recommended to connect an external resistor
to stabilize potentials of V1, V2, V3 and V4 which
are output from the built-in voltage follower.
VSS
VSS
V1
V2
V3
V4
V5
Example of shared reference settings
When V5 can vary between 8 and 12V
Item
Set value
Units
C1
C2
1.0 to 4.7
0.01 to 1.0
uF
uF
VSS, V0
R4 R4
C2
V1
V2
V3
V4
R4 R4
V5
Reference set value R4: 100K Ω ~ 1M Ω
It is recommended to set an optimum
resistance value R4 taking the liquid crystal
display and the drive waveform.
Notes:
1. Because the VR terminal input impedance is high, use short leads and shielded lines.
2. C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage.
Example of the Process by which to Determine the Settings:
• Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside.
• Determine C2 by displaying a LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that
stabilizes the liquid crystal drive voltages (V1 to V5). Note that all C2 capacitors must have the same capacitance value.
• Next turn all the power supplies ON and determine C1.
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AMIC Technology, Inc
A31W65132 Series
Connections Between LCD Drivers (reference examples)
The liquid crystal display area can be enlarged with ease through the use of multiple A31W65132 series chips. Use a same
equipment type.
1. A31W65132 (master) ↔ A31W65132 (slave)
VDD
FR
FR
CL
CL
A31W65132
Slave
M/S
A31W65132
Master
M/S
DOF
DOF
Output
Input
VSS
The liquid crystal display area can be enlarged with ease through the use of multiple A31W65132 series chips. Use a same
equipment type, in the composition of these chips.
1. Single-chip Structure
132 X 65 Dots
COM
SEG
COM
A31W65132 Master
2. Double-chip Structure, # 1
264 X 65 Dots
COM
SEG
SEG
A31W65132 Master
PRELIMINARY
(February, 2001, Version 0.1)
COM
A31W65132 Slave
39
AMIC Technology, Inc
A31W65132 Series
Ordering Information
Part No.
Package
A31W65132C
COG
A31W65132T
TCP
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AMIC Technology, Inc