SLS SL74HC109

SL74HC109
Dual J -K Flip-Flop with Set and Reset
High-Performance Silicon-Gate CMOS
The SL74HC109 is identical in pinout to the LS/ALS109. The device
inputs are compatible with standard CMOS outputs, with pullup
resistors, they are compatible with LS/ALSTTL outputs.
This device consists of two J-K flip-flops with individual set, reset,
and clock inputs. Changes at the inputs are reflected at the outputs
with the next low-to-high transition of the clock. Both Q to Q outputs
are available from each flip-flop.
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µ A
• High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
SL74HC109N Plastic
SL74HC109D SOIC
TA = -55° to 125° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs
PIN 16=VCC
PIN 8 = GND
Outputs
Set
Reset
Clock
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
H
X
*
*
X
X
H
H
H
L
L
L
H
H
H
H
L
Toggle
H
H
L
H
No Change
H
H
H
H
H
H
H
X
X
No Change
L
L
X = Don’t care
*
Both outputs will remain high as long as Set and
Reset are low, but the output states are
unpredictable if Set and Reset go high
simultaneously.
SLS
System Logic
Semiconductor
SL74HC109
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
-0.5 to +7.0
V
VCC
DC Supply Voltage (Referenced to GND)
VI N
DC Input Voltage (Referenced to GND)
-1.5 to VCC +1.5
V
DC Output Voltage (Referenced to GND)
-0.5 to VCC +0.5
V
DC Input Current, per Pin
± 20
mA
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
mW
-65 to +150
°C
260
°C
VO U T
II N
IO U T
Tstg
Storage Temperature
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/° C from 65° to 125° C
SOIC Package: : - 7 mW/° C from 65° to 125° C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
DC Supply Voltage (Referenced to GND)
VI N , VO U T
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr , t f
Input Rise and Fall Time (Figure 1)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
Min
Max
Unit
2.0
6.0
V
0
VCC
V
-55
+125
°C
0
0
0
1000
500
400
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, VI N and VO U T should be constrained to the range
GND≤ (VI N or VO U T )≤ VCC.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused outputs must be left open.
SLS
System Logic
Semiconductor
SL74HC109
D C E L E C T R I C A L C H A R A C T E R I S T I C S (Voltages Referenced to GND)
VCC
Guaranteed Limit
Test Conditions
V
25 ° C
to
-55° C
≤ 85
°C
≤ 125
°C
Unit
Minimum High-Level
Input Voltage
VO U T =0.1 V or VCC-0.1 V
 IO U T ≤ 20 µ A
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
VIL
Maximum Low -Level
Input Voltage
VO U T =0.1 V or VCC-0.1 V
 IO U T  ≤ 20 µ A
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
VO H
Minimum High-Level
Output Voltage
VI N =VI H or VIL
 IO U T  ≤ 20 µ A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
4.5
6.0
3.98
5.48
3.84
5.34
3.7
5.2
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VI N = VIL or VI H
 IO U T  ≤ 4.0 mA
 IO U T  ≤ 5.2 mA
4.5
6.0
0.26
0.26
0.33
0.33
0.4
0.4
Symbol
Parameter
VI H
VI N =VI H or VIL
 IO U T  ≤ 4.0 mA
 IO U T  ≤ 5.2 mA
VO L
Maximum Low-Level
Output Voltage
VI N = VIL or VI H
 IO U T  ≤ 20 µ A
V
II N
Maximum Input
Leakage Current
VI N =VCC or GND
6.0
± 0.1
± 1.0
± 1.0
µA
ICC
Maximum Quiescent
Supply Current
(per Package)
VI N =VCC or GND
IO U T =0µ A
6.0
4.0
40
80
µA
SLS
System Logic
Semiconductor
SL74HC109
A C E L E C T R I C A L C H A R A C T E R I S T I C S (CL =50pF,Input t r =t f =6.0 ns)
VCC
Symbol
Parameter
Guaranteed Limit
V
25 ° C to
-55° C
≤ 85° C
≤ 125° C
Unit
fm a x
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
4.5
6.0
6
30
35
4.8
24
28
4.0
20
24
MHz
tP L H , t P H L
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
4.5
6.0
175
35
30
220
44
37
265
53
45
ns
tP L H , t P H L
Maximum Propagation Delay , Set or Reset to Q or
Q (Figures 2 and 4)
2.0
4.5
6.0
230
46
39
290
58
49
345
69
59
ns
tT L H , t T H L
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
4.5
6.0
75
15
13
95
19
16
110
22
19
ns
-
10
10
10
pF
CI N
Maximum Input Capacitance
CP D
Power Dissipation Capacitance (Per Flip-Flop)
Typical @25° C,VCC=5.0 V
Used to determine the no-load dynamic power
2
consumption: PD =CP D VCC f+ICCVCC
40
pF
T I M I N G R E Q U I R E M E N T S (CL =50pF,Input t r =t f =6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25 ° C to -55° C
≤ 85° C
≤ 125° C
Unit
tSU
Minimum Setup Time, J or K to
Clock (Figure 3)
2.0
4.5
6.0
100
20
17
125
25
21
150
30
26
ns
th
Minimum Hold Time, Clock to
J or K (Figure 3)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
tr e c
Minimum Recovery Time, Set
or Reset Inactive to Clock
(Figure 2)
2.0
4.5
6.0
5
5
5
5
5
5
5
5
5
ns
tw
Minimum Pulse Width, Set or
Reset (Figure 2)
2.0
4.5
6.0
80
16
14
100
20
17
12
24
20
ns
tw
Minimum Pulse Width,Clock
(Figure 1)
2.0
4.5
6.0
80
16
14
100
20
17
12
24
20
ns
tr, tf
Maximum Input Rise and Fall
Times (Figure 1)
2.0
4.5
6.0
1000
500
400
1000
500
400
1000
500
400
ns
SLS
System Logic
Semiconductor
SL74HC109
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
SLS
System Logic
Semiconductor