NPC SM6451A

SM6451A
Audio Variable Volume IC
OVERVIEW
The SM6451A is a 3-wire serial-controlled electronic variable volume IC for audio applications. It provides
electronic volume control for a stereo system (left and right channels), and independent channel attenuation
and muting, with greatly enhanced digital zip noise suppression. The chip address function allows up to four
SM6451A devices to be connected and individually controlled over the 3-wire control interface from a single
CPU. It is available in 16-pin TSSOP packages.
FEATURES
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PINOUT
Stereo inputs and outputs
Attenuation function
• 2-channel independent control
• 1.0dB/step over 80 steps
• 0 to −80dB range
Mute function
3-wire serial data control (MDT, MCK, MLEN)
Chip addressing (up to 4 devices can be connected
in parallel)
Low noise
• ≤ 0.002% THD + noise
• 10µVrms residual noise
5V single power supply
Silicon-gate CMOS process
Package: 16-pin TSSOP (Pb free)
RSTN
1
16
MDT
ADRS1
MCK
ADRS2
MLEN
DVDD
DVSS
LOUT
ROUT
LIN
RIN
AVDD
VRL
AVSS
8
9
VRR
PACKAGE DIMENSIONS
APPLICATIONS
■
(Top view)
(Unit: mm)
Weight: 0.07g
Audio equipment
ORDERING INFORMATION
1.00TYP
0.50 ± 0.10
0.44TYP
1.00 ± 0.05
0 to 8
0.225TYP
0.65
0.08
+ 0.08
0.22 − 0.07
+ 0.03
1.07 − 0.07
16-pin TSSOP
0.17 ± 0.05
6.40 ± 0.2
SM6451AT
5.20MAX
5.00 ± 0.08
+ 0.03
0.07 − 0.04
Package
4.40 ± 0.1
Device
0.13 M
SEIKO NPC CORPORATION —1
SM6451A
BLOCK DIAGRAM
DVDD
DVSS
Attenuation
Control
LIN
LOUT
1/2VDD
Reference
Voltage
Circuits
ADRS1
ADRS2
VRL
Attenuation Decoder
Chip
Address
Decoder
Interface Control
MLEN
MCK
MDT
RSTN
VRR
1/2VDD
Attenuation
Control
RIN
AVDD
ROUT
AVSS
PIN DESCRIPTION
1.
Number
Name
I/O1
A/D1
1
RSTN
Ip
D
System reset input (LOW-level reset)
2
ADRS1
Ip
D
Chip address set 1
3
ADRS2
Ip
D
Chip address set 2
4
DVDD
–
D
Digital supply
5
LOUT
O
A
Left-channel audio output
6
LIN
I
A
Left-channel audio input
7
AVDD
–
A
Analog supply
8
VRL
O
A
Left-channel reference voltage (0.5VDD). Connect a 10µF capacitor
between VRL and AVSS.
9
VRR
O
A
Right-channel reference voltage (0.5VDD). Connect a 10µF capacitor
between VRR and AVSS.
10
AVSS
–
A
Analog ground
11
RIN
I
A
Right-channel audio input
12
ROUT
O
A
Right-channel audio output
13
DVSS
–
D
Digital ground
14
MLEN
Ip
D
Microcontroller latch enable input
15
MCK
Ip
D
Microcontroller clock input
16
MDT
Ip
D
Microcontroller data input
Description
Ip = input pin with pull-up, A = analog, D= digital
SEIKO NPC CORPORATION —2
SM6451A
SPECIFICATIONS
Absolute Maximum Ratings
DVSS = AVSS = 0V, DVDD = AVDD = VDD
Parameter
Symbol
Rating
Unit
Supply voltage
VDD
−0.3 to 7.0
V
Input voltage
VIN
VSS − 0.3 to VDD + 0.3
V
Power dissipation
PD
150
mW
Storage temperature
Tstg
−55 to 125
°C
Symbol
Rating
Unit
VDD
4.5 to 5.5
V
DVDD − AVDD, DVSS − AVSS
±0.1
V
Topr
−40 to 85
°C
Note. Rating applies at power-ON and power-OFF.
Recommended Operating Conditions
DVSS = AVSS = 0V, DVDD = AVDD = VDD
Parameter
Supply voltage
Supply voltage deviation
Operating temperature
DC Characteristics
DVDD = AVDD = VDD = 4.5 to 5.5V, VSS = 0V, Ta = −40 to 85°C
Rating
Parameter
DVDD Current consumption
Symbol
IDDD1
IDDD2
Condition
Data transfer stopped, MDT, MCK,
MLEN, RSTN, ADRS1, ADRS2 = VDD
ADRS1 = ADRS2 = 0V, 1.2Vrms analog
input, ATT = 0dB, data transfer active
Unit
min
typ
max
–
0.3
1.0
µA
–
1
2
mA
–
4.5
8
mA
AVDD Current consumption
IDDA
HIGH-level input voltage1
VIH
0.7VDD
–
–
V
LOW-level input voltage1
VIL
–
–
0.3VDD
V
Input current1
IIL
VIN = 0V
–
230
400
µA
Input leakage current1
IIH
VIN = VDD
–
–
1.0
µA
1.
MDT, MCK, MLEN, RSTN, ADRS1, ADRS2
SEIKO NPC CORPORATION —3
SM6451A
AC Digital Characteristics
DVDD = AVDD = VDD = 4.5 to 5.5V, VSS = 0V, Ta = −40 to 85°C
Serial inputs (MDT, MCK, MLEN)
Rating
Parameter
Symbol
Unit
min
typ
max
MCK, MLEN rise time
tr
–
–
100
ns
MCK, MLEN fall time
tf
–
–
100
ns
MCK pulse cycle
tMCK
100
–
10000
ns
MDT setup time
tMDS
50
–
–
ns
MDT hold time
tMDH
50
–
–
ns
MLEN setup time
tMCS
50
–
–
ns
MLEN hold time
tMCH
50
–
–
ns
MLEN LOW-level pulsewidth
tMEWL
16
–
–
tMCK
MLEN HIGH-level pulsewidth
tMEWH
50
–
5000
ns
0.5VDD
MDT
tMDS
tMDH
MCK
0.5VDD
tMCS
tMCH
MLEN
0.5VDD
tMEWL
tMEWH
tf
MCK
MLEN
tr
0.9VDD
0.9VDD
0.1VDD
0.5VDD
0.1VDD
Reset input (RSTN)
Rating
Parameter
RSTN LOW-level pulsewidth
Symbol
tRSTN
Unit
min
typ
max
100
–
–
ns
SEIKO NPC CORPORATION —4
SM6451A
AC Analog Characteristics
VDD = 5.0V, 1.2Vrms amplitude, 1kHz input frequency, 100kΩ output load resistance, Ta = 25°C,
AC-coupled inputs
Analog inputs (LIN, RIN)
Rating
Parameter
Symbol
Condition
Unit
min
typ
max
Input reference amplitude
VAI
–
1.2
–
Vrms
Input resistance
RIN
40
50
60
kΩ
Input clipping voltage
VCLP
–
1.75
–
Vrms
THD + N = 1%, ATT = 0dB
Analog outputs (LOUT, ROUT)
Rating
Parameter
Symbol
Residual noise voltage
VNS
Signal-to-noise ratio
SNR
Total harmonic distortion + noise
THD + N
Condition
Input signal: 0Vrms,
A-weight filter, 0dBr =
1.2Vrms, ATT = 0dB
ATT = 0dB, 20kHz lowpass
filter
Unit
min
typ
max
–
10
20
µVrms
95
100
–
dBr
–
0.0017
0.0025
%
Gain control range
RCNT
−80
–
0
dB
Step size
Step
0.8
1
1.5
dB
ERR1
0 to −60dB
−2
–
1
dB
ERR2
−61 to −80dB
−5
–
0
dB
AT0
ATT = 0dB
–
−0.1
–
dB
AT2
ATT = −20dB
–
−20.1
–
dB
AT4
ATT = −40dB
–
−40.3
–
dB
AT6
ATT = −60dB
–
−60.5
–
dB
AT8
ATT = −80dB
–
−83.0
–
dB
Mute
ATT = Mute
−88
−92
–
dB
Channel crosstalk
CT
ATT = 0dB
−105
−112
–
dB
Frequency response
FR
ATT = 0dB, f = 200kHz
–
−5
–
dB
Quiescent output zip noise voltage
(while ATT value adjusting)
NJ
0Vrms input
–
–
3
mV
Minimum driver load resistance
RML
ATT = 0dB, THD + N = 1%
–
6
10
kΩ
Symbol
Condition
Attenuation error (1k to 20kHz)
Absolute attenuation (1kHz)
Mute attenuation (1kHz)
Reference voltage (VRL, VRR)
Rating
Parameter
Reference voltage output
VREF
Unit
min
typ
max
0.45VDD
0.5VDD
0.55VDD
V
SEIKO NPC CORPORATION —5
SM6451A
MEASUREMENT CIRCUIT
Chip address: ADRS1 = LOW, ADRS2 = LOW
0.001µF
MDT 16
2 ADRS1
MCK 15
3 ADRS2
MLEN 14
4 DVDD
DVSS 13
5 LOUT
0.022µF
6 LIN
7 AVDD
+
10µF
+
1µF
0.022µF
+
8 VRL
+
10µF
0.022µF
SM6451
+
10µF
1 RSTN
CPU
ROUT 12
RIN 11
AVSS 10
VRR 9
0.022µF
1µF
+
10µF
+
1µF
+
1µF
100kΩ
100kΩ
Generator
Analyzer
Audio Precision
System One SYS − 322A
SEIKO NPC CORPORATION —6
SM6451A
MICROCONTROLLER INTERFACE
The SM6451A uses a 3-wire serial interface comprising MDT (data), MCK (clock) and MLEN (latch enable)
to select channels and attenuation levels for the addressed device.
Input Timing
The microcontroller data input timing is shown in figure 1.
MDT
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
MCK
MLEN
Figure 1. Microcontroller data input timing
Data is shifted into the internal shift register on the rising edge of MCK, and the attenuation value is updated on
the rising edge of MLEN. Accordingly, data on MDT should be changed on the falling edge of MCK.
Note, however, a minimum of 16 MCK input pulses are required.
Data Format
Channel
Select
Attenuation
Data 7
Attenuation
Data 6
Attenuation
Data 5
Attenuation
Data 4
Attenuation
Data 3
Attenuation
Data 2
Attenuation
Data 1
Attenuation
Data 0
D4
D3
D2
D1
D0
Don't
Care
D5
Don't
Care
D6
Chip
Address 2
D7
Chip
Address 1
D8
Don't
Care
D15 D14 D13 D12 D11 D10 D9
Don't
Care
MDT
Channel
Select
The format of microcontroller input data is shown in figure 2.
Figure 2. Microcontroller data format
D15, D14
Don’t care.
D13, D12
Chip address bits. D13 corresponds to ADRS1 and D12 corresponds to ADRS2. The device is addressed only
when ADRS1:ADRS2 matches D13:D12.
Example 1: If D13 = LOW, D12 = HIGH and ADRS1 = LOW, ADRS2 = LOW, then the device is not
addressed since ADRS2 and D12 do not match.
Example 2: If D13/D12 = LOW and ADRS1/ADRS2 = LOW, then the device is addressed and all input data
is read and the attenuation settings updated.
D11, D10
Don’t care.
SEIKO NPC CORPORATION —7
SM6451A
D9, D8
Channel select bits. The selected channel(s) are shown in table 1.
Table 1. Channel select
D9
D8
Selected channel
LOW
LOW
Both left and right channels
LOW
HIGH
Left channel
HIGH
LOW
Right channel
HIGH
HIGH
No change
D7 to D0
Attenuation register (ATT) set bits.
Table 2. Attenuation setting
Attenuation
0 dB
−1 dB
−2 dB
:
−15 dB
−16 dB
−17 dB
:
−63 dB
−64 dB
−65 dB
:
−79 dB
−80 dB
Mute
Mute
:
Mute
Mute
ATTH
00
01
02
:
0F
10
11
:
3F
40
41
:
4F
50
51
52
:
FE
FF
D7
LOW
LOW
LOW
:
LOW
LOW
LOW
:
LOW
LOW
LOW
:
LOW
LOW
LOW
LOW
:
HIGH
HIGH
D6
LOW
LOW
LOW
:
LOW
LOW
LOW
:
LOW
HIGH
HIGH
:
HIGH
HIGH
HIGH
HIGH
:
HIGH
HIGH
D5
LOW
LOW
LOW
:
LOW
LOW
LOW
:
HIGH
LOW
LOW
:
LOW
LOW
LOW
LOW
:
HIGH
HIGH
D4
LOW
LOW
LOW
:
LOW
HIGH
HIGH
:
HIGH
LOW
LOW
:
LOW
HIGH
HIGH
HIGH
:
HIGH
HIGH
D3
LOW
LOW
LOW
:
HIGH
LOW
LOW
:
HIGH
LOW
LOW
:
HIGH
LOW
LOW
LOW
:
HIGH
HIGH
D2
LOW
LOW
LOW
:
HIGH
LOW
LOW
:
HIGH
LOW
LOW
:
HIGH
LOW
LOW
LOW
:
HIGH
HIGH
D1
LOW
LOW
HIGH
:
HIGH
LOW
LOW
:
HIGH
LOW
LOW
:
HIGH
LOW
LOW
HIGH
:
HIGH
HIGH
D0
LOW
HIGH
LOW
:
HIGH
LOW
HIGH
:
HIGH
LOW
HIGH
:
HIGH
LOW
HIGH
LOW
:
LOW
HIGH
Note. Outputs are muted after system reset.
SEIKO NPC CORPORATION —8
SM6451A
ANALOG PERFORMANCE CHARACTERISTICS
DVDD = AVDD = 5.0V, 100kΩ output load resistance, Ta = 25°C
0.1
1
ATT = 0dB
20kHz LPF
THD + N [%]
THD + N [%]
f = 1kHz
ATT = 0dB
20kHz LPF
0.1
0.01 VIN = 0.2Vrms
VIN = 0.4Vrms
0.01
VIN = 0.8Vrms
VIN = 1.2Vrms
0.001
0.001
0.1
1
20
2
100
1k
VIN [Vrms]
10k
Figure 3. THD + N vs. input amplitude
Figure 4. THD + N vs. input frequency
20
2
VIN = 1.2Vrms
f = 1kHz
1
16
VIN = 0Vrms
A-Weight Filter
Noise [µV]
0
Error [dB]
20k
Freq [Hz]
−1
−2
12
8
−3
4
−4
−5
0
−10
−20
−30
−40
−50
−60
−70
0
−80
0
−10
−20
ATT [dB]
ATT = −60dB
ATT = −80dB
−80
−70
−80
VIN = 1.2Vrms
ATT = 0dB
−60
Cross Talk Gain [dB]
Gain [dB]
VIN = 1.2Vrms
ATT = −40dB
−60
−60
−40
ATT = −20dB
−40
−50
Figure 6. Residual noise vs. ATT
ATT = 0dB
−20
−40
ATT [dB]
Figure 5. Attenuation error
+0
−30
−80
−100
−120
ATT = MUTE
−100
20
100
1k
10k
100k
−140
20
100
1k
10k
100k
Freq [Hz]
Freq [Hz]
Figure 7. Frequency response
Figure 8. Crosstalk frequency response
SEIKO NPC CORPORATION —9
SM6451A
100
+0
VIN = 1.2Vrms = 0dB
f = 1kHz
ATT = 0dB
BH window
FFT Gain [dB]
−40
−60
−80
−100
VIN = 1.2Vrms
f = 1kHz
ATT = 0dB
20kHz LPF
10
THD + N [%]
−20
1
0.1
−120
0.01
−140
−160
0.001
0
2k
4k
6k
8k
10k
12k
14k
16k
1k
18k 20k
Figure 9. FFT plot (ATT = 0dB)
Figure 10. THD + N vs. load resistance
10
AVDD + DVDD
ADRS1 = ADRS2 = 5V
8
6
4
4.75
5.00
5.25
5.50
Supply volutage [V]
Figure 11. Current consumption vs. supply voltage
Current consumption [mA]
Current consumption [mA]
10
2
4.50
100k
10k
Load resistance [Ω]
Freq [Hz]
AVDD + DVDD
ADRS1 = ADRS2 = 5V
8
6
4
2
-50
-25
0
25
50
75
100
Operating temperature [°C]
Figure 12. Current consumption vs. temperature
SEIKO NPC CORPORATION —10
SM6451A
TYPICAL APPLICATIONS
Connection Guidelines
Decoupling capacitors of approximately 10µF should be connected from AVDD, VRL, VRR to AVSS, and
from DVDD to DVSS.
In addition, approximately 0.01µF capacitors should also be connected from AVDD, VRL, VRR to AVSS, and
from DVDD to DVSS to suppress digital switch noise.
An approximately 0.001µF capacitor connected from RSTN to DVSS will force a system reset when power is
applied.
Connection 1 (to DAC)
+ 5V
DVDD
AVDD1 to 4
LOA
LOBN
SM5864
ROA
ROBN
DVSS
DVDD
Analog L.P.F.
LIN
Analog L.P.F.
RIN
AVDD
for Front
LOUT
L-ch OUT
ROUT
R-ch OUT
SM6451
AVSS1 to 4
ADRS1
DVSS
ADRS2
AVSS
MDT MCK MLEN
CPU
MDT MCK MLEN
ADRS1
AVDD
ADRS2
DVDD
for Rear
SM6451
LIN
LOUT
L-ch OUT
RIN
ROUT
R-ch OUT
AVSS
DVSS
SEIKO NPC CORPORATION —11
SM6451A
Connection 2
R
3.3R
3.3R
R
L-ch Input
LIN
4Vrms
LOUT
L-ch Output
1.2Vrms
R
SM6451
3.3R
3.3R
R-ch Input
R
RIN
ROUT
R-ch Output
The SM6451A uses a 1.2Vrms input reference amplitude. If the input signal is 4Vrms, then the input must be
reduced by a factor of 1/3.3, and the output increased by a factor of 3.3.
Connection 3
AVDD
L-ch Input
LIN
LOUT
L-ch Output
SM6451
R-ch Input
RIN
ROUT
R-ch Output
AVSS
When there is a possibility that the input peak-to-peak amplitude will exceed the supply voltage, input protection diodes should be connected to prevent device breakdown.
SEIKO NPC CORPORATION —12
SM6451A
Please pay your attention to the following points at time of using the products shown in this document.
The products shown in this document (hereinafter “Products”) are not intended to be used for the apparatus that exerts harmful influence on
human lives due to the defects, failure or malfunction of the Products. Customers are requested to obtain prior written agreement for such
use from SEIKO NPC CORPORATION (hereinafter “NPC”). Customers shall be solely responsible for, and indemnify and hold NPC free and
harmless from, any and all claims, damages, losses, expenses or lawsuits, due to such use without such agreement. NPC reserves the right
to change the specifications of the Products in order to improve the characteristic or reliability thereof. NPC makes no claim or warranty that
the contents described in this document dose not infringe any intellectual property right or other similar right owned by third parties.
Therefore, NPC shall not be responsible for such problems, even if the use is in accordance with the descriptions provided in this document.
Any descriptions including applications, circuits, and the parameters of the Products in this document are for reference to use the Products,
and shall not be guaranteed free from defect, inapplicability to the design for the mass-production products without further testing or
modification. Customers are requested not to export or re-export, directly or indirectly, the Products to any country or any entity not in
compliance with or in violation of the national export administration laws, treaties, orders and regulations. Customers are requested
appropriately take steps to obtain required permissions or approvals from appropriate government agencies.
SEIKO NPC CORPORATION
15-6, Nihombashi-kabutocho, Chuo-ku,
Tokyo 103-0026, Japan
Telephone: +81-3-6667-6601
Facsimile: +81-3-6667-6611
http://www.npc.co.jp/
Email: [email protected]
NC9704EE
2006.04
SEIKO NPC CORPORATION —13