SM6451AV Audio Variable Volume IC NIPPON PRECISION CIRCUITS INC. OVERVIEW PINOUT The SM6451AV is a 3-wire serial-controlled electronic variable volume IC for audio applications. It provides electronic volume control for a stereo system (left and right channels), and independent channel attenuation and muting, with greatly enhanced digital zip noise suppression. The chip address function allows up to four SM6451AV devices to be connected and individually controlled over the 3-wire control interface from a single CPU. It is available in 16-pin VSOP packages. (Top View) RSTN 1 16 MCK ADRS2 MLEN 6451AV ADRS1 DVDD LOUT LIN DVSS ROUT RIN AVDD FEATURES ■ ■ ■ ■ ■ ■ VRL Stereo inputs and outputs Attenuation function • 2-channel independent control • 1.0 dB/step over 80 steps • 0 to −80 dB range Mute function 3-wire serial data control (MDT, MCK, MLEN) Chip addressing (up to 4 devices can be connected in parallel) Low noise • ≤ 0.002% THD + noise • 10 µVrms residual noise 5 V single power supply Silicon-gate CMOS process AVSS 8 9 VRR PACKAGE DIMENSIONS (Unit: mm) 16 pin VSOP 4.4 0.2 6.4 0.2 ■ ■ MDT APPLICATIONS ■ Audio equipment + 0.1 0.05 0.15 - 0.275TYP 5.1 0.2 ORDERING INFORMATION Package SM6451AV 16-pin VSOP 0.65 0.10 + 0.10 0.22 - 0.05 0.12 M 0.10 0.05 1.15 0.1 0 10 Device 0.5 0.2 NIPPON PRECISION CIRCUITS—1 SM6451AV BLOCK DIAGRAM DVDD DVSS Attenuation Control LIN LOUT 1/2VDD Reference Voltage Circuits ADRS1 ADRS2 VRL Attenuation Decoder Chip Address Decoder Interface Control MLEN MCK MDT RSTN VRR 1/2VDD Attenuation Control RIN AVDD ROUT AVSS PIN DESCRIPTION 1. Number Name I/O1 A/D1 1 RSTN Ip D System reset input (LOW-level reset) 2 ADRS1 Ip D Chip address set 1 3 ADRS2 Ip D Chip address set 2 4 DVDD – D Digital supply 5 LOUT O A Left-channel audio output 6 LIN I A Left-channel audio input 7 AVDD – A Analog supply 8 VRL O A Left-channel reference voltage (0.5VDD). Connect a 10 µF capacitor between VRL and AVSS. 9 VRR O A Right-channel reference voltage (0.5VDD). Connect a 10 µF capacitor between VRR and AVSS. 10 AVSS – A Analog ground 11 RIN I A Right-channel audio input 12 ROUT O A Right-channel audio output 13 DVSS – D Digital ground 14 MLEN Ip D Microcontroller latch enable input 15 MCK Ip D Microcontroller clock input 16 MDT Ip D Microcontroller data input Description Ip = input pin with pull-up, A = analog, D= digital NIPPON PRECISION CIRCUITS—2 SM6451AV SPECIFICATIONS Absolute Maximum Ratings DVSS = AVSS = 0 V, DVDD = AVDD = VDD Parameter Symbol Rating Unit Supply voltage VDD −0.3 to 7.0 V Input voltage VIN VSS − 0.3 to VDD + 0.3 V Power dissipation PD 150 mW Storage temperature Tstg −55 to 125 °C Soldering temperature Tsld 255 °C Soldering time tsld 10 s Symbol Rating Unit VDD 4.5 to 5.5 V DVDD − AVDD, DVSS − AVSS ±0.1 V Topr −40 to 85 °C Recommended Operating Conditions DVSS = AVSS = 0 V, DVDD = AVDD = VDD Parameter Supply voltage Supply voltage deviation Operating temperature DC Characteristics DVDD = AVDD = VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −40 to 85 °C Rating Parameter DVDD Current consumption Symbol IDDD1 IDDD2 Condition Data transfer stopped, MDT, MCK, MLEN, RSTN, ADRS1, ADRS2 = VDD ADRS1 = ADRS2 = 0V, 1.2 Vrms analog input, ATT = 0 dB, data transfer active Unit min typ max – 0.3 1.0 µA – 1 2 mA – 4.5 8 mA AVDD Current consumption IDDA HIGH-level input voltage1 VIH 0.7VDD – – V LOW-level input voltage1 VIL – – 0.3VDD V Input current1 IIL VIN = 0 V – 230 400 µA Input leakage current1 IIH VIN = VDD – – 1.0 µA 1. MDT, MCK, MLEN, RSTN, ADRS1, ADRS2 NIPPON PRECISION CIRCUITS—3 SM6451AV AC Digital Characteristics DVDD = AVDD = VDD = 4.5 to 5.5 V, VSS = 0 V, Ta = −40 to 85 °C Serial inputs (MDT, MCK, MLEN) Rating Parameter Symbol Unit min typ max MCK, MLEN rise time tr – – 100 ns MCK, MLEN fall time tf – – 100 ns MDT setup time tMDS 50 – – ns MDT hold time tMDH 50 – – ns MLEN setup time tMCS 50 – – ns MLEN hold time tMCH 50 – – ns MLEN LOW-level pulsewidth tMEWL 50 – – ns MLEN HIGH-level pulsewidth tMEWH 50 – – ns 0.5VDD MDT tMDS tMDH MCK 0.5VDD tMCS tMCH MLEN 0.5VDD tMEWL tMEWH tf tr 0.9VDD MCK MLEN 0.9VDD 0.1VDD 0.1VDD 0.5VDD Reset input (RSTN) Rating Parameter RSTN LOW-level pulsewidth Symbol tRSTN Unit min typ max 100 – – ns NIPPON PRECISION CIRCUITS—4 SM6451AV AC Analog Characteristics VDD = 5.0 V, 1.2 Vrms amplitude, 1 kHz input frequency, 100 kΩ output load resistance, Ta = 25 °C, AC-coupled inputs Analog inputs (LIN, RIN) Rating Parameter Symbol Condition Unit min typ max Input reference amplitude VAI – 1.2 – Vrms Input resistance RIN 40 50 60 kΩ Input clipping voltage VCLP – 1.75 – Vrms THD + N = 1%, ATT = 0 dB Analog outputs (LOUT, ROUT) Rating Parameter Symbol Residual noise voltage VNS Signal-to-noise ratio SNR Total harmonic distortion + noise THD + N Condition Input signal: 0 Vrms, A-weight filter, 0 dBr = 1.2 Vrms, ATT = 0 dB ATT = 0 dB, 20 kHz lowpass filter Unit min typ max – 10 20 µVrms 95 100 – dBr – 0.0017 0.0025 % Gain control range RCNT −80 – 0 dB Step size Step 0.8 1 1.5 dB ERR1 0 to −60 dB −2 – 1 dB ERR2 −61 to −80 dB −5 – 0 dB AT0 ATT = 0 dB – −0.1 – dB AT2 ATT = −20 dB – −20.1 – dB AT4 ATT = −40 dB – −40.3 – dB AT6 ATT = −60 dB – −60.5 – dB AT8 ATT = −80 dB – −83.0 – dB Mute ATT = Mute −88 −92 – dB Channel crosstalk CT ATT = 0 dB −105 −112 – dB Frequency response FR ATT = 0 dB, f = 200 kHz – −5 – dB Quiescent output zip noise voltage (while ATT value adjusting) NJ 0 Vrms input – – 3 mV Minimum driver load resistance RML ATT = 0 dB, THD + N = 1% – 6 10 kΩ Symbol Condition Attenuation error (1k to 20kHz) Absolute attenuation (1 kHz) Mute attenuation (1 kHz) Reference voltage (VRL, VRR) Rating Parameter Reference voltage output VREF Unit min typ max 0.45VDD 0.5VDD 0.55VDD V NIPPON PRECISION CIRCUITS—5 SM6451AV MEASUREMENT CIRCUIT Chip address: ADRS1 = LOW, ADRS2 = LOW 330pF 0.022uF MDT 16 2 ADRS1 MCK 15 3 ADRS2 MLEN 14 4 DVDD DVSS 13 5 LOUT ROUT 12 6 LIN + 10uF + 1uF 0.022uF + 7 AVDD + 10uF SM6451 + 10uF 1 RSTN 8 VRL 0.022uF CPU RIN 11 AVSS 10 VRR 9 0.022uF 1uF + 10uF + 1uF + 1uF 100kΩ 100kΩ Generator Analyzer Audio Precision System One SYS − 322A NIPPON PRECISION CIRCUITS—6 SM6451AV MICROCONTROLLER INTERFACE The SM6451AV uses a 3-wire serial interface comprising MDT (data), MCK (clock) and MLEN (latch enable) to select channels and attenuation levels for the addressed device. Input Timing The microcontroller data input timing is shown in figure 1. MDT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MCK MLEN Figure 1. Microcontroller data input timing Data is shifted into the internal shift register on the rising edge of MCK, and the attenuation value is updated on the rising edge of MLEN. Accordingly, data on MDT should be changed on the falling edge of MCK. The dotted lines for MCK and MLEN also indicate valid timing. Note, however, a minimum of 16 MCK input pulses are required. Data Format Attenuation Data 7 Attenuation Data 6 Attenuation Data 5 Attenuation Data 4 Attenuation Data 3 Attenuation Data 2 Attenuation Data 1 Attenuation Data 0 D15 D14 D13 D12 D11 D10 D9 Channel Select Channel Select Don't Care Don't Care Chip Address 2 Chip Address 1 Don't Care MDT Don't Care The format of microcontroller input data is shown in figure 2. D8 D7 D6 D5 D4 D3 D2 D1 D0 Figure 2. Microcontroller data format D15, D14 Don’t care. D13, D12 Chip address bits. D13 corresponds to ADRS1 and D12 corresponds to ADRS2. The device is addressed only when ADRS1:ADRS2 matches D13:D12. Example 1: If D13 = LOW, D12 = HIGH and ADRS1 = LOW, ADRS2 = LOW, then the device is not addressed since ADRS2 and D12 do not match. Example 2: If D13/D12 = LOW and ADRS1/ADRS2 = LOW, then the device is addressed and all input data is read and the attenuation settings updated. D11, D10 Don’t care. NIPPON PRECISION CIRCUITS—7 SM6451AV D9, D8 Channel select bits. The selected channel(s) are shown in table 1. Table 1. Channel select D9 D8 Selected channel LOW LOW Both left and right channels LOW HIGH Left channel HIGH LOW Right channel HIGH HIGH No change D7 to D0 Attenuation register (ATT) set bits. Table 2. Attenuation setting1 Attenuation 0 dB −1 dB −2 dB : −15 dB −16 dB −17 dB : −63 dB −64 dB −65 dB : −79 dB −80 dB Mute Mute : Mute Mute 1. ATT H 00 01 02 : 0F 10 11 : 3F 40 41 : 4F 50 51 52 : FE FF D7 LOW LOW LOW : LOW LOW LOW : LOW LOW LOW : LOW LOW LOW LOW : HIGH HIGH D6 LOW LOW LOW : LOW LOW LOW : LOW HIGH HIGH : HIGH HIGH HIGH HIGH : HIGH HIGH D5 LOW LOW LOW : LOW LOW LOW : HIGH LOW LOW : LOW LOW LOW LOW : HIGH HIGH D4 LOW LOW LOW : LOW HIGH HIGH : HIGH LOW LOW : LOW HIGH HIGH HIGH : HIGH HIGH D3 LOW LOW LOW : HIGH LOW LOW : HIGH LOW LOW : HIGH LOW LOW LOW : HIGH HIGH D2 LOW LOW LOW : HIGH LOW LOW : HIGH LOW LOW : HIGH LOW LOW LOW : HIGH HIGH D1 LOW LOW HIGH : HIGH LOW LOW : HIGH LOW LOW : HIGH LOW LOW HIGH : HIGH HIGH D0 LOW HIGH LOW : HIGH LOW HIGH : HIGH LOW HIGH : HIGH LOW HIGH LOW : LOW HIGH Outputs are muted after system reset. NIPPON PRECISION CIRCUITS—8 SM6451AV ANALOG PERFORMANCE CHARACTERISTICS DVDD = AVDD = 5.0 V, 100 kΩ output load resistance, Ta = 25 °C 1 0.1 ATT = 0dB 20kHz LPF THD + N(%) THD + N(%) f = 1kHz ATT = 0dB 20kHz LPF 0.1 0.01 VIN=0.2Vrms VIN=0.4Vrms 0.01 VIN=0.8Vrms VIN=1.2Vrms 0.001 0.1 1 0.001 2 VIN(Vrms) 20 100 1k Figure 3. THD + N vs. input amplitude 20k Figure 4. THD + N vs. input frequency 2 20 VIN = 1.2Vrms f = 1kHz 1 16 VIN = 0Vrms A-Weight Filter Noise (uV) 0 Error(dB) 10k Freq(Hz) −1 −2 12 8 −3 4 −4 −5 0 −10 −20 −30 −40 −50 −60 −70 0 −80 0 −10 −20 ATT(dB) −40 ATT=−40dB −60 ATT=−60dB −80 ATT=−80dB −60 −70 −80 −40 VIN = 1.2Vrms Cross Talk Gain(dB) Gain(dB) ATT=−20dB −50 Figure 6. Residual noise vs. ATT ATT=0dB −20 −40 ATT(dB) Figure 5. Attenuation error +0 −30 VIN = 1.2Vrms ATT = 0dB −60 −80 −100 −120 ATT=MUTE −100 −140 20 100 1k 10k Freq(Hz) Figure 7. Frequency response 100k 20 100 1k 10k 100k Freq(Hz) Figure 8. Crosstalk frequency response NIPPON PRECISION CIRCUITS—9 SM6451AV +0 100 VIN = 1.2Vrms = 0dB f = 1kHz ATT = 0dB BH window −40 −60 −80 −100 VIN = 1.2Vrms f = 1kHz ATT = 0dB 20kHz LPF 10 THD + N(%) FFT Gain(dB) −20 1 0.1 −120 0.01 −140 −160 0 2k 4k 6k 8k 10k 12k 14k 16k 18k 20k 0.001 1k Load resistance(Ω) Figure 9. FFT plot (ATT = 0 dB) Figure 10. THD + N vs. load resistance 10 AVDD + DVDD ADRS1=ADRS2=5V AVDD + DVDD ADRS1=ADRS2=5V Current consumption(mA) Current consumption(mA) 10 8 6 4 2 4.50 100k 10k Freq(Hz) 4.75 5.00 5.25 5.50 Supply volutage(V) Figure 11. Current consumption vs. supply voltage 8 6 4 2 −50 −25 0 25 50 75 100 Operating temperature(°C) Figure 12. Current consumption vs. temperature NIPPON PRECISION CIRCUITS—10 SM6451AV TYPICAL APPLICATIONS Connection Guidelines Decoupling capacitors of approximately 10 µF should be connected from AVDD, VRL, VRR to AVSS, and from DVDD to DVSS. In addition, approximately 0.01 µF capacitors should also be connected from AVDD, VRL, VRR to AVSS, and from DVDD to DVSS to suppress digital switch noise. An approximately 0.001 µF capacitor connected from RSTN to DVSS will force a system reset when power is applied. Connection 1 (to DAC) + 5V DVDD AVDD1 to 4 LOA LOBN SM5864 ROA ROBN DVSS DVDD Analog L.P.F. LIN Analog L.P.F. RIN AVDD for Front LOUT L ch OUT ROUT R ch OUT SM6451 AVSS1 to 4 ADRS1 DVSS ADRS2 AVSS MDT MCK MLEN CPU MDT MCK MLEN ADRS1 AVDD ADRS2 DVDD for Rear SM6451 LIN LOUT L ch OUT RIN ROUT R ch OUT AVSS DVSS NIPPON PRECISION CIRCUITS—11 SM6451AV Connection 2 R 3.3R 3.3R L ch Input LIN 4Vrms R L ch Output 1.2Vrms R R ch Input LOUT SM6451 3.3R 3.3R RIN ROUT R R ch Output The SM6451AV uses a 1.2 Vrms input reference amplitude. If the input signal is 4 Vrms, then the input must be reduced by a factor of 1/3.3, and the output increased by a factor of 3.3. Connection 3 AVDD L ch Input LIN LOUT L ch Output SM6451 R ch Input RIN ROUT R ch Output AVSS When there is a possibility that the input peak-to-peak amplitude will exceed the supply voltage, input protection diodes should be connected to prevent device breakdown. NIPPON PRECISION CIRCUITS INC. reserves the right to make changes to the products described in this data sheet in order to improve the design or performance and to supply the best possible products. Nippon Precision Circuits Inc. assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Nippon Precision Circuits Inc. makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification. The products described in this data sheet are not intended to use for the apparatus which influence human lives due to the failure or malfunction of the products. Customers are requested to comply with applicable laws and regulations in effect now and hereinafter, including compliance with export controls on the distribution or dissemination of the products. Customers shall not export, directly or indirectly, any products without first obtaining required licenses and approvals from appropriate government agencies. NIPPON PRECISION CIRCUITS INC. NIPPON PRECISION CIRCUITS INC. 4-3, Fukuzumi 2-chome Koto-ku, Tokyo 135-8430, Japan Telephone: 03-3642-6661 Facsimile: 03-3642-6698 NC9704AE 1998.06 NIPPON PRECISION CIRCUITS—12