SM6451B Audio Variable Volume IC OVERVIEW The SM6451B is a 3-wire serial-controlled electronic variable volume IC for audio applications. It provides electronic volume control for a stereo system (left and right channels), and independent channel attenuation and muting, with greatly enhanced digital zip noise suppression. The chip address function allows up to four SM6451B devices to be connected and individually controlled over the 3-wire control interface from a single CPU. It is available in 16-pin TSSOP packages. FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ PINOUT Stereo inputs and outputs Attenuation function • 2-channel independent control • 1.0dB/step over 80 steps • 0 to −80dB range Mute function 3-wire serial data control (MDT, MCK, MLEN) Chip addressing (up to 4 devices can be connected in parallel) Low noise • 0.003% THD + noise • 12µVrms residual noise 2.5 to 3.6V single power supply Silicon-gate CMOS process Package: 16-pin TSSOP (Pb free) RSTN 1 MDT 16 ADRS1 MCK ADRS2 MLEN DVDD DVSS LOUT ROUT LIN RIN AVDD VRL AVSS 8 9 VRR PACKAGE DIMENSIONS APPLICATIONS ■ (Top view) (Unit: mm) Weight: 0.07g Audio equipment ORDERING INFORMATION 5.30MAX 5.00 ± 0.08 1.00TYP 0.17 ± 0.05 0.44TYP 0.50 ± 0.10 16-pin TSSOP 6.40 ± 0.2 SM6451BT 4.40 ± 0.1 Package 0 to 8° 0.225TYP 0.65 0.10 + 0.08 0.22 − 0.07 + 0.03 0.07 − 0.04 + 0.03 1.07 − 0.09 Device 0.13 M SEIKO NPC CORPORATION —1 SM6451B BLOCK DIAGRAM DVDD DVSS Attenuation Control LIN LOUT 1/2VDD Reference Voltage Circuits ADRS1 ADRS2 VRL Attenuation Decoder Chip Address Decoder Interface Control MLEN MCK MDT RSTN VRR 1/2VDD Attenuation Control RIN AVDD ROUT AVSS PIN DESCRIPTION 1. Number Name I/O1 A/D1 1 RSTN Ip D System reset input (LOW-level reset) 2 ADRS1 Ip D Chip address set 1 3 ADRS2 Ip D Chip address set 2 4 DVDD – D Digital supply 5 LOUT O A Left-channel audio output 6 LIN I A Left-channel audio input 7 AVDD – A Analog supply 8 VRL O A Left-channel reference voltage (0.5VDD). Connect a 10µF capacitor between VRL and AVSS. 9 VRR O A Right-channel reference voltage (0.5VDD). Connect a 10µF capacitor between VRR and AVSS. 10 AVSS – A Analog ground 11 RIN I A Right-channel audio input 12 ROUT O A Right-channel audio output 13 DVSS – D Digital ground 14 MLEN Ip D Microcontroller latch enable input 15 MCK Ip D Microcontroller clock input 16 MDT Ip D Microcontroller data input Description Ip = input pin with pull-up, A = analog, D= digital SEIKO NPC CORPORATION —2 SM6451B SPECIFICATIONS Absolute Maximum Ratings DVSS = AVSS = 0V, DVDD = AVDD = VDD Parameter Symbol Rating Unit Supply voltage VDD −0.3 to 7.0 V Input voltage VIN VSS − 0.3 to VDD + 0.3 V Power dissipation PD 150 mW Storage temperature Tstg −55 to 125 °C Symbol Rating Unit VDD 2.5 to 3.6 V DVDD − AVDD, DVSS − AVSS ±0.1 V Topr −40 to 85 °C Note. Rating applies at power-ON and power-OFF. Recommended Operating Conditions DVSS = AVSS = 0V, DVDD = AVDD = VDD Parameter Supply voltage Supply voltage deviation Operating temperature DC Characteristics DVDD = AVDD = VDD = 2.5 to 3.6V, VSS = 0V, Ta = −40 to 85°C Rating Parameter DVDD Current consumption Symbol IDDD1 IDDD2 Condition Data transfer stopped, MDT, MCK, MLEN, RSTN, ADRS1, ADRS2 = VDD ADRS1 = ADRS2 = 0V, 0.8Vrms analog input, ATT = 0dB, data transfer active Unit min typ max – 0.2 1.0 µA – 0.4 1.0 mA – 1.9 5.5 mA AVDD Current consumption IDDA HIGH-level input voltage1 VIH 0.7VDD – – V LOW-level input voltage1 VIL – – 0.3VDD V Input current1 IIL VIN = 0V – 70 150 µA Input leakage current1 IIH VIN = VDD – – 1.0 µA 1. MDT, MCK, MLEN, RSTN, ADRS1, ADRS2 SEIKO NPC CORPORATION —3 SM6451B AC Digital Characteristics DVDD = AVDD = VDD = 2.5 to 3.6V, VSS = 0V, Ta = −40 to 85°C Serial inputs (MDT, MCK, MLEN) Rating Parameter Symbol Unit min typ max MCK, MLEN rise time tr – – 100 ns MCK, MLEN fall time tf – – 100 ns MCK pulse cycle tMCK 100 – 10000 ns MDT setup time tMDS 50 – – ns MDT hold time tMDH 50 – – ns MLEN setup time tMCS 50 – – ns MLEN hold time tMCH 50 – – ns MLEN LOW-level pulsewidth tMEWL 16 – – tMCK MLEN HIGH-level pulsewidth tMEWH 50 – 5000 ns 0.5VDD MDT tMDS tMDH MCK 0.5VDD tMCS tMCH MLEN 0.5VDD tMEWL tMEWH tf MCK MLEN tr 0.9VDD 0.9VDD 0.1VDD 0.5VDD 0.1VDD Reset input (RSTN) Rating Parameter RSTN LOW-level pulsewidth Symbol tRSTN Unit min typ max 100 – – ns SEIKO NPC CORPORATION —4 SM6451B AC Analog Characteristics VDD = 3.0V, 0.8Vrms amplitude, 1kHz input frequency, 100kΩ output load resistance, Ta = 25°C, AC-coupled inputs Analog inputs (LIN, RIN) Rating Parameter Symbol Condition Unit min typ max Reference input amplitude VAI – 0.8 – Vrms Input resistance RIN 40 50 60 kΩ Input clipping voltage VCLP – 1.1 – Vrms THD + N = 1%, ATT = 0dB Analog outputs (LOUT, ROUT) Rating Parameter Symbol Residual noise voltage VNS Signal-to-noise ratio SNR Total harmonic distortion + noise THD + N Condition Input signal: 0Vrms, A-weight filter, 0dBr = 0.8Vrms, ATT = 0dB ATT = 0dB, 20kHz lowpass filter Unit min typ max – 12 20 µVrms 92 96 – dBr – 0.0025 0.005 % Gain control range RCNT – 80 – 0 dB Step size Step 0.8 1.0 1.8 dB Attenuation error (1k to 20kHz) ERR1 0 to −60dB –2 – 1 dB ERR2 −61 to −80dB –6 – 0 dB AT0 ATT = 0dB – – 0.0 – dB AT2 ATT = −20dB – – 20.0 – dB AT4 ATT = −40dB – – 40.0 – dB AT6 ATT = −60dB – – 60.4 – dB AT8 ATT = −80dB – – 84.2 – dB Mute ATT = Mute – 85.0 – 88.0 – dB Channel crosstalk CT ATT = 0dB – 103 – 105 – dB Frequency response FR ATT = 0dB, f = 200kHz – 10 –8 – dB Quiescent output zip noise voltage (while ATT value adjusting) NJ 0Vrms input – – 3 mV Minimum driver load resistance RML ATT = 0dB, THD + N = 1% – 8 12 kΩ Symbol Condition Absolute attenuation (1kHz) Mute attenuation (1kHz) Reference voltage (VRL, VRR) Rating Parameter Reference voltage output VREF Unit min typ max 0.45VDD 0.5VDD 0.55VDD V SEIKO NPC CORPORATION —5 SM6451B MEASUREMENT CIRCUIT Chip address: ADRS1 = LOW, ADRS2 = LOW 0.001µF MDT 16 2 ADRS1 MCK 15 3 ADRS2 MLEN 14 4 DVDD DVSS 13 5 LOUT 0.022µF 6 LIN 7 AVDD + 10µF + 1µF 0.022µF + 8 VRL + 10µF 0.022µF SM6451 + 10µF 1 RSTN CPU ROUT 12 RIN 11 AVSS 10 VRR 9 0.022µF 1µF + 10µF + 1µF + 1µF 100kΩ 100kΩ Generator Analyzer Audio Precision System Two SYS − 2322A SEIKO NPC CORPORATION —6 SM6451B MICROCONTROLLER INTERFACE The SM6451B uses a 3-wire serial interface comprising MDT (data), MCK (clock) and MLEN (latch enable) to select channels and attenuation levels for the addressed device. Input Timing The microcontroller data input timing is shown in figure 1. MDT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 MCK MLEN Figure 1. Microcontroller data input timing Data is shifted into the internal shift register on the rising edge of MCK, and the attenuation value is updated on the rising edge of MLEN. Accordingly, data on MDT should be changed on the falling edge of MCK. Note, however, a minimum of 16 MCK input pulses are required. Data Format Channel Select Attenuation Data 7 Attenuation Data 6 Attenuation Data 5 Attenuation Data 4 Attenuation Data 3 Attenuation Data 2 Attenuation Data 1 Attenuation Data 0 D4 D3 D2 D1 D0 Don't Care D5 Don't Care D6 Chip Address 2 D7 Chip Address 1 D8 Don't Care D15 D14 D13 D12 D11 D10 D9 Don't Care MDT Channel Select The format of microcontroller input data is shown in figure 2. Figure 2. Microcontroller data format D15, D14 Don’t care. D13, D12 Chip address bits. D13 corresponds to ADRS1 and D12 corresponds to ADRS2. The device is addressed only when ADRS1:ADRS2 matches D13:D12. Example 1: If D13 = LOW, D12 = HIGH and ADRS1 = LOW, ADRS2 = LOW, then the device is not addressed since ADRS2 and D12 do not match. Example 2: If D13/D12 = LOW and ADRS1/ADRS2 = LOW, then the device is addressed and all input data is read and the attenuation settings updated. D11, D10 Don’t care. SEIKO NPC CORPORATION —7 SM6451B D9, D8 Channel select bits. The selected channel(s) are shown in table 1. Table 1. Channel select D9 D8 Selected channel LOW LOW Both left and right channels LOW HIGH Left channel HIGH LOW Right channel HIGH HIGH No change D7 to D0 Attenuation register (ATT) set bits. Table 2. Attenuation setting Attenuation 0 dB −1 dB −2 dB : −15 dB −16 dB −17 dB : −63 dB −64 dB −65 dB : −79 dB −80 dB Mute Mute : Mute Mute ATTH 00 01 02 : 0F 10 11 : 3F 40 41 : 4F 50 51 52 : FE FF D7 LOW LOW LOW : LOW LOW LOW : LOW LOW LOW : LOW LOW LOW LOW : HIGH HIGH D6 LOW LOW LOW : LOW LOW LOW : LOW HIGH HIGH : HIGH HIGH HIGH HIGH : HIGH HIGH D5 LOW LOW LOW : LOW LOW LOW : HIGH LOW LOW : LOW LOW LOW LOW : HIGH HIGH D4 LOW LOW LOW : LOW HIGH HIGH : HIGH LOW LOW : LOW HIGH HIGH HIGH : HIGH HIGH D3 LOW LOW LOW : HIGH LOW LOW : HIGH LOW LOW : HIGH LOW LOW LOW : HIGH HIGH D2 LOW LOW LOW : HIGH LOW LOW : HIGH LOW LOW : HIGH LOW LOW LOW : HIGH HIGH D1 LOW LOW HIGH : HIGH LOW LOW : HIGH LOW LOW : HIGH LOW LOW HIGH : HIGH HIGH D0 LOW HIGH LOW : HIGH LOW HIGH : HIGH LOW HIGH : HIGH LOW HIGH LOW : LOW HIGH Note. Outputs are muted after system reset. Attenuation error is changed dependent on the supply voltage when attenuation level is under – 60dB. In the case of the supply voltage being under 2.6V, mute level inverses up to the same level of – 80dB setting or more. (see Figure 6) SEIKO NPC CORPORATION —8 SM6451B ANALOG PERFORMANCE CHARACTERISTICS DVDD = AVDD = 3.0V, 100kΩ output load resistance, Ta = 25°C 0.1 1 ATT = 0dB 20kHz LPF 0.1 THD + N [%] THD + N [%] f = 1kHz ATT = 0dB 20kHz LPF VDD = 3.3V VDD = 3.0V VDD = 2.7V 0.01 VIN = 0.2Vrms 0.01 VIN = 0.5Vrms VIN = 0.8Vrms 0.001 .1 .2 1 .5 1.2 VIN [Vrms] 0.001 20 −68 0 Ideal Gain −72 Gain [dB] Error [dB] 20k −64 VIN = 0.8Vrms f = 1kHz 1 −1 −2 −76 VDD = 2.7V −84 −4 −88 0 −10 −20 −30 −40 −50 −60 −70 −92 −64 −80 VDD = 3V −80 −3 ATT [dB] VDD = 2.5V −68 −72 −76 −80 Mute ATT [dB] Figure 5. Attenuation error Figure 6. Attenuation characteristic (– 64dB to MUTE) +10 20 +0 VIN = 0Vrms A-Weight Filter −10 16 −20 Gain [dB] Residual Noise [µVrms] 10k Figure 4. THD + N vs. input frequency 2 12 8 −30 −40 4 −60 −80 −90 0 −10 −20 −30 −40 −50 −60 −70 ATT [dB] Figure 7. Residual noise vs. ATT −80 VIN = 0.8Vrms ATT = 0dB ATT = −20dB ATT = −40dB −50 −70 0 1k Frequency [Hz] Figure 3. THD + N vs. input amplitude −5 100 −100 20 ATT = −60dB ATT = −80dB ATT = MUTE 100 1k 10k 100k 200k Frequency [Hz] Figure 8. Frequency response SEIKO NPC CORPORATION —9 SM6451B −40 +0 −80 −100 −120 −140 VIN = 0.8Vrms = 0dBr f = 1kHz ATT = 0dB BH Window −20 VIN = 0.8Vrms ATT = 0dB FFT Spectrum [dBr] Cross Talk [dB] −60 −40 −60 −80 −100 −120 20 100 1k 10k −140 100k 200k 0 2k 4k Frequency [Hz] 8k 10k 12k 14k 16k 18k 20k Frequency [Hz] Figure 9. Crosstalk frequency response Figure 10. FFT spectrum 6 100 Current Consumption [mA] VIN = 0.8Vrms f = 1kHz ATT = 0dB 20kHz LPF 10 THD + N [%] 6k 1 0.1 0.01 0.001 1 10 Load Resistance [kΩ] 100 5 AVDD + DVDD ADRS1 = ADRS2 = 0V 4 3 2 1 0 2.4 2.7 3 3.3 3.6 Power Supply [V] Figure 11. THD + N vs. load resistance Figure 12. Current consumption vs. supply voltage Current Consumption [mA] 6 5 AVDD + DVDD ADRS1 = ADRS2 = 0V 4 3 VDD = 3.3V VDD = 3.0V 2 VDD = 2.7V 1 0 −50 −25 0 25 50 75 100 Operating Temperature [°C] Figure 13. Current consumption vs. operating temperature SEIKO NPC CORPORATION —10 SM6451B TYPICAL APPLICATIONS Connection Guidelines Decoupling capacitors of approximately 10µF should be connected from AVDD, VRL, VRR to AVSS, and from DVDD to DVSS. In addition, approximately 0.01µF capacitors should also be connected from AVDD, VRL, VRR to AVSS, and from DVDD to DVSS to suppress digital switch noise. An approximately 0.001µF capacitor connected from RSTN to DVSS will force a system reset when power is applied. Connection 1 (to DAC) CPU MDT MCK MLEN LPF LIN LOUT LPF RIN ROUT L-ch OUT DAC R-ch OUT SM6451 2.5 to 3.6V DVDD DVSS AVDD AVSS ADRS1 ADRS2 Connection 2 When there is a possibility that the input peak-to-peak amplitude will exceed the supply voltage, input protection diodes should be connected to prevent device breakdown. AVDD L-ch Input LIN LOUT L-ch Output SM6451 R-ch Input RIN ROUT R-ch Output AVSS SEIKO NPC CORPORATION —11 SM6451B Please pay your attention to the following points at time of using the products shown in this document. 1. The products shown in this catalog (hereinafter “Products”) are not designed and manufactured to be used for the apparatus that exerts harmful influence on the human lives due to the defects, failure or malfunction of the Products. If you wish to use the Products in that apparatus, please contact our sales section in advance. In the event that the Products are used in such apparatus without our prior approval, we assume no responsibility whatsoever for any damages resulting from the use of that apparatus. 2. NPC reserves the right to change the specifications of the Products in order to improve the characteristics or reliability thereof. 3. The information described in this catalog is presented only as a guide for using the Products. No responsibility is assumed by us for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of the third parties. Then, we assume no responsibility whatsoever for any damages resulting from that infringements. 4. The constant of each circuit shown in this catalog is described as an example, and it is not guaranteed about its value of the massproduction products. 5. In the case of that the Products in this catalog falls under the foreign exchange and foreign trade control law or other applicable laws and regulations, approval of the export to be based on those laws and regulations are necessary. Customers are requested appropriately take steps to obtain required permissions or approvals form appropriate government agencies. SEIKO NPC CORPORATION 1-9-9, Hatchobori, Chuo-ku, Tokyo 104-0032, Japan Telephone: +81-3-5541-6501 Facsimile: +81-3-5541-6510 http://www.npc.co.jp/ Email: [email protected] ND14017E00 2014.10 SEIKO NPC CORPORATION —12