TI SN55182

SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
1IN–
1RT
1IN+
1STRB
1RTC
1OUT
GND
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
2IN–
2RT
2IN+
2STRB
2RTC
2OUT
SN55182 . . . FK PACKAGE
(TOP VIEW)
1IN+
NC
1STRB
NC
1RTC
description
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2RT
NC
2IN+
NC
2STRB
1OUT
GND
NC
2OUT
2RTC
The SN55182 and SN75182 dual differential line
receivers are designed to sense small differential
signals in the presence of large common-mode
noise. These devices give TTL-compatible output
signals as a function of the polarity of the
differential input voltage. The frequency response
of each channel can be easily controlled by a
single external capacitor to provide immunity to
differential noise spikes. The output goes to a high
level when the inputs are open circuited. A strobe
input (STRB) is provided that, when in the low
level, disables the receiver and forces the output
to a high level.
1IN+
NC
V CC
2IN–
D
SN55182 . . . J OR W PACKAGE
SN75182 . . . N PACKAGE
(TOP VIEW)
Single 5-V Supply
Differential Line Operation
Dual Channels
TTL Compatibility
±15-V Common-Mode Input Voltage Range
±15-V Differential Input Voltage Range
Individual Channel Strobes
Built-In Optional Line-Termination Resistor
Individual Frequency Response Controls
Designed for Use With Dual Differential
Drivers SN55183 and SN75183
Designed to Be Interchangeable With
National Semiconductor DS7820A and
DS8820A
1RT
D
D
D
D
D
D
D
D
D
D
NC – No internal connection
THE SN55182 IS NOT RECOMMENDED
FOR NEW DESIGNS
The receiver is of monolithic single-chip construction, and both halves of the dual circuits use common
power-supply and ground terminals.
The SN55182 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN75182 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
STRB
OUTPUT
OUT
L
VID
X
H
H
H
H
L
L
H
H = VI ≥ VIH min or VID more
positive than VTH max
L = VI ≤ VIL max or VID more
negative than VTL max
X = irrelevant
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
logic symbol†
3
1IN+
&
1
1IN–
2
1RT
6
RT
4
1STRB
5
1RTC
1OUT
RESP
11
2IN+
13
2IN–
8
12
2RT
2OUT
10
2STRB
9
2RTC
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the J, N, and W packages.
logic diagram (positive logic)
1IN+
1IN–
1RT
1RTC
1STRB
2IN+
2IN–
2RT
2RTC
2STRB
3
6
1
5
4
11
8
13
12
9
10
Pin numbers shown are for the J, N, and W packages.
2
1OUT
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
2OUT
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
schematic (each receiver)
RTC
5, 9
14
VCC
167 Ω
3 kΩ
5 kΩ
1.5 kΩ
4.15 kΩ
5 kΩ
320 Ω
6, 8
1.5 kΩ
IN+
3, 11
170 Ω
RT
5 kΩ
1 kΩ
2, 12
1 kΩ
750 Ω
1 kΩ
167 Ω
ÁÁÁ
IN–
OUT
7
GND
167 Ω
1, 13
4, 10
5 kΩ
STRB
Resistor values shown are nominal.
Pin numbers shown are for the J, N, and W packages.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Common-mode input voltage, VIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V
Differential input voltage, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V
Strobe input voltage, VI(STRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V
Output sink current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or W package . . . . . . . . . . . . . . . . 300°C
Case temperature for 60 seconds, Tc: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential voltages, are with respect to network ground terminal.
2. Differential voltage values are at the noninverting terminal with respect to the inverting terminal.
DISSIPATION RATING TABLE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
1375 mW
11.0 mW/°C
880 mW
275 mW
1375 mW
11.0 mW/°C
880 mW
275 mW
N
1150 mW
9.2 mW/°C
736 mW
–
W‡
1000 mW
8.0 mW/°C
640 mW
200 mW
PACKAGE
FK‡
J‡
TA = 70°C
POWER RATING
TA = 125°C
POWER RATING
‡ In the FK, J, and W packages, SN55182 chips are alloy mounted.
recommended operating conditions
SN55182
Supply voltage, VCC
MIN
NOM
4.5
5
MIN
NOM
5.5
4.5
5
±15
Common-mode input voltage, VIC
High-level strobe input voltage, VIH(STRB)
Low-level strobe input voltage, VIL(STRB)
5.5
V
±15
V
V
5.5
2.1
5.5
0.9
0
0.9
V
–400
µA
16
mA
70
°C
Low-level output current, IOL
16
–55
POST OFFICE BOX 655303
UNIT
0
–400
Operating free-air temperature, TA
MAX
2.1
High-level output current, IOH
4
SN75182
MAX
• DALLAS, TEXAS 75265
125
0
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
electrical characteristics over recommended ranges of VCC, VIC, and operating free-air
temperature (unless otherwise noted)
TEST CONDITIONS†
PARAMETER
MIN
TYP‡
MAX
VIT
IT+
Positive going input threshold voltage
Positive-going
VO = 2.5 V,,
IOH = –400 µA
VIC = –3 V to 3 V
VIC = –15 V to 15 V
0.5
VIT
IT–
Negative going input threshold voltage
Negative-going
VO = 0.4 V,,
IOL = 16 mA
VIC = –3 V to 3 V
VIC = –15 V to 15 V
–0.5
VOH
High level output voltage
High-level
VOL
Low level output voltage
Low-level
Input current
Noninverting input
IIH(STRB)
IIL(STRB)
High-level strobe input current
ri
Input resistance
ICC
VID = 1 V
V, V(STRB) = 2
2.1
1V
V, IOH = –400
400 µA
25
2.5
42
4.2
55
5.5
VID = –1
1V
V, V(STRB) = 0
0.4
4V
V, IOH = –400
400 µA
25
2.5
42
4.2
55
5.5
0 25
0.25
04
0.4
V
V
V
V
VIC = 15 V
VIC = 0
3
4.2
0
–0.5
VIC = –15 V
VIC = 15 V
–3
–4.2
5
7
VIC = 0
VIC = –15 V
–1
–1.4
–7
–9.8
5
µA
–1
–1.4
mA
V(STRB) = 5.5 V
V(STRB) = 0
Low-level strobe input current
mA
Inverting input
3.6
5
Noninverting input
1.8
2.5
120
170
250
Ω
–2.8
–4.5
–6.7
mA
4.2
6
6.8
10.2
9.4
14
TYP
MAX
Line-terminating resistance
IOS
–1
1V
1V
VID = –1
V, V(STRB) = 2
2.1
V, IOL = 16 mA
Inverting input
II
1
UNIT
Short-circuit output current
TA = 25°C
VCC = 5.5 V,
Supply current (average per receiver)
VIC = 15 V,
VIC = 0,
VO = 0
VID = –1 V
VID = –0.5 V
VID = –1 V
VIC = –15 V,
† Unless otherwise noted, V(STRB) ≥ 2.1 V or open.
‡ All typical values are at VCC = 5 V, VIC = 0, and TA = 25°C.
kΩ
mA
switching characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
MIN
UNIT
tPLH(D)
Propagation delay time,
low- to high-level output from differential input
RL = 400 Ω,
CL = 15 pF,
see Figure 1
18
40
ns
tPHL(D)
Propagation delay time,
high- to low-level output from differential input
RL = 400 Ω,
CL = 15 pF,
see Figure 1
31
45
ns
tPLH(S)
Propagation delay time,
low- to high-level output from STRB input
RL = 400 Ω,
CL = 15 pF,
see Figure 1
9
30
ns
tPHL(S)
Propagation delay time,
high- to low-level output from STRB input
RL = 400 Ω,
CL = 15 pF,
see Figure 1
15
25
ns
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
Output
Input
VCC = 5 V
Pulse
Generator No. 1
(see Note A)
400 Ω
See Note C
50 Ω
CL = 15 pF
(see Note B)
Pulse
Generator No. 2
(see Note A)
50 Ω
Strobe
Input
TEST CIRCUIT
tw
2.5 V
Input
0V
0V
0V
0V
–2.5 V
tw
>100 ns
>100 ns
>100 ns
>100 ns
2.6 V
STRB
1.3 V
1.3 V
1.3 V
1.3 V
0V
tPHL(D)
tPLH(D)
tPHL(S)
tPLH(S)
VOH
Output
1.3 V
1.3 V
1.3 V
1.3 V
VOL
VOLTAGE WAVEFORMS
NOTES: A. The pulse generators have the following characteristics: ZO = 50 Ω, tr ≤ 10 ns, tf ≤ 10 ns, tw = 0.5 ±0.1 µs, PRR ≤ 1 MHz.
B. CL includes probe and jig capacitance.
C. All diodes are 1N3064 or equivalent.
Figure 1. Test Circuit and Voltage Waveforms
6
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• DALLAS, TEXAS 75265
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS†
DIFFERENTIAL INPUT THRESHOLD VOLTAGE
vs
COMMON-MODE INPUT VOLTAGE
DIFFERENTIAL INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
0.5
VIC = 0
TA = 25°C
VVID
ID – Differential Input Threshold Voltage – V
VVID
ID – Differential Input Threshold Voltage – V
0.3
0.2
0.1
VO = 2.5 V, IO = –400 µA
0
–0.1
VO = 0.4 V, IO = 16 mA
–0.2
–0.3
4.5
5
5.5
VCC – Supply Voltage – V
0.4
0.3
0.2
VO = 2.5 V, IO = –400 µA
0.1
0
VO = 0.4 V, IO = 16 mA
–0.1
–0.2
–0.3
–0.4
–0.5
–20
6
VCC = 5 V
TA = 25°C
–15
–10 –5
0
5
10
15
VIC – Common-Mode Input Voltage – V
Figure 2
20
Figure 3
DIFFERENTIAL INPUT THRESHOLD VOLTAGE
vs
FREE-AIR TEMPERATURE
V
VID
ID – Differential Input Threshold Voltage – V
100
VO = 2.5 V, IO = –400 µA
50
0
–50
VO = 0.4 V, IO = 16 mA
–100
–150
VCC = 5 V
VIC = 0
–200
–75
–50
–25
0
25
50
75
100
125
TA – Free-Air Temperature – °C
Figure 4
† Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS†
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VOLTAGE TRANSFER CHARACTERISTICS
5
5
VCC = 5 V
VIC = 0
VCC = 5 V
TA = 25°C
5V
4
VID = 0.5 V, IO = –400 µA
V
VO
O – Output Voltage – V
V
VO
O – Output Voltage – V
4
3
2
400 Ω
From Output
Under Test
4 Each
1N3064
10 kΩ
3
TA = –55°C
TA = 125°C
2
1
1
VID = –0.5 V, IOL = 16 mA
0
–75
–50
–25
0
25
50
75
100
0
–0.5 –0.4 –0.3 –0.2 –0.1
125
TA – Free-Air Temperature – °C
0.3 0.4 0.5
Figure 6
TERMINATING RESISTANCE
vs
FREE-AIR TEMPERATURE
INPUT CURRENT
vs
INPUT VOLTAGE
200
10
VCC = 5 V
VID = 0 to ±20 V
TA = 25°C
Terminating Resistance – Ω
6
IIII – Input Current – mA
0.1 0.2
VID – Differential Input Voltage – V
Figure 5
8
0
4
2
IN–
0
–2
–4
IN+
190
180
170
160
–6
–8
–10
–20
–15
–10
–5
5
0
10
VI – Input Voltage – V
15
20
150
–75
–50
–25
0
25
50
75
100
125
TA – Free-Air Temperature – °C
Figure 8
Figure 7
† Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS†
SUPPLY CURRENT
(AVERAGE PER RECEIVER)
vs
COMMON-MODE INPUT VOLTAGE
POWER DISSIPATION
(AVERAGE PER RECEIVER)
vs
COMMON-MODE INPUT VOLTAGE
12
300
250
PD
PD – Power Dissipation – mW
IICC
CC – Supply Current – mA
10
VID = –1 V
8
6
VID = 1 V
4
2
0
–20
VCC = 5 V
VID = –1 V
VCC = 5 V
No Load
TA = 25°C
–15
–10
Max Rated PD at TA = 125°C
(W Package )
200
150
TA = 25°C
100
50
TA = 125°C
–5
0
5
10
15
20
VIC – Common-Mode Input Voltage – V
0
–20
–15
–10
–5
0
5
10
15
20
VIC – Common-Mode Input Voltage – V
Figure 9
Figure 10
† Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
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• DALLAS, TEXAS 75265
9
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS†
MAXIMUM NOISE PULSE DURATION
vs
MAXIMUM RESPONSE TIME-CONTROL CAPACITANCE
tw – Maximum Noise Pulse Duration – ns
tw
1000
VCC = 5 V
TA = 25°C
See Note A
700
400
200
2.5 V
0V
100
– 2.5 V
70
tw
40
INPUT PULSE
20
10
10
40
100
400
1000
4000
10000
Response Time Control Capacitance – pF
NOTE A: Figure 11 shows the maximum duration of the illustrated pulse that can be applied differently without the output changing from the
low to high level.
Figure 11
† Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
10
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
PROPAGATION DELAY TIME
FROM DIFFERENTIAL INPUT
vs
FREE-AIR TEMPERATURE
38
36
VCC = 5 V
See Figure 1
34
tPHL(D)
32
30
28
26
24
22
20
tPLH(D)
18
16
14
–75
–50
–25
0
25
50
75
100
TA – Free-Air Temperature – °C
125
t P(S) – Propagation Delay Time From Strobe Input – ns
t P(D) – Propagation Delay Time From Differential Input – ns
TYPICAL CHARACTERISTICS†
PROPAGATION DELAY TIME
FROM STROBE INPUT
vs
FREE-AIR TEMPERATURE
20
18
VCC = 5 V
See Figure 1
tPHL(S)
16
14
12
tPLH(S)
10
8
6
4
–75
–50
–25
0
25
50
75
100
125
TA – Free-Air Temperature – °C
Figure 13
Figure 12
† Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
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• DALLAS, TEXAS 75265
11
SN55182, SN75182
DUAL DIFFERENTIAL LINE RECEIVERS
SLLS092D – OCTOBER 1972 – REVISED APRIL 1998
APPLICATION INFORMATION
VCC = 5 V
VCC = 5 V
1/2 ’183
Inputs
1/2 ’182
A
B
C
D
Z
IN–
0.002 µF
(see Note A)
OUT
RT
RTC
Y
100 pF
(see Note B)
IN+
Twisted
Pair
STRB
GND
GND
NOTES: A. When the inputs are open circuited, the output is high. A capacitor may be used for dc isolation of the line-terminating resistor.
At the frequency of operation, the impedance of the capacitor should be relatively small.
Example: let f = 5 MHz
C = 0.002 µF
1
1
Z (C)
2 fC
2 5 10 6 0.002
Z (C)
16
+
[
p + pǒ
W
Ǔǒ
10 *6
Ǔ
B. Use of a capacitor to control response time is optional.
Figure 14. Transmission of Digital Data Over Twisted-Pair Line
12
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PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
5962-7900801VDA
ACTIVE
CFP
W
14
25
TBD
A42
N / A for Pkg Type
Call TI
SN55182J
OBSOLETE
CDIP
J
14
SN75182D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75182DE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75182DG4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75182DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75182DRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75182DRG4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75182N
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
CU NIPDAU N / A for Pkg Type
Call TI
CU NIPDAU N / A for Pkg Type
SN75182NE4
ACTIVE
PDIP
N
14
25
Pb-Free (RoHS)
SN75182NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75182NSRE4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SN75182NSRG4
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
SNJ55182FK
OBSOLETE
LCCC
FK
20
TBD
Call TI
Call TI
SNJ55182J
OBSOLETE
CDIP
J
14
TBD
Call TI
Call TI
SNJ55182W
OBSOLETE
CFP
W
14
TBD
Call TI
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
(Requires Login)
5962-7900801VCA
TBD
(3)
PACKAGE OPTION ADDENDUM
www.ti.com
28-Aug-2012
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN55182, SN55182-SP, SN75182 :
• Catalog: SN75182, SN55182
• Military: SN55182
• Space: SN55182-SP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN75182DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN75182NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN75182DR
SN75182NSR
SOIC
D
14
2500
367.0
367.0
38.0
SO
NS
14
2000
367.0
367.0
38.0
Pack Materials-Page 2
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