SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS
FEATURES
•
•
•
•
•
•
•
•
•
•
Receiver and Drivers Meet or Exceed the
Requirements of ANSI EIA/TIA-644 Standard
– SN65LVDS105 Receives Low-Voltage TTL
(LVTTL) Levels
– SN65LVDS104 Receives Differential Input
Levels, ±100 mV
Typical Data Signaling Rates to 400 Mbps or
Clock Frequencies to 400 MHz
Operates From a Single 3.3-V Supply
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and a 100-Ω
Load
Propagation Delay Time
– SN65LVDS105 – 2.2 ns (Typ)
– SN65LVDS104 – 3.1 ns (Typ)
LVTTL Levels Are 5-V Tolerant
Electrically Compatible With LVDS, PECL,
LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT,
SSTL, or HSTL Outputs With External
Networks
Driver Outputs Are High Impedance When
Disabled or With VCC <1.5 V
Bus-Pin ESD Protection Exceeds 16 kV
SOIC and TSSOP Packaging
DESCRIPTION
The SN65LVDS104 and SN65LVDS105 are a differential line receiver and a LVTTL input (respectively)
connected to four differential line drivers that implement the electrical characteristics of low-voltage
differential signaling (LVDS). LVDS, as specified in
EIA/TIA-644 is a data signaling technique that offers
low-power, low-noise coupling, and switching speeds
to transmit data at relatively long distances. (Note:
The ultimate rate and distance of data transfer is
dependent upon the attenuation characteristics of the
media, the noise coupling to the environment, and
other system characteristics.)
SN65LVDS104
D OR PW PACKAGE
(Marked as LVDS104)
(TOP VIEW)
EN1
EN2
EN3
VCC
GND
A
B
EN4
16
1
2
15
3
14
4
13
5
12
11
6
7
10
8
9
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
SN65LVDS105
D OR PW PACKAGE
(Marked as LVDS105)
(TOP VIEW)
EN1
EN2
EN3
VCC
GND
A
NC
EN4
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
logic diagram (positive logic)
’LVDS104
1Y
EN1
EN2
1Z
2Y
2Z
EN3
3Y
A
B
3Z
4Y
EN4
4Z
’LVDS105
1Y
EN1
EN2
1Z
2Y
2Z
EN3
3Y
A
3Z
4Y
EN4
4Z
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. Having the drivers integrated into the same substrate, along with the low pulse
skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input.
This is particularly advantageous in distribution or expansion of signals such as clock or serial data stream.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2005, Texas Instruments Incorporated
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The SN65LVDS104 and SN65LVDS105 are characterized for operation from –40°C to 85°C.
The SN65LVDS104 and SN65LVDS105 are members of a family of LVDS repeaters. A brief overview of the
family is provided in the table below.
Selection Guide to LVDS Repeaters
NO. INPUTS
NO. OUTPUTS
SN65LVDS22
DEVICE
2 LVDS
2 LVDS
PACKAGE
16-pin D
Dual multiplexed LVDS repeater
COMMENT
SN65LVDS104
1 LVDS
4 LVDS
16-pin D
4-Port LVDS repeater
SN65LVDS105
1 LVTTL
4 LVDS
16-pin D
4-Port TTL-to-LVDS repeater
SN65LVDS108
1 LVDS
8 LVDS
38-pin DBT
8-Port LVDS repeater
SN65LVDS109
2 LVDS
8 LVDS
38-pin DBT
Dual 4-port LVDS repeater
SN65LVDS116
1 LVDS
16 LVDS
64-pin DGG
16-Port LVDS repeater
SN65LVDS117
2 LVDS
16 LVDS
64-pin DGG
Dual 8-port LVDS repeater
Function Tables (1)
SN65LVDS104
SN65LVDS105
INPUT
OUTPUT
INPUT
VID = VA - VB
xEN
xY
xZ
X
X
Z
X
L
Z
VID ≥ 100 mV
H
–100 mV < VID < 100 mV
VID ≤ –100 mV
(1)
OUTPUT
A
ENx
xY
xZ
Z
L
Z
H
H
L
H
H
H
H
L
L
Open
H
L
H
H
?
?
X
L
Z
Z
H
L
H
X
X
Z
Z
H = high level, L = low level, Z = high impedance, ? = indeterminate, X = don't care
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
VCC
300 kΩ
300 kΩ
EN and
A (’LVDS105)
Input
A
Input
B
Input
50 Ω
10 kΩ
7V
300 kΩ
7V
2
7V
5Ω
Y or Z
Output
7V
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
UNIT
(2)
Supply voltage range, VCC
–0.5 to 4 V
Enables, A ('LVDS105)
Voltage range
–0.5 to 6 V
A, B, Y or Z
Electrostatic discharge (3)
–0.5 to 4 V
A, B, Y, Z, and GND
Class 3, A:16 kV, B: 400 V
Continuous power dissipation
See Dissipation Rating Table
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
(3)
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with MIL-STD-883C Method 3015.7
DISSIPATION RATING TABLE
(1)
PACKAGE
TA≤ 25°C
POWER RATING
OPERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
D
950 mW
7.6 mW/°C
494 mW
PW
774 mW
6.2 mW/°C
402 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and
with no air flow.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
3.3
3.6
VCC
Supply voltage
3
VIH
High-level input voltage
2
VIL
Low-level input voltage
VI or VIC
Voltage at any bus terminal (separately or common-mode)
TA
Operating free-air temperature
UNIT
V
V
0.8
0
VCC–0.8
–40
85
V
°C
3
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
SN65LVDS104 ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
VIT+
Positive-going differential input voltage threshold
VIT-
Negative-going differential input voltage threshold
|VOD|
Differential output voltage magnitude
∆|VOD|
Change in differential output voltage magnitude between logic
states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output voltage between logic states
VOC(PP)
Peak-to-peak common-mode output voltage
ICC
Supply current
TEST CONDITIONS
See Figure 1 and Table 1
RL = 100 Ω, VID = ± 100 mV,
See Figure 1 and Figure 2
See Figure 3
MIN
MAX UNIT
100
–100
247
340
mV
454
mV
–50
50
1.125
1.375
–50
50
mV
25
150
mV
23
35
mA
3
8
mA
–2
–11
–20
–1.2
–3
Enabled, RL = 100 Ω
Disabled
VI = 0 V
TYP (1)
V
II
Input current (A or B inputs)
II(OFF)
Power-off Input current
VCC = 1.5 V, VI = 2.4 V
20
µA
IIH
High-level input current (enables)
VIH = 2 V
20
µA
IIL
Low-level input current (enables)
VIL = 0.8 V
VI = 2.4 V
µA
10
µA
VOY or VOZ = 0 V
±10
mA
VOD = 0 V
±10
mA
±1
µA
±1
µA
IOS
Short-circuit output current
IOZ
High-impedance output current
VO = 0 V or 2.4 V
IO(OFF)
Power-off output current
VCC = 1.5 V, VO = 2.4 V
CIN
Input capacitance (A or B inputs)
VI = 0.4 sin (4E6πt) + 0.5 V
3
pF
Output capacitance (Y or Z outputs)
VI = 0.4 sin (4E6πt) + 0.5 V,
Disabled
9.4
pF
CO
(1)
All typical values are at 25°C and with a 3.3-V supply.
SN65LVDS104 SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP (1) MAX UNIT
tPLH
Propagation delay time, low-to-high-level output
2.4
3.2
4.2
ns
tPHL
Propagation delay time, high-to-low-level output
2.2
3.1
4.2
ns
tr
Differential output signal rise time
0.3
0.8
1.2
ns
tf
Differential output signal fall time
0.3
0.8
1.2
ns
tsk(p)
Pulse skew (|tPHL - tPLH|)
150
500
ps
20
100
ps
1.5
ns
RL = 100 Ω, CL = 10 pF,
See Figure 4
skew (2)
tsk(o)
Channel-to-channel output
tsk(pp)
Part-to-part skew (3)
tPZH
Propagation delay time, high-impedance-to-high-level output
7.2
15
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
8.4
15
ns
tPHZ
Propagation delay time, high-level-to-high-impedance output
3.6
15
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
6
15
ns
(1)
(2)
(3)
4
See Figure 5
All typical values are at 25°C and with a 3.3-V supply.
tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected
together.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
SN65LVDS105 ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
|VOD|
Differential output voltage magnitude
∆|VOD|
Change in differential output voltage magnitude between logic
states
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output voltage between
logic states
VOC(PP)
Peak-to-peak common-mode output voltage
TEST CONDITIONS
RL = 100 Ω,
VID = ±100 mV,
See Figure 6 and Figure 7
See Figure 8
MIN TYP (1) MAX UNIT
247
340
454
mV
–50
50
1.125
1.37
5
–50
50
mV
V
25
150
mV
Enabled, RL = 100 Ω
23
35
mA
Disabled
0.7
ICC
Supply current
6.4
mA
IIH
High-level input current
VIH = 2 V
20
µA
IIL
Low-level input current
VIL = 0.8 V
10
µA
IOS
Short-circuit output current
VOY or VOZ = 0 V
±10
mA
VOD = 0 V
±10
mA
IOZ
High-impedance output current
VO = 0 V or 2.4 V
±1
µA
IO(OFF)
Power-off output current
VCC = 1.5 V, VO = 2.4 V
±1
µA
CIN
Input capacitance
VI = 0.4 sin (4E6πt) + 0.5 V
5
pF
Output capacitance (Y or Z outputs)
VI = 0.4 sin (4E6πt) + 0.5 V,
Disabled
9.4
pF
CO
(1)
0.3
All typical values are at 25°C and with a 3.3-V supply.
SN65LVDS105 SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1) MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
1.7
2.2
3
ns
tPHL
Propagation delay time, high-to-low-level output
1.4
2.3
3.5
ns
tr
Differential output signal rise time
0.3
0.8
1.2
ns
tf
Differential output signal fall time
tsk(p)
Pulse skew (|tPHL - tPLH|)
tsk(o)
Channel-to-channel output skew (2)
RL = 100 Ω, CL = 10 pF,
See Figure 9
0.3
0.8
1.2
ns
150
500
ps
20
100
ps
skew (3)
tsk(pp)
Part-to-part
1.5
ns
tPZH
Propagation delay time, high-impedance-to-high-level output
7.2
15
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
8.4
15
ns
tPHZ
Propagation delay time, high-level-to-high-impedance output
3.6
15
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
6
15
ns
(1)
(2)
(3)
See Figure 10
All typical values are at 25°C and with a 3.3-V supply.
tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected
together.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
5
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
PARAMETER MEASUREMENT INFORMATION
II
IOY
A
Y
IIB
VID
VOD
IOZ
V
VOY
Z
VIA
B
OY
V
OZ
2
VOC
VIB
VOZ
Figure 1. 'LVDS104 Voltage and Current Definitions
Table 1. SN65LVDS104 Minimum and Maximum Input Threshold Test Voltages
RESULTING
DIFFERENTIAL
INPUT VOLTAGE
APPLIED
VOLTAGES
RESULTING
COMMON-MODE
INPUT VOLTAGE
VIA
VIB
VID
VIC
1.25 V
1.15 V
100 mV
1.2 V
1.15 V
1.25 V
–100 mV
1.2 V
2.4 V
2.3 V
100 mV
2.35 V
2.3 V
2.4 V
–100 mV
2.35 V
0.1 V
0V
100 mV
0.05 V
0V
0.1 V
–100 mV
0.05 V
1.5 V
0.9 V
600 mV
1.2 V
0.9 V
1.5 V
–600 mV
1.2 V
2.4 V
1.8 V
600 mV
2.1 V
1.8 V
2.4 V
–600 mV
2.1 V
0.6 V
0V
600 mV
0.3 V
0V
0.6 V
–600 mV
0.3 V
3.75 kΩ
Y
VOD
Input
Z
100 Ω
3.75 kΩ
±
Figure 2. 'LVDS104 VOD Test Circuit
6
0 V ≤ VTEST ≤ 2.4 V
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
49.9 Ω ± 1% (2 Places)
Y
Input
(see Note A)
VI
1.4 V
VI
1V
Z
VOC(PP)
CL = 10 pF
(2 Places)
(see Note B)
VOC
VOC(SS)
VO
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns.
B.
CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP) is made
on test equipment with a –3 dB bandwidth of at least 300 MHz.
Figure 3. 'LVDS104 Test Circuit and Definitions for the Driver Common-Mode Output Voltage
A
Y
B
Z
Input
(see Note A)
1.4 V
1.2 V
1V
VIB
Input
VIA
tPLH
VOD
tPHL
100%
80%
100 Ω ± 1%
VOD(H)
Output
CL = 10 pF
(2 Places)
(see Note B)
0V
VOD(L)
20%
0%
tf
tr
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulsewidth = 10 ± 0.2 ns.
B.
CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 4. 'LVDS104 Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
7
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
49.9 Ω ± 1% (2 Places)
Y
1 V or 1.4 V
Input
(see Note A)
Z
1.2 V
1.2 V
EN
CL = 10 pF
(2 Places)
(see Note B)
VOY
VOZ
3V
1.5 V
0V
EN
tPZH
tPHZ
≅ 1.4 V
1.25 V
1.2 V
VOY or VOZ
tPZL
tPLZ
1.2 V
1.15 V
≅1V
VOZ or VOY
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns.
B.
CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 5. 'LVDS104 Enable and Disable Time Circuit and Definitions
IOY
II
Y
A
IOZ
VOD
V
VOY
Z
OY
V
OZ
2
VOC
VIA
VOZ
Figure 6. 'LVDS105 Voltage and Current Definitions
3.75 kΩ
Y
VOD
Input
Z
100 Ω
3.75 kΩ
±
Figure 7. 'LVDS105 VOD Test Circuit
8
0 V ≤ VTEST ≤ 2.4 V
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
49.9 Ω ± 1% (2 Places)
3V
Y
Input
(see Note A)
A
0V
Z
VOC(PP)
VOC
CL = 10 pF
(2 Places)
(see Note B)
VOC(SS)
VO
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns.
B.
CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP) is made
on test equipment with a -3 dB bandwidth of at least 300 MHz.
Figure 8. 'LVDS105 Test Circuit and Definitions for the Driver Common-Mode Output Voltage
Y
Input
(see Note A)
Z
3V
1.5 V
0V
Input
VIA
tPLH
VOD
tPHL
100 Ω ± 1%
100%
80%
Output
CL = 10 pF
(2 Places)
(see Note B)
VOD(H)
0V
VOD(L)
20%
0%
tf
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulsewidth = 10 ± 0.2 ns.
B.
CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
tr
Figure 9. 'LVDS105 Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
9
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
Y
49.9 Ω ± 1% (2 Places)
0.8 V or 2 V
Z
Input
(see Note A)
1.2 V
EN
CL = 10 pF
(2 Places)
(see Note B)
VOY
VOZ
3V
1.5 V
0V
EN
tPZH
tPHZ
VOY
or
VOZ
≅ 1.4 V
1.25 V
1.2 V
tPZL
tPLZ
VOZ
or
VOY
1.2 V
1.15 V
≅1V
A.
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulsewidth = 500 ± 10 ns.
B.
CL includes instrumentation and fixture capacitance within 0,06 m of the D.U.T.
Figure 10. 'LVDS105 Enable and Disable Time Circuit and Definitions
10
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
TYPICAL CHARACTERISTIC
SN65LVDS104
SUPPLY CURRENT
vs
FREQUENCY
SN65LVDS105
SUPPLY CURRENT
vs
FREQUENCY
60
50
45
I CC − Supply Current − mA
I CC − Supply Current − mA
55
50
VCC = 3.6 V
45
VCC = 3 V
40
35
VCC = 3.3 V
40
VCC = 3.6 V
35
VCC = 3 V
30
VCC = 3.3 V
25
30
All Outputs Loaded
and Enabled
25
50
100
150
200
250
300
All Outputs Loaded
and Enabled
20
350
50
100
150
f − Frequency − MHz
250
300
Figure 11.
Figure 12.
DRIVER
LOW-LEVEL OUTPUT VOLTGE
vs
LOW-LEVEL OUTPUT CURRENT
DRIVER
HIGH-LEVEL OUTPUT VOLTGE
vs
HIGH-LEVEL OUTPUT CURRENT
350
3.5
4
VCC = 3.3 V
TA = 25°C
VOH − High-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
200
f − Frequency − MHz
3
2
1
VCC = 3.3 V
TA = 25°C
3
2.5
2
1.5
1
0.5
0
0
0
2
4
IOL − Low-Level Output Current − mA
Figure 13.
6
−4
−3
−2
−1
0
IOH − High-Level Output Current − mA
Figure 14.
11
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
TYPICAL CHARACTERISTIC (continued)
SN65LVDS104
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
3.6
t PHL − High-To-Low Propagation Delay Time − ns
t PLH − Low-To-High Propagation Delay Time − ns
SN65LVDS104
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
3.5
3.4
VCC = 3.3 V
3.3
3.2
VCC = 3 V
3.1
VCC = 3.6 V
3.0
2.9
2.8
−50
−25
0
25
50
75
100
3.6
3.5
3.4
3.3
VCC = 3 V
3.2
VCC = 3.3 V
3.1
VCC = 3.6 V
3.0
2.9
2.8
−50
0
25
50
75
Figure 15.
Figure 16.
SN65LVDS105
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
SN65LVDS105
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
2.7
2.6
2.5
2.4
VCC = 3 V
2.3
2.2
VCC = 3.3 V
2.1
2.0
−50
VCC = 3.6 V
−25
0
25
50
TA − Free-Air Temperature − °C
Figure 17.
12
−25
100
TA − Free-Air Temperature − °C
t PHL − High-To-Low Propagation Delay Time − ns
t PLH − Low-To-High Propagation Delay Time − ns
TA − Free-Air Temperature − °C
75
100
2.7
2.6
2.5
VCC = 3 V
2.4
2.3
VCC = 3.3 V
2.2
VCC = 3.6 V
2.1
2.0
−50
−25
0
25
50
TA − Free-Air Temperature − °C
Figure 18.
75
100
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
TYPICAL CHARACTERISTIC (continued)
SN65LVDS104 P-P EYE-PATTERN JITTER
vs
PRBS SIGNALING RATE
800
TA = 25C
700
Peak-to-Peak Jitter − ps
VCC = 3.6 V
600
500
VCC = 3 V
400
300
200
100
0
0
100
200
300
400
500
600
Signaling Rate − Mbps
NOTES: Input: 215 PRBS with peak-to-peak jitter <115 ps at 100 Mbps. Test board adds about 70 ps p-p jitter. All outputs
enabled and loaded with differential 100-Ω loads, worst-case output, supply decoupled with 0.1-µF ceramic 0603-style
capacitors 1 cm from the device.
Figure 19.
SN65LVDS104 P-P PERIOD JITTER
vs
CLOCK FREQUENCY
18
TA = 25C
16
VCC = 3 V
Peak-to-Peak Jitter − ps
14
12
10
VCC = 3.6 V
8
6
4
2
0
0
100
200
300
400
500
Clock Frequency − MHz
600
NOTES: Input: 50% duty cycle square wave with period jitter < 9 ps at 100 MHz. Test board adds about 5 ps p-p jitter. All
outputs enabled and loaded with differential 100-Ω loads, worst-case output, supply decoupled with 0.1-µF and
0.001-µF ceramic 0603-style capacitors 1 cm from the device.
Figure 20.
13
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
TYPICAL CHARACTERISTIC (continued)
SN65LVDS105 P-P EYE-PATTERN JITTER
vs
PRBS SIGNALING RATE
600
TA = 25C
VCC = 3.6 V
Peak-to-Peak Jitter − ps
500
VCC = 3 V
400
300
200
100
0
0
100
200
300
400
500
600
Signaling Rate − Mbps
NOTES: Input: 215 PRBS with peak-to-peak Jitter < 147 ps at 100 Mbps, Test board adds about 43 ps p-p jitter. All outputs
enabled and loaded with differential 100-Ω loads, worst-case output, supply decoupled with 0.1-µF and 0.001-µF
ceramic 0603-style capacitors 1 cm from the device.
Figure 21.
SN65LVDS105 P-P PERIOD JITTER
vs
CLOCK FREQUENCY
14
TA = 25C
Peak-to-Peak Jitter − ps
12
VCC = 3.6 V
10
8
6
VCC = 3 V
4
2
0
0
100
200
300
400
500
Clock Frequency − MHz
600
NOTES: Input: 50% duty cycle square wave with period jitter < 10 ps at 100 MHz. Test board adds about 5 ps p-p jitter. All
outputs enabled and loaded with differential 100-Ω loads, worst-case output, supply decoupled with 0.1-µF and
0.001-µF ceramic 0603-style capacitors 1 cm from the device.
Figure 22.
14
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
APPLICATION INFORMATION
INPUT LEVEL TRANSLATION
An LVDS receiver can be used to receive various other types of logic signals. Figure 23 through Figure 32 show
the termination circuits for SSTL, HSTL, GTL, BTL, LVPECL, PECL, CMOS, and TTL.
VDD
25 Ω
50 Ω
A
1/2 VDD
50
Ω
B
0.1 µF
LVDS Receiver
Figure 23. Stub-Series Terminated (SSTL) or High-Speed Transceiver Logic (HSTL)
VDD
50 Ω
A
50 Ω
B
1.35 V < VTT < 1.65 V
0.1 µF
LVDS Receiver
Figure 24. Center-Tap Termination (CTT)
1.14 V < VTT < 1.26 V
VDD
1 kΩ
50 Ω
50 Ω
A
B
2 kΩ
0.1 µF
LVDS Receiver
Figure 25. Gunning Transceiver Logic (GTL)
15
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
Z0
Z0
A
B
1.47 V < VTT < 1.62 V
0.1 µF
LVDS Receiver
Figure 26. Backplane Transceiver Logic (BTL)
3.3 V
3.3 V
50 Ω
120 Ω
120 Ω
33 Ω
ECL
A
50 Ω
33 Ω
B
51 Ω
51 Ω
LVDS Receiver
Figure 27. Low-Voltage Positive Emitter-Coupled Logic (LVPECL)
16
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
5V
5V
82 Ω
50 Ω
82 Ω
100 Ω
ECL
A
50 Ω
100 Ω
B
33 Ω
33 Ω
LVDS Receiver
Figure 28. Positive Emitter-Coupled Logic (PECL)
3.3 V
3.3 V
7.5 kΩ
A
B
7.5 kΩ
0.1 µF
LVDS Receiver
Figure 29. 3.3-V CMOS
17
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
5V
5V
10 kΩ
560 Ω
A
B
560 Ω
3.32 kΩ
0.1 µF
LVDS Receiver
Figure 30. 5-V CMOS
5V
5V
10 kΩ
470 Ω
A
B
3.3 V
4.02 kΩ
0.1 µF
LVDS Receiver
Figure 31. 5-V TTL
3.3 V
3.3 V
4.02 kΩ
560 Ω
A
B
3.01 kΩ
Figure 32. LVTTL
18
0.1 µF
LVDS Receiver
SN65LVDS104
SN65LVDS105
www.ti.com
SLLS396F – SEPTEMBER 1999 – REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
FAIL SAFE
A common problem with differential signaling applications is how the system responds when no differential
voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that its output
logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV and within
its recommended input common-mode voltage range. Hovever, TI LVDS receivers handles the open-input circuit
situation differently.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
pulls each line of the signal pair to near VCC through 300-kΩ resistors as shown in Figure 33. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level regardless of the differential input voltage.
VCC
300 kΩ
300 kΩ
A
Rt = 100 Ω (Typ)
Y
B
VIT ≈ 2.3 V
Figure 33. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver will be valid with less than a 100 mV differential
input voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as
long as it is connected as shown in Figure 33. Other termination circuits may allow a dc current to ground that
could defeat the pullup currents from the receiver and the fail-safe feature.
19
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LVDS104D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS104DG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS104DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS104DRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS104PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS104PWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS104PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS104PWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS105D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS105DG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS105DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS105DRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS105PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS105PWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS105PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS105PWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jan-2007
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to
discontinue any product or service without notice. Customers should obtain the latest relevant information
before placing orders and should verify that such information is current and complete. All products are sold
subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent
TI deems necessary to support this warranty. Except where mandated by government requirements, testing
of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible
for their products and applications using TI components. To minimize the risks associated with customer
products and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent
right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine,
or process in which TI products or services are used. Information published by TI regarding third-party
products or services does not constitute a license from TI to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or
other intellectual property of the third party, or a license from TI under the patents or other intellectual
property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices.
Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not
responsible or liable for such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for
that product or service voids all express and any implied warranties for the associated TI product or service
and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Low Power Wireless
www.ti.com/lpw
Telephony
www.ti.com/telephony
Mailing Address:
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated