SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G – SEPTEMBER 1999 – REVISED NOVEMBER 2004
HIGH-SPEED DIFFERENTIAL LINE RECEIVERS
FEATURES
•
•
•
•
•
•
•
•
•
•
•
Four- ('390), Eight- ('388A), or Sixteen- ('386)
Line Receivers Meet or Exceed the
Requirements of ANSI TIA/EIA-644 Standard
Integrated 110-Ω Line Termination Resistors
on LVDT Products
Designed for Signaling Rates (1) Up To
630 Mbps
SN65 Version's Bus-Terminal ESD Exceeds
15 kV
Operates From a Single 3.3-V Supply
Typical Propagation Delay Time of 2.6 ns
Output Skew 100 ps (Typ) Part-To-Part Skew
Is Less Than 1 ns
LVTTL Levels Are 5-V Tolerant
Open-Circuit Fail Safe
Flow-Through Pinout
Packaged in Thin Shrink Small-Outline
Package With 20-mil Terminal Pitch
DESCRIPTION
This family of four-, eight-, or sixteen-, differential line
receivers (with optional integrated termination) implements the electrical characteristics of low-voltage
differential signaling (LVDS). This signaling technique
lowers the output voltage levels of 5-V differential
standard levels (such as EIA/TIA-422B) to reduce the
power, increase the switching speeds, and allow
operation with a 3-V supply rail. Any of the eight or
sixteen differential receivers provides a valid logical
output state with a ±100-mV differential input voltage
within the input common-mode voltage range. The
input common-mode voltage range allows 1 V of
ground potential difference between two LVDS
nodes. Additionally, the high-speed switching of
LVDS signals almost always requires the use of a line
impedance matching resistor at the receiving end of
the cable or transmission media. The LVDT products
eliminate this external resistor by integrating it with
the receiver.
(1)
’LVDS388A, ’LVDT388A
DBT PACKAGE
(TOP VIEW)
A1A
A1B
A2A
A2B
AGND
B1A
B1B
B2A
B2B
AGND
C1A
C1B
C2A
C2B
AGND
D1A
D1B
D2A
D2B
1
38
2
37
3
36
4
35
5
34
6
33
7
32
8
31
9
30
10
29
11
28
12
27
13
26
14
25
15
24
16
23
17
22
18
21
19
20
GND
VCC
ENA
A1Y
A2Y
ENB
B1Y
B2Y
DGND
DVCC
DGND
C1Y
C2Y
ENC
D1Y
D2Y
END
VCC
GND
See application section for VCC
and GND description.
’LVDS390, ’LVDT390
D OR PW PACKAGE
(TOP VIEW)
1A
1B
2A
2B
3A
3B
4A
4B
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
EN1,2
1Y
2Y
VCC
GND
3Y
4Y
EN3,4
’LVDS386, ’LVDT386
DGG PACKAGE
(TOP VIEW)
A1A
A1B
A2A
A2B
A3A
A3B
A4A
A4B
B1A
B1B
B2A
B2B
B3A
B3B
B4A
B4B
C1A
C1B
C2A
C2B
C3A
C3B
C4A
C4B
D1A
D1B
D2A
D2B
D3A
D3B
D4A
D4B
1
64
2
63
3
62
4
61
5
60
6
59
7
58
8
57
9
56
10
55
11
54
12
53
13
52
14
51
15
50
16
49
17
48
18
47
19
46
20
45
21
44
22
43
23
42
24
41
25
40
26
39
27
38
28
37
29
36
30
35
31
34
32
33
GND
VCC
VCC
GND
ENA
A1Y
A2Y
A3Y
A4Y
ENB
B1Y
B2Y
B3Y
B4Y
GND
VCC
VCC
GND
C1Y
C2Y
C3Y
C4Y
ENC
D1Y
D2Y
D3Y
D4Y
END
GND
VCC
VCC
GND
Signaling Rate, 1/t, where t is the minimum unit interval and is
expressed in the units bits/s (bits per second)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2004, Texas Instruments Incorporated
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G – SEPTEMBER 1999 – REVISED NOVEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The intended application of this device and signaling technique is for point-to-point baseband data transmission
over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board
traces, backplanes, or cables. The large number of receivers integrated into the same substrate along with the
low pulse skew of balanced signaling, allows extremely precise timing alignment of clock and data for
synchronous parallel data transfers. When used with its companion, 8- or 16-channel driver, the SN65LVDS389
or SN65LVDS387, over 300 million data transfers per second in single-edge clocked systems are possible with
little power. (Note: The ultimate rate and distance of data transfer depends on the attenuation characteristics of
the media, the noise coupling to the environment, and other system characteristics.)
AVAILABLE OPTIONS
TEMPERATURE
RANGE
NUMBER OF
RECEIVERS
BUS-PIN ESD
SYMBOLIZATION
SN65LVDS386DGG
–40°C to 85°C
16
15 kV
LVDS386
SN65LVDT386DGG
–40°C to 85°C
16
15 kV
LVDT386
SN75LVDS386DGG
0°C to 70°C
16
4 kV
75LVDS386
SN75LVDT386DGG
0°C to 70°C
16
4 kV
75LVDT386
SN65LVDS388ADBT
–40°C to 85°C
8
15 kV
LVDS388A
SN65LVDT388ADBT
–40°C to 85°C
8
15 kV
LVDT388A
SN75LVDS388ADBT
0°C to 70°C
8
4 kV
75LVDS388A
SN75LVDT388ADBT
0°C to 70°C
8
4 kV
75LVDT388A
SN65LVDS390D
–40°C to 85°C
4
15 kV
LVDS390
SN65LVDS390PW
–40°C to 85°C
4
15 kV
LVDS390
SN65LVDT390D
–40°C to 85°C
4
15 kV
LVDT390
SN65LVDT390PW
PART NUMBER
–40°C to 85°C
4
15 kV
LVDT390
SN75LVDS390D
0°C to 70°C
4
4 kV
75LVDS390
SN75LVDS390PW
0°C to 70°C
4
4 kV
DS390
SN75LVDT390D
0°C to 70°C
4
4 kV
75LVDT390
SN75LVDT390PW
0°C to 70°C
4
4 kV
DG390
2
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G – SEPTEMBER 1999 – REVISED NOVEMBER 2004
LOGIC DIAGRAM (POSITIVE LOGIC)
’LVDx388A
’LVDx386
’LVDx390
’LVDT386 ONLY
’LVDT390 ONLY
’LVDT388A ONLY
1A
1Y
1B
2A
2Y
2B
EN
3A
1A
1Y
1A
1B
EN
2A
1Y
1B
EN
2A
2Y
2B
2B
3Y
4A
3A
(1/4 of ’LVDx388A shown)
3B
2Y
3Y
3B
EN
4A
4Y
4B
4Y
4B
(1/4 of ’LVDx386 shown)
(’LVDx390 shown)
FUNCTION TABLE
SNx5LVD386/388A/390 and SNx5LVDT386/388A/390
(1)
DIFFERENTIAL INPUT (1)
ENABLES (1)
OUTPUT (1)
A-B
EN
Y
VID≥ 100 mV
H
H
–100 mV < VID≤ 100 mV
H
?
VID≤ -100 mV
H
L
X
L
Z
Open
H
H
H = high level, L = low level, X = irrelevant, Z = high impedance
(off), ? = indeterminate
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
VCC
300 kΩ
VCC
300 kΩ
400 Ω
5Ω
EN
Y Output
A Input
B Input
7V
7V
300 kΩ
7V
7V
110 Ω
’LVDT Devices Only
3
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G – SEPTEMBER 1999 – REVISED NOVEMBER 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)
(1)
UNITS
VCC
(2)
Supply voltage range
VI
–0.5 V to 4 V
Voltage range:
IO
Output current
|VID|
Differential input voltage magnitude
Enables or Y
–0.5 V to 6 V
A or B
–0.5 V to 4 V
±12 mA
Y
Electrostatic discharge: see
SN65LVDT' or SN75LVDT' only
(3)
Class 3, A:15 kV, B: 400 V
SN75' (A, B, and GND)
Class 2, A:4 kV, B: 400 V
Continuous power dissipation
Tstg
1V
SN65' (A, B, and GND)
See Dissipation Rating Table
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 in) from case
for 10 seconds
(1)
(2)
(3)
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
PACKAGE
(1)
TA≤ 25°C
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
494 mW
D
950 mW
7.6 mW/°C
608 mW
DBT
1071 mW
8.5 mW/°C
688 mW
556 mW
DGG
2094 mW
16.7 mW/°C
1342 mW
1089 mW
PW
774 mW
6.2 mW/°C
496 mW
402 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted (low-k) and with no air flow.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
VCC
Supply voltage
3
3.3
3.6
VIH
High-level input voltage
2
VIL
Low-level input voltage
IO
Output current
|VID|
Magnitude of differential input voltage
VIC, see Figure 4
Common-mode input voltage
V
V
0.8
Y
UNIT
–8
8
0.1
0.6
mA
V
|V
|V
|
ID
2
2.4 |
ID
2
V
V
VCC – 0.8
TA
4
Operating free-air temperature
SN75'
0
70
°C
SN65'
–40
85
°C
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G – SEPTEMBER 1999 – REVISED NOVEMBER 2004
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going differential input voltage threshold
VIT–
Negative-going differential input voltage threshold
See Figure 1 and
Table 1
VOH
High-level output voltage
IOH= –8 mA
VOL
Low-level output voltage
IOL = 8 mA
MIN
ICC
Supply current
2.4
Enabled, No load
'LVDx390
II
Input current (A or B inputs)
'LVDT
100
mV
mV
V
0.2
0.4
50
70
22
40
8
18
3
Disabled
V
mA
3
'LVDx390
'LVDS
UNIT
3
'LVDx386
'LVDx388A
MAX
–100
'LVDx386
'LVDx388A
TYP (1)
1.5
VI = 0 V
VI = 2.4 V
–13
–1.2
VI = 0 V, other input
open
VI = 2.4 V, other input
open
–20
–3
–40
µA
±2
µA
2.2
mA
±20
µA
–2.4
IID
Differential input current |IIA - IIB|
'LVDS
VIA = 0 V, VIB = 0.1 V,
VIA= 2.4 V, VIB = 2.3 V
IID
Differential input current (IIA - IIB)
'LVDT
VIA = 0.2 V, VIB = 0 V,
VIA= 2.4 V, VIB = 2.2 V
II(OFF)
Power-off input current (A or B inputs)
'LVDS
VCC = 0 V, VI = 2.4 V
II(OFF)
Power-off input current (A or B inputs)
'LVDT
VCC = 0 V, VI = 2.4 V
±40
µA
IIH
High-level input current (enables)
VIH = 2 V
10
µA
IIL
Low-level input current (enables)
VIL = 0.8 V
10
µA
IOZ
High-impedance output current
VO = 0 V
±1
VO= 3.6 V
10
CIN
Input capacitance, A or B input to GND
VID = 0.4 sin 2.5E09 t V
Z(t)
Termination impedance
VID = 0.4 sin 2.5E09 t V
(1)
1.5
12
5
88
µA
pF
132
Ω
All typical values are at 25°C and with a 3.3-V supply.
5
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G – SEPTEMBER 1999 – REVISED NOVEMBER 2004
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
MAX
UNIT
tPLH
Propagation delay time, low-to-high-level output
1
2.6
4
ns
tPHL
Propagation delay time, high-to-low-level output
1
2.5
4
ns
tr
Output signal rise time
500
800
1200
ps
tf
Output signal fall time
500
800
1200
ps
tsk(p)
Pulse skew (|tPHL - tPLH|)
150
600
ps
tsk(o)
Output skew (2)
100
400
ps
tsk(pp)
Part-to-part skew (3)
1
ns
tPZH
Propagation delay time, high-impedance-to-high-level output
7
15
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
7
15
ns
tPHZ
Propagation delay time, high-level-to-high-impedance output
7
15
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
7
15
ns
(1)
(2)
(3)
See Figure 2
See Figure 3
All typical values are at 25°C and with a 3.3-V supply.
tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all drivers of a single device with all of their inputs connected
together.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of any two devices characterized in
this data sheet when both devices operate with the same supply voltage, at the same temperature, and have the same test circuits.
PARAMETER MEASUREMENT INFORMATION
A
V
IA
V
IB
VID
2
R
VIA
VIC
B
VO
VIB
Figure 1. Voltage Definitions
Table 1. Receiver Minimum and Maximum Input Threshold Test Voltages
APPLIED VOLTAGES
6
RESULTING DIFFERENTIAL
INPUT VOLTAGE
RESULTING COMMONMODE INPUT VOLTAGE
VIA
VIB
VID
VIC
1.25 V
1.15 V
100 mV
1.2 V
1.15 V
1.25 V
–100 mV
1.2 V
2.4 V
2.3 V
100 mV
2.35 V
2.3 V
2.4 V
–100 mV
2.35 V
0.1 V
0V
100 mV
0.05 V
0V
0.1 V
–100 mV
0.05 V
1.5 V
0.9 V
600 mV
1.2 V
0.9 V
1.5 V
–600 mV
1.2 V
2.4 V
1.8 V
600 mV
2.1 V
1.8 V
2.4 V
–600 mV
2.1 V
0.6 V
0V
600 mV
0.3 V
0V
0.6 V
–600 mV
0.3 V
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G – SEPTEMBER 1999 – REVISED NOVEMBER 2004
VID
VIA
VIB
CL
10 pF
VO
VIA
1.4 V
VIB
1V
VID
0.4 V
0V
–0.4 V
tPHL
VO
tPLH
VOH
80%
1.5 V
20%
VOL
tf
A.
tr
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 2. Timing Test Circuit and Wave Forms
7
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G – SEPTEMBER 1999 – REVISED NOVEMBER 2004
B
1.2 V
500 Ω
A
Inputs
A.
CL
10 pF
EN
+
–
VO
VTEST
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
2.5 V
VTEST
A
1V
2V
EN
1.4 V
0.8 V
tPZL
tPLZ
2.5 V
1.4 V
Y
VOL +0.5 V
VOL
0V
VTEST
A
1.4 V
2V
EN
1.4 V
0.8 V
tPZH
Y
VOH –0.5 V
tPHZ
VOH
1.4 V
0V
Figure 3. Enable/Disable Time Test Circuit and Wave Forms
8
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G – SEPTEMBER 1999 – REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS
LVDx390
SUPPLY CURRENT
vs
SWITCHING FREQUENCY
COMMON-MODE INPUT VOLTAGE
vs
DIFFERENTIAL INPUT VOLTAGE
140
2.5
120
Max at VCC = 3 V
2.0
ICC − Supply Current − mA
VIC − Common-Mode Input Voltage − V
Max at VCC > 3.15 V
1.5
1.0
VCC = 3.6 V
100
80
VCC = 3 V
60
VCC = 3.3 V
40
0.5
20
Minimum
0.0
0.0
0
0.1
0.2
0.3
0.4
0.5
0
0.6
50
150
200
250
Figure 4.
Figure 5.
LVDx388A
SUPPLY CURRENT
vs
SWITCHING FREQUENCY
LVDx386
SUPPLY CURRENT
vs
SWITCHING FREQUENCY
350
300
350
600
300
500
ICC − Supply Current − mA
ICC − Supply Current − mA
100
f − Switching Frequency − MHz
|VID| − Differential Input Voltage − V
250
VCC = 3.6 V
200
VCC = 3 V
150
VCC = 3.3 V
100
VCC = 3.6 V
400
VCC = 3 V
300
VCC = 3.3 V
200
100
50
0
0
0
50
100
150
200
250
f − Switching Frequency − MHz
Figure 6.
300
0
50
100
150
200
250
300
f − Switching Frequency − MHz
Figure 7.
9
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G – SEPTEMBER 1999 – REVISED NOVEMBER 2004
TYPICAL CHARACTERISTICS (continued)
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
4.0
5.0
4.5
VOL − Low-Level Output Voltage − V
3.0
2.5
2.0
1.5
1.0
0.5
t PLH − Low-To-High Propagation Delay Time − ns
0.0
−70
3.5
3.0
2.5
2.0
1.5
1.0
0.0
−60
−50
−40
−30
−20
−10
0
0
10
20
30
40
50
60
70
IOH − High-Level Output Current − mA
IOL − Low-Level Output Current − mA
Figure 8.
Figure 9.
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
3.0
2.9
2.8
VCC = 3 V
2.7
2.6
VCC = 3.6 V
2.5
2.4
VCC = 3.3 V
2.3
2.2
2.1
2.0
−50
−30
−10
10
30
50
TA − Free-Air Temperature − °C
Figure 10.
10
4.0
0.5
t PHL − High-To-Low Propagation Delay Time − ns
VOH − High-Level Output Voltage − V
3.5
70
90
80
3.0
2.9
2.8
2.7
2.6
2.5
VCC = 3 V
VCC = 3.6 V
2.4
2.3
2.2
VCC = 3.3 V
2.1
2.0
−50
−30
−10
10
30
50
TA − Free-Air Temperature − °C
Figure 11.
70
90
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G – SEPTEMBER 1999 – REVISED NOVEMBER 2004
APPLICATION INFORMATION
Host
Host
Controller
Power
Balanced Interconnect
Power
Target
T
DBn
DBn
Target
Controller
T
DBn–1
DBn–1
T
DBn–2
DBn–2
T
DBn–3
DBn–3
T
DB2
DB2
T
DB1
DB1
T
DB0
DB0
T
TX Clock
RX Clock
LVDx368, LVDx388
LVDx388A, or LVDx390
LVDS Drivers
Indicates twisting of the
conductors.
Indicates the line termination
T circuit.
Figure 12. Typical Application Schematic
ANALOG AND DIGITAL GROUNDS/POWER SUPPLIES
Although it is not necessary to separate out the analog/digital supplies and grounds on the SN65LVDS/T388A
and SN75LVDS/T388A, the pinout provides the user that option. To help minimize or perhaps eliminate switching
noise being coupled between the two supplies, the user could lay out separate supply and ground planes for the
designated pinout.
Most applications probably have all grounds connected together and all power supplies connected together. This
configuration was used while characterizing and setting the data-sheet parameters.
FAIL SAFE
One of the most common problems with differential signaling applications is how the system responds when no
differential voltage is present on the signal pair. The LVDS receiver is like most differential line receivers, in that
its output logic state can be indeterminate when the differential input voltage is between –100 mV and 100 mV,
and within its recommended input common-mode voltage range. TI's LVDS receiver is different in how it handles
the open-input circuit situation, however.
Open-circuit means that there is little or no input current to the receiver from the data line itself. This could be
when the driver is in a high-impedance state or the cable is disconnected. When this occurs, the LVDS receiver
pulls each line of the signal pair to near VCC through 300-kΩ resistors, as shown in Figure 13. The fail-safe
feature uses an AND gate with input voltage thresholds at about 2.3 V to detect this condition and force the
output to a high-level, regardless of the differential input voltage.
11
SN65LVDS386/388A/390, SN65LVDT386/388A/390
SN75LVDS386/388A/390, SN75LVDT386/388A/390
www.ti.com
SLLS394G – SEPTEMBER 1999 – REVISED NOVEMBER 2004
APPLICATION INFORMATION (continued)
VCC
300 kΩ
300 kΩ
A
Rt = 100 Ω (Typ)
Y
B
VIT ≈ 2.3 V
Figure 13. Open-Circuit Fail Safe of the LVDS Receiver
It is only under these conditions that the output of the receiver is valid with less than a 100-mV differential input
voltage magnitude. The presence of the termination resistor, Rt, does not affect the fail-safe function as long as it
is connected as shown in the figure. Other termination circuits may allow a dc current to ground that could defeat
the pullup currents from the receiver and the fail-safe feature.
12
PACKAGE OPTION ADDENDUM
www.ti.com
18-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN65LVDS386DGG
ACTIVE
TSSOP
DGG
64
25
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65LVDS386DGGR
ACTIVE
TSSOP
DGG
64
2000
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65LVDS388ADBT
ACTIVE
SM8
DBT
38
50
TBD
CU NIPDAU
Level-2-220C-1 YEAR
SN65LVDS388ADBTR
ACTIVE
SM8
DBT
38
2000
TBD
CU NIPDAU
Level-2-220C-1 YEAR
SN65LVDS390D
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN65LVDS390DR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN65LVDS390PW
ACTIVE
TSSOP
PW
16
90
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65LVDS390PWR
ACTIVE
TSSOP
PW
16
2000
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65LVDT386DGG
ACTIVE
TSSOP
DGG
64
25
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65LVDT386DGGG4
PREVIEW
TSSOP
DGG
64
25
TBD
Call TI
SN65LVDT386DGGR
ACTIVE
TSSOP
DGG
64
2000
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65LVDT388ADBT
ACTIVE
SM8
DBT
38
50
TBD
CU NIPDAU
Level-2-220C-1 YEAR
SN65LVDT388ADBTR
ACTIVE
SM8
DBT
38
2000
TBD
CU NIPDAU
Level-2-220C-1 YEAR
SN65LVDT390D
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN65LVDT390DR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Call TI
SN65LVDT390PW
ACTIVE
TSSOP
PW
16
90
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN65LVDT390PWR
ACTIVE
TSSOP
PW
16
2000
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN75LVDS386DGG
ACTIVE
TSSOP
DGG
64
25
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN75LVDS386DGGR
ACTIVE
TSSOP
DGG
64
2000
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN75LVDS388ADBT
ACTIVE
SM8
DBT
38
50
TBD
CU NIPDAU
Level-2-220C-1 YEAR
SN75LVDS388ADBTR
ACTIVE
SM8
DBT
38
2000
TBD
CU NIPDAU
Level-2-220C-1 YEAR
SN75LVDS390D
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN75LVDS390DR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN75LVDS390PW
ACTIVE
TSSOP
PW
16
90
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN75LVDS390PWR
ACTIVE
TSSOP
PW
16
2000
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN75LVDS390PWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN75LVDT386DGG
ACTIVE
TSSOP
DGG
64
25
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN75LVDT386DGGR
ACTIVE
TSSOP
DGG
64
2000
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN75LVDT388ADBT
ACTIVE
SM8
DBT
38
50
TBD
CU NIPDAU
Level-2-220C-1 YEAR
SN75LVDT388ADBTG4
ACTIVE
SM8
DBT
38
50
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TBD
CU NIPDAU
Level-2-220C-1 YEAR
CU NIPDAU
Level-2-260C-1 YEAR
SN75LVDT388ADBTR
ACTIVE
SM8
DBT
38
2000
SN75LVDT388ADBTRG4
PREVIEW
SM8
DBT
38
2000 Green (RoHS &
no Sb/Br)
SN75LVDT390D
ACTIVE
SOIC
D
16
40
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
SN75LVDT390DR
ACTIVE
SOIC
D
16
2500
Pb-Free
(RoHS)
CU NIPDAU
Level-2-260C-1YEAR/
Level-1-220C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Mar-2005
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN75LVDT390PW
ACTIVE
TSSOP
PW
16
90
TBD
CU NIPDAU
Level-1-220C-UNLIM
SN75LVDT390PWR
ACTIVE
TSSOP
PW
16
2000
TBD
CU NIPDAU
Level-1-220C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS019D – FEBRUARY 1996 – REVISED FEBRUARY 2002
DBT (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
30 PINS SHOWN
0,50
0,27
0,17
30
16
0,08 M
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
15
0°–ā8°
0,75
0,50
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
20
24
28
30
38
44
50
A MAX
5,10
6,60
7,90
7,90
9,80
11,10
12,60
A MIN
4.90
6,40
7,70
7,70
9,60
10,90
12,40
DIM
4073252/E 02/02
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated