TI SN65LVDT9637BD

SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
www.ti.com
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
HIGH-SPEED DIFFERENTIAL RECEIVERS
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
Meets or Exceeds the Requirements of ANSI
EIA/TIA-644 Standard for Signaling Rates (1) up
to 400 Mbps
Operates With a Single 3.3-V Supply
–2-V to 4.4-V Common-Mode Input Voltage
Range
Differential Input Thresholds <50 mV With
50 mV of Hysteresis Over Entire CommonMode Input Voltage Range
Integrated 110-Ω Line Termination Resistors
Offered With the LVDT Series
Propagation Delay Times 4 ns (typ)
Active Fail Safe Assures a High-Level Output
With No Input
Bus-Pin ESD Protection Exceeds 15 kV HBM
Inputs Remain High-Impedance on Power
Down
Recommended Maximum Parallel Rate of
200 M-Transfer/s
Available in Small-Outline Package With
1,27-mm Terminal Pitch
Pin-Compatible With the AM26LS32, MC3486,
or µA9637
DESCRIPTION
This family of differential line receivers offers
improved performance and features that implement
the electrical characteristics of low-voltage differential
signaling (LVDS). LVDS is defined in the
TIA/EIA-644 standard. This improved performance
represents the second generation of receiver
products for this standard, providing a better overall
solution for the cabled environment. This generation
of products is an extension to TI's overall product
portfolio and is not necessarily a replacement for
older LVDS receivers.
SN65LVDS32B
SN65LVDT32B
Logic Diagram
(positive logic)
D PACKAGE
(TOP VIEW)
1B
1A
1Y
G
2Y
2A
2B
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4B
4A
4Y
G
3Y
3A
3B
G
G
SN65LVDT32B
ONLY (4 Places)
1A
1Y
1B
2A
2Y
2B
3A
3Y
3B
4A
4Y
4B
SN65LVDS3486B
SN65LVDT3486B
Logic Diagram
(positive logic)
D PACKAGE
(TOP VIEW)
1B
1A
1Y
1,2EN
2Y
2A
2B
GND
SN65LVDT3486B
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
ONLY (4 Places)
1A
4B
4A
1B
1,2EN
4Y
2A
3,4EN
3Y
2B
3A
3A
3B
3B
3,4EN
4A
1Y
2Y
3Y
4Y
4B
SN65LVDS9637B
SN65LVDT9637B
D PACKAGE
(TOP VIEW)
VCC
1Y
2Y
GND
1
8
2
7
3
6
4
5
Logic Diagram
(positive logic)
1A
1B
2A
2B
1A
1Y
1B
SN65LVDT9637B
ONLY
2A
2Y
2B
(1)
Signaling rate, 1/t, where t is the minimum unit interval and is
expressed in the units bit/s (bits per second).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2007, Texas Instruments Incorporated
SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
www.ti.com
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Improved features include an input common-mode voltage range 2 V wider than the minimum required by the
standard. This will allow longer cable lengths by tripling the allowable ground noise tolerance to 3 V between a
driver and receiver. TI has additionally introduced an even wider input common-mode voltage range of –4 to 5 V
in their SN65LVDS/T33 and SN65LVDS/T34.
Precise control of the differential input voltage thresholds now allows for inclusion of 50 mV of input voltage
hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more
than ±50 mV over the full input common-mode voltage range.
The high-speed switching of LVDS signals almost always necessitates the use of a line impedance matching
resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates
this external resistor by integrating it with the receiver. The non-terminated SN65LVDS series is also available
for multidrop or other termination circuits.
The receivers can withstand ±15-kV human-body model (HBM) and ±600 V-machine model (MM) electrostatic
discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled
and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent pending) fail-safe circuit that will provide a high-level output within 600 ns
after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or
powered-down transmitters. This prevents noise from being received as valid data under these fault conditions.
This feature may also be used for wired-OR bus signaling.
The intended application of these devices and signaling technique is for point-to-point baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media may be
printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent
upon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS32B, SN65LVDT32B, SN65LVDS3486B, SN65LVDT3486B,
SN65LVDT9637B are characterized for operation from –40°C to 85°C.
SN65LVDS9637B,
AVAILABLE OPTIONS
(1)
2
PART NUMBER (1)
NUMBER OF
RECEIVERS
TERMINATION
RESISTOR
SYMBOLIZATION
SN65LVDS32BD
4
No
LVDS32B
SN65LVDT32BD
4
Yes
LVDT32B
SN65LVDS3486BD
4
No
LVDS3486
SN65LVDT3486BD
4
Yes
LVDT3486
SN65LVDS9637BD
2
No
DK637B
SN65LVDT9637BD
2
Yes
DR637B
Add the suffix R for taped and reeled carrier.
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and
SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
www.ti.com
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
FUNCTION TABLES
SN65LVDS32B and SN65LVDT32B
ENABLES (1)
DIFFERENTIAL INPUT
(1)
OUTPUT (1)
A-B
G
G
Y
VID ≥ –32 mV
H
X
X
L
H
H
–100 mV < VID ≤ –32 mV
H
X
X
L
?
?
VID ≤ –100 mV
H
X
X
L
L
L
X
L
H
Z
Open
H
X
X
L
H
H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
SN65LVDS3486B and SN65LVDT3486B
(1)
DIFFERENTIAL INPUT
ENABLES (1)
OUTPUT (1)
A-B
EN
Y
VID ≥ –32 mV
H
H
–100 mV < VID ≤ –32 mV
H
?
VID ≤ –100 mV
H
L
X
L
Z
Open
H
H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
SN65LVDS9637B and SN65LVDT9637B
DIFFERENTIAL INPUT
(1)
OUTPUT (1)
A-B
Y
VID≥ -32 mV
H
–100 mV < VID≤ -32 mV
?
VID≤ -100 mV
L
Open
H
H = high level, L = low level, ? = indeterminate
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SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
www.ti.com
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
VCC
Attenuation
Network
6.5 kΩ
60 kΩ
A Input
200 kΩ
3 pF
250 kΩ
Attenuation
Network
1 pF
6.5 kΩ
Attenuation
Network
VCC
B Input
7V
7V
7V
7V
LVDT Only 110 Ω
VCC
VCC
300 kΩ
(G Only)
Enable
Inputs
50 Ω
37 Ω
Y Output
7V
7V
300 kΩ
(EN and G Only)
4
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SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
www.ti.com
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Supply voltage range (2)
VCC
–0.5 V to 4 V
Enables or Y
Voltage range
–0.5 V to VCC + 3 V
A or B
Electrostatic discharge:
–4 V to 6 V
|VA– VB| (LVDT)
1V
A, B, and GND (3)
Class 3, A: 15 kV, B: 600 V
Continuous power dissipation
See Dissipation Rating Table
Storage temperature range
–65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
(2)
(3)
260°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with MIL-STD-883C Method 3015.7.
DISSIPATION RATING TABLE
(1)
PACKAGE
TA ≤ 25°C
POWER RATING
OPERATING FACTOR (1)
ABOVE TA = 25°C
TA = 85°C
POWER RATING
D8
725 mW
5.8 mW/°C
377 mW
D16
950 mW
7.6 mW/°C
494 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air
flow.
RECOMMENDED OPERATING CONDITIONS
VCC
Supply voltage
VIH
High-level input voltage
Enables
VIL
Low-level input voltage
Enables
| VID|
Magnitude of differential input voltage
VI or VIC
Voltage at any bus terminal (separately or common-mode)
TA
Operating free-air temperature
LVDS
MIN
NOM
MAX
3
3.3
3.6
2
0.1
V
V
0.8
V
3
V
0.8
V
–2
4.4
V
–40
85
°C
LVDT
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UNIT
5
SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
www.ti.com
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
VIT1
Positive-going differential input voltage threshold
VIT2
Negative-going differential input voltage threshold
VIB = -2 V or 4.4 V,
See Figure 1 and Figure 2
–50
VIT3
Differential input fail-safe voltage threshold
See Table 1 and Figure 5
–32
50
VID(HYS) Differential input voltage hysteresis, VIT1– VIT2
High-level output voltage
IOH = –4 mA
VOL
Low-level output voltage
IOL = 4 mA
Supply current
'32B or '3486B
'9637B
II
Input current (A or B inputs)
SN65LVDT
Differential input current
(IIA - IIB)
IID
G or EN at GND
1.1
5
Power-off input current
(A or B inputs)
VI = 2.4 V, Other input open
±20
VI = –2 V, Other input open
±40
VI = 4.4 V, Other input open
±40
VI = 0 V, Other input open
±40
VI = 2.4 V, Other input open
±40
VI = –2 V, Other input open
±80
VI = 4.4 V, Other input open
±80
1.55
VA or VB = 0 V or 2.4 V, VCC = 0 V
±30
VA or VB = –2 V or 4.4 V, VCC = 0 V
±50
Low-level input current (enables)
VIL = 0.8 V
High-impedance output current
CI
Input capacitance, A or B input to GND
VI = 0.4 sin (4E6πt) + 0.5 V
All typical values are at 25°C and with a 3.3 V supply.
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5
µA
mA
±35
IOZ
µA
2.22
VA or VB = –2 V or 4.4 V, VCC = 0 V
IIL
mA
µA
±20
VIH = 2 V
V
±3
VA or VB = 0 V or 2.4 V, VCC = 0 V
High-level input current (enables)
mV
12
±20
IIH
(1)
8
VI = 0 V, Other input open
VID = 0.2 V, VIC = –2 V or 4.4 V
SN65LVDT
6
23
SN65LVDT
SN65LVDS
II(OFF)
0.4
16
SN65LVDS
mV
V
G or EN at VCC, No load, Steady-state
VID = 100 mV, VIC= –2 V or 4.4 V,
See Figure 1
UNIT
mV
2.4
No load, Steady-state
SN65LVDS
–100
50
VOH
ICC
MAX
µA
10
µA
10
µA
±10
µA
pF
SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
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SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
td1
Delay time, fail-safe deactivate time
td2
Delay time, fail-safe activate time
tsk(p)
Pulse skew (|tPHL1 - tPLH1|)
See Figure 3
See Figure 3 and
Figure 6
MIN TYP (1)
MAX
4
6
ns
2.5
4
6
ns
0.3
9
ns
1.5
µs
200
skew (2)
UNIT
2.5
ps
tsk(o)
Output
tsk(pp)
Part-to-part skew (3)
tr
Output signal rise time
0.8
tf
Output signal fall time
0.8
tPHZ
Propagation delay time, high-level-to-high-impedance output
5.5
9
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
4.4
9
ns
tPZH
Propagation delay time, high-impedance -to-high-level output
3.8
9
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
7
9
ns
(1)
(2)
(3)
150
CL = 10 pF, See Figure 3
See Figure 4
ps
1
ns
ns
ns
All typical values are at 25°C and with a 3.3-V supply.
tsk(o) is the magnitude of the time difference between the tPLH or tPHL of all receivers of a single device with all of their inputs driven
together.
tsk(pp) is the magnitude of the time difference in propagation delay times between any specified terminals of two devices when both
devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits.
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SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
www.ti.com
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
PARAMETER MEASUREMENT INFORMATION
IIA
A
VO
Y
VID
B
(VIA + VIB)/2
VIA
VIC
IIB
VO
VIB
Figure 1. Voltage and Current Definitions
1000 Ω
100 Ω
100 Ω†
VID
1000 Ω
VIC
†
10 pF,
2 Places
+
–
VO
10 pF
Removed for testing the LVDT device
VIT1
0V
VID
–100 mV
VO
100 mV
VID
0V
VIT2
VO
NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns.
Figure 2. VIT1 and VIT2 Input Voltage Threshold Test Circuit and Definitions
8
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SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
www.ti.com
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
PARAMETER MEASUREMENT INFORMATION (continued)
VID
VIA
CL = 10 pF
VIB
VO
VIA
1.4 V
VIB
1V
0.4 V
VID
0V
–0.4 V
tPHL
tPLH
80%
VO
20%
1.4 V
VOL
20%
tf
A.
VOH
80%
tr
All input pulses are supplied by a generator having the following characteristics: tr or tf≤ 1 ns, pulse repetition rate
(PRR) = 50 Mpps, Pulsewidth = 10 ±0.2 ns . CL includes instrumentation and fixture capacitance within 0,06 mm of
the D.U.T.
Figure 3. Timing Test Circuit and Waveforms
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SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
www.ti.com
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
PARAMETER MEASUREMENT INFORMATION (continued)
1.2 V
B
500 Ω
A
10 pF
±
VO
G
Inputs
VTEST
G
1,2,EN, or 3,4, EN
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse
repetition rate (PRR) = 0.5 Mpps, Pulsewidth = 500 ±10 ns . CL includes instrumentation and fixture
capacitance within 0,06 mm of the D.U.T.
VTEST
2.5 V
A
1V
2V
1.4 V
0.8 V
G, 1,2EN,or 3,4EN
2V
1.4 V
0.8 V
G
tPLZ
tPZL
tPLZ
tPZL
Y
VTEST
0
1.4 V
A
2V
1.4 V
0.8 V
2V
1.4 V
0.8 V
G, 1,2EN,or 3,4EN
G
tPHZ
tPZH
2.5 V
1.4 V
VOL +0.5 V
VOL
tPHZ
tPZH
Y
VOH
VOH –0.5 V
1.4 V
0
Figure 4. Enable/Disable Time Test Circuit and Waveforms
10
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SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
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SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
Table 1. Receiver Minimum and Maximum VIT3 Input Threshold Test Voltages
APPLIED VOLTAGES (1)
(1)
RESULTANT INPUTS
VIA (mV)
VIB (mV)
VID (mV)
VIC (mV)
Output
–2000
–1900
–100
–1950
L
–2000
–1968
–32
–1984
H
4300
4400
–100
4350
L
4368
4400
–32
4384
H
These voltages are applied for a minimum of 1.5 µs.
VIA
–100 mV @ 250 KHz
VIB
VO
a) No Failsafe
VIA
–32 mV @ 250 KHz
VIB
VO
Failsafe Asserted
b) Failsafe Asserted
Figure 5. VIT3 Failsafe Threshold Test
1.4 V
1V
0.4 V
>1.5 µs
0V
–0.2 V
–0.4 V
td1
td2
VOH
1.4 V
VOL
Figure 6. Waveforms for Failsafe Activate and Deactivate
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SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
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SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
4
VCC = 3.3 V
TA = 25°C
VCC = 3.3 V
TA = 25°C
VOH − High-Level Output Voltage − V
VOL − Low-Level Output Voltage − V
5
4
3
2
1
0
3
2
1
0
0
10
20
30
40
−40
IOL − Low-Level Output Current − mA
−10
Figure 8.
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
4.5
VCC = 3 V
4
VCC = 3.3 V
VCC = 3.6 V
3.5
3
−50
0
5
t PHL − High-To-Low Propagation Delay Time − ns
t PLH − Low-To-High Propagation Delay Time − ns
−20
Figure 7.
5
0
50
TA − Free-Air Temperature − °C
100
4.5
VCC = 3 V
VCC = 3.3 V
4
VCC = 3.6 V
3.5
3
−50
Figure 9.
12
−30
IOH − High-Level Output Current − mA
0
50
TA − Free-Air Temperature − °C
Figure 10.
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SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
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SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT
vs
FREQUENCY
140
I CC − Supply Current − mA
120
VCC = 3.3 V
100
80
VCC = 3.6 V
60
VCC = 3 V
40
20
0
0
100
150
200
f − Switching Frequency − MHz
Figure 11.
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SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
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SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
APPLICATION INFORMATION
0.01 µF
1
VCC
16
0.1 µF
(see Note A)
1B
100 Ω
2
3
VCC 4
5
6
1A
4B
2Y
4Y
G
2A
100 Ω
7
4A
2B
3Y
3A
5V
1N645
(2 places)
15
1Y
G
≈3.6 V
14
100 Ω
(see Note B)
13
12
11
See Note C
10
100 Ω
8
GND
3B
9
A.
Place a 0.1-µF Z5U ceramic, mica or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitor should be located as close as possible to the device terminals.
B.
The termination resistance value should match the nominal characteristic impedance of the transmission media with
±10%.
C.
Unused enable inputs should be tied to VCC or GND as appropriate.
Figure 12. Operation with 5-V Supply
RELATED INFORMATION
IBIS modeling is available for this device. contact the local TI sales office or the TI Web site at www.ti.com for
more information.
For more application guidelines, see the following documents:
• Low-Voltage Differential Signaling Design Notes (SLLA014)
• Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
• Reducing EMI With LVDS (SLLA030)
• Slew Rate Control of LVDS Circuits (SLLA034)
• Using an LVDS Receiver With RS-422 Data (SLLA031)
• Evaluating the LVDS EVM (SLLA033)
TERMINATED FAILSAFE
A differential line receiver commonly has a fail-safe circuit to prevent it from switching on input noise. Current
LVDS fail-safe solutions require either external components with subsequent reduction in signal quality or
integrated solutions with limited application. This family of receivers has a new integrated fail-safe that solves
the limitations seen in present solutions. A detailed theory of operation is presented in application note The
Active Fail-Safe Feature of the SN65LVDS32A (SLLA082).
Figure 13 shows one receiver channel with active fail-safe. It consists of a main receiver that can respond to a
high-speed input differential signal. Also connected to the input pair are two fail-safe receivers that form a
window comparator. The window comparator has a much slower response than the main receiver and detects
when the input differential falls below 80 mV. A 600-ns fail-safe timer filters the window comparator outputs.
When fail-safe is asserted, the fail-safe logic drives the main receiver output to logic high.
14
Submit Documentation Feedback
SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
www.ti.com
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
Output
Buffer
Main Receiver
+
_
A
B
R
Reset
Failsafe
Timer
A > B + 80 mV
+
_
Failsafe
B > A + 80 mV
+
_
Window Comparator
Figure 13. Receiver With Terminated Failsafe
ECL/PECL-to-LVTTL CONVERSION WITH TI's LVDS RECEIVER
The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of
choice for system designers. Designers know of the established technology and that it is capable of high-speed
data transmission. In the past, system requirements often forced the selection of ECL. Now technologies like
LVDS provide designers with another alternative. While the total exchange of ECL for LVDS may not be a
design option, designers have been able to take advantage of LVDS by implementing a small resistor divider
network at the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode
LVDS receiver (no divider network required) which can be connected directly to an ECL driver with only the
termination bias voltage required for ECL termination (VCC– 2 V).
Figure 14 and Figure 15 show the use of an LV/PECL driver driving 5 meters of CAT-5 cable and being received
by TI's wide common-mode receiver and the resulting eye pattern. The values for R3 are required in order to
provide a resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the
characteristic load impedance of 50 Ω. The R2 resistor is a small value and is intended to minimize any possible
common-mode current reflections.
VCC
R1 = 50 Ω
R2 = 50 Ω
ICC
5 Meters
of CAT-5
LV/PECL
R3
VEE
R3
VB
VB
R1
VCC
ICC
LVDS
R1
R2
R3 = 240 Ω
Figure 14. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
Submit Documentation Feedback
15
SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
www.ti.com
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
Figure 15. LV/PECL to Remote SN65LVDS32B at 500 Mbps Receiver Output (CH1)
TEST CONDITIONS
•
•
•
VCC = 3.3 V
TA = 25°C (ambient temperature)
All four channels switching simultaneously with NRZ data. Scope is pulse-triggered simultaneously with NRZ
data.
EQUIPMENT
•
•
•
Tektronix PS25216 programmable power supply
Tektronix HFS 9003 stimulus system
Tektronix TDS 784D 4-channel digital phosphor oscilloscope – DPO
Tektronix PS25216
Programmable
Power Supply
Tektronix HFS 9003
Stimulus System
Trigger
Bench Test Board
Figure 16. Equipment Setup
16
Submit Documentation Feedback
Tektronix TDS 784D 4-Channel
Digital Phosphor Oscilloscope
– DPO
SN65LVDS32B,, SN65LVDT32B
SN65LVDS3486B, SN65LVDT3486B
SN65LVDS9637B, SN65LVDT9637B
www.ti.com
SLLS440B – OCTOBER 2000 – REVISED APRIL 2007
APPLICATION INFORMATION (continued)
100 Mbit/s
200 Mbit/s
Figure 17. Typical Eye Pattern SN65LVDS32B
Submit Documentation Feedback
17
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
PACKAGING INFORMATION
(1)
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65LVDS32BD
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32BDG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32BDR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS32BDRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3486BD
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3486BDG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3486BDR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS3486BDRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637BD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637BDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637BDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9637BDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT32BD
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT32BDG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT32BDR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT32BDRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT3486BD
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT3486BDG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT3486BDR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT9637BD
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT9637BDG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT9637BDR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDT9637BDRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNLVDT3486BDRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
The marketing status values are defined as follows:
Addendum-Page 1
Lead/Ball Finish
MSL Peak Temp (3)
PACKAGE OPTION ADDENDUM
www.ti.com
23-Apr-2007
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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