SN65MLVD048 www.ti.com SLLS903 – DECEMBER 2009 QUAD CHANNEL M-LVDS RECEIVERS Check for Samples: SN65MLVD048 FEATURES 1 • 2 • • • • • • • (1) Low-Voltage Differential 30-Ω to 55-Ω Line Receivers for Signaling Rates(1) up to 250Mbps; Clock Frequencies up to 125MHz Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis Type-2 Receiver Provides 100 mV Offset Threshold to Detect Open-Circuit and Idle-Bus Conditions Wide Receiver Input Common-Mode Voltage Range, –1 V to 3.4 V, Allows 2 V of Ground Noise Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Topology High Input Impedance when Vcc ≤ 1.5V Enhanced ESD Protection: 7 kV HBM on all pins 48-Pin 7 X 7 QFN (RGZ) The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the units bps (bits per second). APPLICATIONS • • • • Parallel Multipoint Data and Clock Transmission via Backplanes and Cables Cellular Base Stations Central Office Switches Network Switches and Routers LOGIC DIAGRAM (POSITIVE LOGIC) LOGIC DIAGRAM (POSITIVE LOGIC) SN65MLVD048 Channel 1 1FSEN 1A 1R 1B 1RE PDN 2FSEN – 4FSEN 3 2A – 4A Channels 2 - 4 2R – 4R 3 2RE – 4RE 3 2B – 4B DESCRIPTION The SN65MLVD048 is a quad-channel M-LVDS receiver. This device is designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which is optimized to operate at signaling rates up to 250 Mbps. Each receiver channel is controlled by a receive enable (RE). When RE = low, the corresponding channel is enabled; when RE = high, the corresponding channel is disabled. The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers implement a failsafe by using an offset threshold. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges. The devices are characterized for operation from –40°C to 85°C. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009, Texas Instruments Incorporated SN65MLVD048 SLLS903 – DECEMBER 2009 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PIN FUNCTIONS PIN NAME I/O NO. 1R––4R 36, 33, 29, 26 O DESCRIPTION Data output from receivers 1A–4A 47, 3, 9, 13 I/O M-LVDS bus non-inverting input/output 1B–4B 48, 4, 10, 14 I/O M-LVDS bus inverting input/output GND 6, 7, 18, 23, 27, 31, 34, 38, 43 I Circuit ground. ALL GND pins must be connected to ground. VCC 2, 11, 15, 16, 24, 37, 45, 46 I Supply voltage. ALL VCC pins must be connected to supply. 40, 42, 19, 21 I Receiver enable, active low, enables individual receivers. When this pin is left floating, internally this pin will be pulled to logic HIGH. 1RE–4RE Failsafe enable pin. When this pin is left floating, internally this pin will be pulled to logic HIGH. 1FSEN–4FSEN 39, 41, 20, 22 I This pin enables the Type 2 receiver for the respective channel. xFSEN = L → Type 1 receiver inputs xFSEN = H → Type 2 receiver inputs Power Down pin. When this pin is left floating, internally this pin will be pulled to logic LOW. PDN When PDN is HIGH, the device is powered up. 30 When PDN is LOW, the device overrides all other control and powers down. All outputs are Hi-Z NC 1, 5, 8, 12, 17, 25, 28, 32, 35 NC 44 Not Connected. Internal TI Test pin. This pin must be left unconnected. PowerPAD™ – Connected to GND Not Connected 36 35 34 33 32 31 30 29 28 27 26 25 1R NC GND 2R NC GND PDN 3R NC GND 4R NC 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 4A 4B VCC VCC NC GND 3RE 3FSEN 4RE 4FSEN GND VCC NC VCC 2A 2B NC GND GND NC 3A 3B VCC NC 48 47 46 45 44 43 42 41 40 39 38 37 1B 1A VCC VCC NC GND 2RE 2FSEN 1RE 1FSEN GND VCC RGZ PACKAGE (TOP VIEW) 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 SN65MLVD048 www.ti.com SLLS903 – DECEMBER 2009 Table 1. DEVICE FUNCTION TABLE INPUTS (1) (1) OUTPUT (1) RECEIVER TYPE VID = VA – VB PDN FSEN RE VID > 35 mV H L L Type 1 R H –35 mV ≤ VID ≤ 35 mV H L L Type 1 ? VID < – 35 mV H L L Type 1 L VID > 135 mV H H L Type 2 H 65 mV ≤ VID ≤ 135 mV H H L Type 2 ? VID < 65 mV H H L Type 2 L Open Circuit H L L Type 1 ? Open Circuit H H L Type 2 L X H X H X Z X H X OPEN X Z X L X X X Z H=high level, L=low level, Z=high impedance, X=Don’t care, ?=indeterminate ORDERING INFORMATION (1) PART NUMBER SN65MLVD048RGZR SN65MLVD048RGZT (1) FUNCTION PART MARKING M-LVDS Type 1 and 2 Receiver PACKAGE / CARRIER MLVD048 48-Pin QFN / Tape and Reel MLVD048 48-Pin QFN / Small Tape and Reel For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. PACKAGE DISSIPATION RATINGS (1) PACKAGE 48-Pin QFN (RGZ) (1) (2) PCB TYPE TA ≤ 25°C POWER RATING DERATING FACTOR (2) ABOVE TA = 25°C Low-K 1298 mW 12.98 mW/°C 519 mW High-K 3448 mW 34.48 mW/°C 1379 mW TA = 85°C POWER RATING The thermal dissipations are in the consideration of soldering down the powerPAD without via on each type of boards. This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. THERMAL CHARACTERISTICS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RθJB Junction-to-board thermal resistance 9 °C/W RθJC Junction-to-case thermal resistance 20 °C/W RθJP Junction-to-pad thermal resistance PD Device power dissipation 1.37 RE at 0 V, CL = 15 pF, VID = 400 mV, 125 MHz °C/W 339 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 mW 3 SN65MLVD048 SLLS903 – DECEMBER 2009 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Input voltage range Output voltage range (4) UNIT V RE, FSEN –0.5 to 4 V A or B –1.8 to 4 V R Electrostatic discharge (2) (3) VALUE –0.5 to 4 Supply voltage range (2) VCC (1) (1) Human-body model (3) All other pins Charged-device model (4) All pins –0.3 to 4 V ±7 kV ±1.5 kV Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal. Tested in accordance with JEDEC Standard 22, Test Method A114-E. Bus pin stressed with respect to a common connection of GND and VCC. Tested in accordance with EIA-JEDEC JESD22-C101D. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX VCC Supply voltage 3 3.3 3.6 V VIH High-level input voltage 2 VCC V VIL Low-level input voltage GND 0.8 V VA or VB Voltage at any bus terminal –1.4 3.8 V |VID| Magnitude of differential input voltage 0.05 VCC V VIC Differential common-mode input voltage –1 3.4 V RL Differential load resistance 30 1/tUI Signaling rate 250 Mbps TA Operating free-air temperature 85 °C Ω 50 –40 UNIT DEVICE ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER ICC (1) 4 TEST CONDITIONS Supply current RE at 0 V for all channels CL = 15 pF, VID = 400 mV, 125 MHz Power down PDN = L MIN TYP (1) MAX UNIT 86 94 mA 0.75 1.5 mA All typical values are at 25°C and with a 3.3-V supply voltage. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 SN65MLVD048 www.ti.com SLLS903 – DECEMBER 2009 RECEIVER ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER VIT+ VIT– VHYS MIN TYP (1) TEST CONDITIONS MAX Positive-going differential input voltage threshold Type 1 35 Type 2 135 Negative-going differential input voltage threshold Type 1 Differential input voltage hysteresis (VIT+ – VIT–) Type 1 25 Type 2 0 Type 2 –35 See Table 2 and Table 3 UNIT mV mV 65 mV VOH High-level output voltage IOH = –8 mA VOL Low-level output voltage IOL = 8 mA IIH High-level input current VIH = 2 V to VCC –10 IIL Low-level input current VIL = GND to 0.8 V –10 IOZ High-impedance output current VO = 0 V or VCC –10 15 μA IA or IB Receiver input current One input (VA or VB) = –1.4 V or 3.8 V, Other input = 1.2 V –20 20 μA IAB Receiver differential input current (IA – IB) VA = VB = –1.4 V or 3.8 V –4 4 μA IA(OFF) or IB(OFF) Receiver input current One input (VA or VB) = –1.4 V or 3.8 V, Other input = 1.2 V, VCC = GND or 1.5 V –32 32 μA IAB(OFF) Receiver power-off differential input current (IA – IB) VA = VB = –1.4 V or 3.8 V, VCC = GND or 1.5 V –4 4 μA CA or CB Input capacitance VI = 0.4sin(30E6πt) + 0.5V, (2) Other input at 1.2 V CAB Differential input capacitance CA/B Input capacitance balance, (CA/CB) (1) (2) VAB = 0.4sin(30E6πt) + 0.5 V 2.4 V 0.4 μA 5 (2) pF 3 0.99 V μA pF 1.01 All typical values are at 25°C and with a 3.3-V supply voltage. HP4194A impedance analyzer (or equivalent) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 5 SN65MLVD048 SLLS903 – DECEMBER 2009 www.ti.com RECEIVER SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 2 6 ns tPHL Propagation delay time, high-to-low-level output 2 6 ns tr Output signal rise time 1 2.3 tf Output signal fall time CL = 15 pF, See Figure 2 tsk(p) Pulse skew (|tPHL – tPLH|) tsk(pp) Part-to-part skew tjit(per) Period jitter, rms (1 standard deviation) (2) tjit(c-c) Cycle-to-cycle jitter, rms (2) tjit(det) Deterministic jitter (2) 1 2.3 Type 1 35 270 Type 2 150 460 All channels switching, 125 MHz clock input (3), See Figure 4 Type 1 Type 2 Type 1 All channels switching, 250 Mbps 215-1 PRBS input (3), See Figure 4 ns ps 800 ps 6 ps 13 ps 800 ps 945 ps 9 ps 8 ps tjit(ran) Random jitter (2) tPZH Enable time, high-impedance-to-high-level output CL = 15 pF, See Figure 3 15 ns tPZL Enable time, high-impedance-to-low-level output CL = 15 pF, See Figure 3 15 ns tPHZ Disable time, high-level-to-high-impedance output CL = 15 pF, See Figure 3 10 ns tPLZ Disable time, low-level-to-high-impedance output CL = 15 pF, See Figure 3 10 ns (1) (2) (3) 6 Type 2 All typical values are at 25°C and with a 3.3-V supply voltage. Jitter is ensured by design and characterization. Stimulus jitter has been subtracted from the numbers. tr = tf = 0.5ns (10% to 90%) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 SN65MLVD048 www.ti.com SLLS903 – DECEMBER 2009 EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS Receiver Enable VCC 360 kW 400 W RE 7V Receiver Output VCC Receiver Input VCC 100 kW 100 kW 250 kW 250 kW 10 W R B A 10 W 200 kW 200 kW 7V Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 7 SN65MLVD048 SLLS903 – DECEMBER 2009 www.ti.com PARAMETER MEASUREMENT INFORMATION IA A IO R V ID (V A +V B )/2 V CM B VA VO IB VB Figure 1. Receiver Voltage and Current Definitions Table 2. Type-1 Receiver Input Threshold Test Voltages APPLIED VOLTAGES (1) RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMON-MODE INPUT VOLTAGE RECEIVER OUTPUT (1) VIA VIB VID VIC 2.400 0.000 2.400 1.200 H 0.000 2.400 –2.400 1.200 L 3.400 3.365 0.035 3.3825 H 3.365 3.400 –0.035 3.3825 L –0.965 –1 0.035 –0.9825 H –1 –0.965 –0.035 –0.9825 L H= high level, L = low level, output state assumes receiver is enabled (RE = L) Table 3. Type-2 Receiver Input Threshold Test Voltages APPLIED VOLTAGES (1) 8 RESULTING DIFFERENTIAL INPUT VOLTAGE RESULTING COMMON-MODE INPUT VOLTAGE RECEIVER OUTPUT (1) VIA VIB VID VIC 2.400 0.000 2.400 1.200 0.000 2.400 –2.400 1.200 L 3.400 3.265 0.135 3.3325 H 3.4000 3.335 0.05065 3.3675 L –0.865 –1 0.135 –0.9325 H -0.935 –1 0.065 –0.9675 L H H= high level, L = low level, output state assumes receiver is enabled (RE = L) Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 SN65MLVD048 www.ti.com SLLS903 – DECEMBER 2009 VID VA CL 15 pF VB VO VA 1.2 V VB 0.8 V VID 0.4 V 0V -0.4 V tPHL tPLH VO 90% 10% tf tr VOH VCC 2 VOL A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, Frequency = 1 MHz, duty cycle = 50 ± 5%. CL is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within 2 cm of the D.U.T. B. The measurement is made on test equipment with a –3dB bandwidth of at least 1 GHz. Figure 2. Receiver Timing Test Circuit and Waveforms Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 9 SN65MLVD048 SLLS903 – DECEMBER 2009 www.ti.com 1.2 V B RL 499 W A CL 15 pF Inputs RE VO VTEST VTEST VCC 0.8 V A VCC VCC 2 0V RE tPZL tPLZ VO VCC VCC V 2 + 0.5 V OL VOL VTEST 0V 1.6 V A VCC VCC 2 0V RE tPZH VO tPHZ VOH VOH VCC 2 0V 0.5 V A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, frequency = 1 MHz, duty cycle = 50 ± 5%. B. RL is 1% tolerance, metal film, surface mount, and located within 2 cm of the D.U.T C. CL is the instrumentation and fixture capacitance within 2 cm of the D.U.T. and ±20%. The measurement is made on test equipment with a –3dB bandwidth of at least 1GHz. Figure 3. Receiver Enable/Disable Time Test Circuit and Waveforms 10 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 SN65MLVD048 www.ti.com SLLS903 – DECEMBER 2009 INPUTS Type 1 VA - VB 0.2 Vpk Type 2 0.4 Vpk CLOCK INPUT VA - VB 1/fo VCM 1V Period Jitter IDEAL OUTPUT VOH VCC /2 VOL VA 1/fo PRBS INPUT ACTUAL OUTPUT V OH VB VCC/2 VOL Peak to Peak Jitter VOH tc(n) OUTPUT tjit(per) = | tc(n) - 1/fo | VCC/2 VOL t jit(pp) Cycle to Cycle Jitter OUTPUT VOH VCC /2 VOL tc(n) tc(n+1) tjit(cc) = | tc(n) - tc(n+1)| A. All input pulses are supplied by the Agilent 81250 Parallel BERT Stimulus System with plug-in E4832A. B. The cycle-to-cycle jitter measurement is made on a TEK TDS6604 running TDSJIT3 application software. C. All other jitter measurements are made with an Agilent Infiniium DCA-J 86100C Digital Communications Analyzer. D. Period jitter and cycle-to-cycle jitter are measured using a 125-MHz 50 ± 1% duty cycle clock input. Measured over 75K samples. E. Deterministic jitter and random jitter are measured using a 250-Mbps 215 -1 PRBS input. Measured over BER = 10 -12 Figure 4. Receiver Jitter Measurement Waveforms Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 11 SN65MLVD048 SLLS903 – DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY RECEIVER (TYPE-1) PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 100 ICC - Supply Current - mA 80 Type 1 60 Type 2 40 VCC = 3.3 V, TA = 25°C, VID = 400 mV (Type 1)/800 mV (Type2), VIC = 1 V 20 0 PD - Propagation Delay Time - ns 5 50 75 100 f - Frequency - MHz tPHL 4 3.5 125 -40 25 85 TA - Free-Air Temperature - °C Figure 5. Figure 6. RECEIVER (TYPE-2) PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE RECEIVER (TYPE-1) TRANSITION TIME vs FREE-AIR TEMPERATURE 3 tr/tf - Rising/Falling Transition Time - ns 4.5 VCC = 3.3 V, f = 1 MHz, CL = 15 pF, VID = 800 mV, VIC = 1 V tPLH 4 tPHL 3.5 3 -40 25 85 TA - Free-Air Temperature - °C 2.5 VCC = 3.3 V, f = 1 MHz, CL = 15 pF, VID = 400 mV, VIC = 1 V tr 2 tf 1.5 1 Figure 7. 12 tPLH 3 25 5 PD - Propagation Delay Time - ns 4.5 VCC = 3.3 V, f = 1 MHz, CL = 15 pF, VID = 400 mV, VIC = 1 V -40 25 85 TA - Free-Air Temperature - °C Figure 8. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 SN65MLVD048 www.ti.com SLLS903 – DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) RECEIVER (TYPE-2) TRANSITION TIME vs FREE-AIR TEMPERATURE RECEIVER (TYPE-1) TRANSITION TIME vs OUTPUT LOAD CAPACITOR 2.5 3 VCC = 3.3 V, f = 1 MHz, CL = 15 pF, VID = 800 mV, VIC = 1 V tr/tf - Rising/Falling Transition Time - ns tr/tf - Rising/Falling Transition Time - ns 3 tr 2 tf 1.5 -40 tr tf 1.5 1 0.5 25 85 TA - Free-Air Temperature - °C 4.7 6.8 8.2 12 CL - Output Load Capacitor - pF Figure 9. Figure 10. RECEIVER (TYPE-2) TRANSITION TIME vs OUTPUT LOAD CAPACITOR ADDED RECEIVER PEAK-TO-PEAK JITTER vs SIGNALING RATE 15 800 3 VCC = 3.3 V, TA = 25°C, VCC = 3.3 V, TA = 25°C, f = 1 MHz, VID = 800 mV, VIC = 1 V 15 tjit(pp) - Peak-to-Peak - ps tr/tf - Rising/Falling Transition Time - ns 2 0 1 2.5 2.5 VCC = 3.3 V, TA = 25°C, f = 1 MHz, VID = 400 mV, VIC = 1 V tr 2 1.5 tf 1 600 2 -1 PRBS NRZ VID = 400 mV(Type 1)/800 mV(Type2), VIC = 1 V Type 2 400 Type 1 200 0.5 0 4.7 6.8 8.2 12 CL - Output Load Capacitor - pF 15 0 50 Figure 11. 100 150 200 Signaling Rate - Mbps 250 Figure 12. Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 13 SN65MLVD048 SLLS903 – DECEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) ADDED RECEIVER PERIOD JITTER vs CLOCK FREQUENCY ADDED RECEIVER CYCLE-TO-CYCLE JITTER vs CLOCK FREQUENCY 3 tjit(per) rms - Period Jitter - ps 2.5 Type 1 2 1.5 Type 2 1 0.5 VCC = 3.3 V, TA = 25°C, VID = 400 mV (Type 1)/800 mV (Type2), VIC = 1 V tjit(c-c) - Cycle-to-Cycle Jitter - ps 15 Type 2 10 Type 1 5 VCC = 3.3 V, TA = 25°C, VID = 400 mV (Type 1)/800 mV (Type2), VIC = 1 V 0 0 50 75 100 125 fCLK - Clock Frequency - MHz 50 Figure 13. 75 100 fCLK - Clock Frequency - MHz 125 Figure 14. EYE PATTERNS Figure 15. SN65MLVD048 Output (VCC = 3.3 V, VID = 400 mV) 250 Mbps 215–1 PRBS, Receiver Type 1 14 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 SN65MLVD048 www.ti.com SLLS903 – DECEMBER 2009 TYPICAL CHARACTERISTICS (continued) Figure 16. SN65MLVD048 Output (VCC = 3.3 V, VID = 800 mV) 250 Mbps 215–1 PRBS, Receiver Type 2 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s) :SN65MLVD048 15 PACKAGE OPTION ADDENDUM www.ti.com 21-Dec-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN65MLVD048RGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR SN65MLVD048RGZT ACTIVE VQFN RGZ 48 250 CU NIPDAU Level-3-260C-168 HR Green (RoHS & no Sb/Br) Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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