SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997 D D D D D D description The ’ABT853 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR) output indicates whether or not an error in the B data has occurred. The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively isolated. The ’ABT853 transceivers provide true data at their outputs. OEA A1 A2 A3 A4 A5 A6 A7 A8 ERR CLR GND 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC B1 B2 B3 B4 B5 B6 B7 B8 PARITY OEB LE SN54ABT853 . . . FK PACKAGE (TOP VIEW) A3 A4 A5 NC A6 A7 A8 4 5 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 B3 B4 B5 NC B6 B7 B8 CLR GND NC LE OEB PARITY D SN54ABT853 . . . JT OR W PACKAGE SN74ABT853 . . . DB, DW, NT, OR PW PACKAGE (TOP VIEW) A2 A1 OEA NC V CC B1 B2 D State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 500 mA Per JESD 17 Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C High-Drive Outputs (–32-mA IOH, 64-mA IOL) High-Impedance State During Power Up and Power Down Parity-Error Flag With Parity Generator/Checker Latch for Storage of Parity-Error Flag Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), Ceramic Flat (W) Package, and Plastic (NT) and Ceramic (JT) DIPs ERR D NC – No internal connection A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC-ΙΙB is a trademark of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997 description (continued) The SN54ABT853 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ABT853 is characterized for operation from –40°C to 85°C. FUNCTION TABLE INPUTS OUTPUTS AND I/Os Ai Σ OF H Bi† Σ OF H A B NA NA A B NA NA FUNCTION OEA CLR LE L H X X H L X L NA H L H H NA X X NA NA NC Store error flag X X L H X X X NA NA H Clear error flag register H H X L H X X L L Odd X L H Even H L H L X Odd Even Odd Even L NA H H L A data to B bus and generate parity B data to A bus and check parity NC X Z Z H Z Isolation§ (parity check) H L Odd X PARITY ERR‡ OEB NA NA H A Even NA L A data to B bus and generate inverted parity NA = not applicable, NC = no change, X = don’t care † Summation of high-level inputs includes PARITY along with Bi inputs. ‡ Output states shown assume ERR was previously high. § In this mode, ERR (when clocked) shows inverted parity of the A bus. logic symbol¶ LE CLR OEA OEB A1 A2 A3 A4 A5 A6 A7 A8 13 11 1 14 2 Φ LE 10 ERR CLR OEA OEB PARITY 1 1 23 22 4 21 5 20 6 A Bus 19 B Bus 7 18 8 17 8 8 ¶ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. 2 15 3 9 ERR POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 16 PARITY B1 B2 B3 B4 B5 B6 B7 B8 SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997 logic diagram (positive logic) 2–9 A1– A8 8x 8 23–16 8 B1–B8 EN 8x 8 EN 14 OEB 15 1 OEA PARITY 8 8 MUX 1 1 2k 9 1 P 1 G1 10 13 LE ERR 11 CLR Pin numbers shown are for the DB, DW, JT, NT, PW, and W packages. ERROR-FLAG FUNCTION TABLE INPUTS INTERNAL TO DEVICE OUTPUT PRESTATE POINT P ERRN–1† CLR LE L L H L L H H H X L H X OUTPUT ERR L H L X L X L L H H H X X H L L H H FUNCTION Pass Sample Clear Store † The state of ERR before changes at CLR, LE, or point P POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997 error-flag waveforms H OEB L H OEA L Even Bi + PARITY Odd H LE L H CLR L H ERR L Pass Store Sample Clear absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high or power-off state, VO . . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V Current into any output in the low state, IO: SN54ABT853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74ABT853 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997 recommended operating conditions (see Note 3) SN54ABT853 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage VOH IOH High-level output voltage ERR High-level output current Except ERR IOL ∆t/∆v Low-level output current ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage SN74ABT853 MIN 2 2 0.8 Input voltage 0 Input transition rise or fall rate Outputs enabled UNIT V V 0.8 V VCC 5.5 V –24 –32 mA 48 64 mA 10 10 ns/V VCC 5.5 0 µs/V 200 125 –40 V 85 °C NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH All outputs except ERR TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –3 mA VCC = 5 V, VCC = 4 4.5 5V VOL Vhys IOH II VCC = 4 4.5 5V MIN TA = 25°C TYP† MAX SN54ABT853 MIN –1.2 MAX SN74ABT853 MIN –1.2 –1.2 2.5 2.5 2.5 IOH = –3 mA IOH = –24 mA 3 3 3 2 2 IOH = – 32 mA IOL = 24 mA 2* IOL = 64 mA 0.55 0.55* Control inputs A or B ports VOH = 5.5 V VCC = 5 5.5 5V V, VI = VCC or GND V 2 0.55 VCC = 4.5 V, UNIT V 0.55 100 ERR V mV 50 50 50 ±1 ±1 ±1 ±100 ±100 ±100 µA µA IOZPU‡ VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA IOZPD‡ VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X ±50 ±50 ±50 µA IOZH§ IOZL§ VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.5 V Ioff VCC = 0, VCC = 5.5 V, VO = 5.5 V VI or VO ≤ 4.5 V VCC = 5.5 V, VO = 2.5 V Outputs high ICEX IO¶ ICC A or B ports Data inp inputs ts ∆ICC|| Control inputs Ci Control inputs VCC = 5.5 V, IO = 0, VI = VCC or GND VCC = 5.5 V, One input at 3.4 V,, Other inputs at VCC or GND 10 10 10 µA –10 –10 –10 µA ±100 µA 50 µA –200# mA 250 µA ±100 Outputs high 50 –50 –100 –200# 1 250 50 –50 –200# –50 450 Outputs low 24 38 38 38 mA Outputs disabled 0.5 250 450 250 µA Outputs enabled 1.5 1.5 1.5 mA Outputs disabled 50 50 50 µA 1.5 1.5 1.5 mA VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND VI = 2.5 V or 0.5 V VO = 2.5 V or 0.5 V 4.5 Cio A or B ports 10.5 * On products compliant to MIL-PRF-38535, this parameter does not apply. † All typical values are at VCC = 5 V. ‡ This parameter is characterized, but not production tested. § The parameters IOZH and IOZL include the input leakage current. ¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second. # This data sheet limit can vary among suppliers. || This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 6 MAX POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 pF pF SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) VCC = 5 V, TA = 25°C MIN tw Pulse duration tsu Setup time th Hold time LE high or low MAX SN54ABT853 MIN MAX SN74ABT853 MIN 3.5 3.5 3.5 4 9.4† 4 10.2 4 9.4† CLR before LE↓ 2 2 2 B or PARITY after LE↓ 0 0 0 CLR after LE↓ 3 3 3 CLR low B or PARITY before LE↓ UNIT MAX ns ns ns † This data sheet limit can vary among suppliers. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A or B B or A tPLH tPHL A PARITY tPLH tPHL OE PARITY CLR PARAMETER VCC = 5 V, TA = 25°C MIN MAX MIN MAX 4.8 4.8† 1.2 6.4 1.2 1 1 5.4 1 5.3 5.3† 2.1 9.5 2.1 13.3 2.1 11.2 2.5 9.7 2.5 11 2.5 11 1.8 8.5 1.8 13.6 1.8 10.5 2.3 8.6 2.3 11.7 2.3 10 ERR 1 5.5 1 6.3 1 6.2 5.1 1.8 6 ERR 1.8 1† 6.1 LE 1.8 1† 6.7 1 6.6 B or PARITY ERR 2 2.2† 10.1 11.8 2 2.2† 12.8 tPZH tPZL A or B or PARITY tPHZ tPLZ OE A or B or PARITY 1 1.5† 1.8† 5.8† OE 2.1† tPHL tPLH tPHL TYP SN74ABT853 MAX tPLH tPLH MIN SN54ABT853 1.2 5.8 11.5 2 2.2† 12.9 6.7† 9.5 1 1.5† 1.8† 8.2 2.1† 8.1 8.8 7.3 1 1.5† 1.8† 7.2 2.1† 5.8 11.7 9.8 6.7 7.9 UNIT ns ns ns ns ns ns ns ns † This data sheet limit can vary among suppliers. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ABT853, SN74ABT853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS SCBS198F – FEBRUARY 1991 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION 7V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 7V Open LOAD CIRCUIT 3V Timing Input 1.5 V 0V tw tsu 3V 1.5 V Input th 3V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V 1.5 V Input 1.5 V 0V VOH 1.5 V Output 1.5 V VOL VOH Output 1.5 V 1.5 V VOL 1.5 V 0V tPLZ Output Waveform 1 S1 at 7 V (see Note B) tPLH tPHL 1.5 V tPZL tPHL tPLH 3V Output Control Output Waveform 2 S1 at Open (see Note B) 1.5 V tPZH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 3.5 V VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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