SCAS166A − JUNE 1990 − REVISED APRIL 1996
D Members of the Texas Instruments
D
D
D
D
D
D
D
D
54ACT16833 . . . WD PACKAGE
74ACT16833 . . . DL PACKAGE
(TOP VIEW)
Widebus Family
Inputs Are TTL-Voltage Compatible
Parity Error Flag With Parity
Generator/Checker
Register for Storage of the Parity Error Flag
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include 300-mil Shrink
Small-Outline (DL) Packages Using 25-mil
Center-to-Center Pin Spacings and 380-mil
Fine-Pitch Ceramic Flat (WD) Packages
Using 25-mil Center-to-Center Pin Spacings
1OEB
1CLK
1ERR
GND
1A1
1A2
VCC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2ERR
2CLK
2OEB
description
The ’ACT16833 consist of two noninverting 8-bit
to 9-bit parity bus transceivers and are designed
for communication between data buses. For each
transceiver, when data is transmitted from the
A bus to the B bus, an odd-parity bit is generated
and output on the parity I/O pin (1PARITY or
2PARITY). When data is transmitted from the
B bus to the A bus, 1PARITY or 2PARITY is
configured as an input and combined with the
B-input data to generate an active-low error flag if
odd parity is not detected.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEA
1CLR
1PARITY
GND
1B1
1B2
VCC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2PARITY
2CLR
2OEA
The error (1ERR or 2ERR) output is configured as an open-collector output. The B-to-A parity error flag is
clocked into 1ERR or 2ERR on the low-to-high transition of the clock (1CLK or 2CLK) input. 1ERR or 2ERR is
cleared (set high) by taking the clear (1CLR or 2CLR) input low.
The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively
isolated. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity
is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic
capability.
The 74ACT16833 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16833 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74ACT16833 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
! "#$%&'( $#()(! (*#+&)#( $%++'( )! #* ,%-.$)#( ")'/ +#"%$! $#(*#+& #
!,'$*$)#(! ,'+ ' '+&! #* '0)! (!+%&'(! !)(")+" 1)++)(2/
+#"%$#( ,+#$'!!(3 "#'! (# ('$'!!)+.2 ($.%"' '!(3 #* )..
,)+)&''+!/
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1
SCAS166A − JUNE 1990 − REVISED APRIL 1996
FUNCTION TABLE
INPUTS
OUTPUT AND I/O
Bi†
Σ OF H
A
B
PARITY
ERR‡
OEA
CLR
CLK
L
H
X
X
Odd
Even
NA
NA
A
L
H
NA
A data to B bus and
generate parity
H
L
H
↑
NA
Odd
Even
B
NA
NA
H
L
B data to A bus and
check parity
X
X
L
X
X
X
X
NA
NA
H
Check error-flag register
H
No↑
X
L
No↑
X
H
↑
Odd
H
↑
Even
X
Odd
Even
H
L
H
L
X
NC
H
X
Z
Z
Z
A
H
L
H
Isolation§
L
NA
NA
NA = not applicable, NC = no change, X = don’t care
† Summation of high-level inputs includes PARITY along with Bi inputs.
‡ Output states shown assume ERR was previously high.
§ In this mode, ERR (when clocked) shows inverted parity of the A bus.
2
FUNCTION
OEB
Ai
Σ OF H
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NA
A data to B bus and
generate inverted parity
SCAS166A − JUNE 1990 − REVISED APRIL 1996
logic symbol†
1CLK
1CLR
1OEA
1OEB
2CLK
2CLR
2OEA
2OEB
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
Φ
PARITY XCVR
’ACT16833
2
55
56
1
1CLK
29
28
5
1OEB
54
1PARITY
1PARITY
2CLK
26
2ERR
2CLR
2ERR
2OEA
2OEB
31
2PARITY
1
1
52
6
51
8
49
9
48
10
A Bus
47
B Bus
12
45
13
44
14
43
15
1ERR
1OEA
27
30
3
1ERR
1CLR
8
8
1
1
42
16
41
17
40
19
38
20
A Bus
37
B Bus
21
36
23
34
24
33
8
8
2PARITY
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
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3
SCAS166A − JUNE 1990 − REVISED APRIL 1996
logic diagram (positive logic)
8
1A1−1A8
8x
8
1B1−1B8
EN
8x
8
EN
1OEB
1OEA
1
54
56
8
1PARITY
8
1 MUX
1
2k
9
1
P
1
G1
1CLK
1CLR
1D
C1
R
2
55
8
2A1−2A8
8x
3
8
1ERR
2B1−2B8
EN
8x
8
EN
2OEB
2OEA
28
31
29
8
2PARITY
8
1 MUX
1
1
2k
9
P
1
G1
2CLK
2CLR
4
1D
C1
R
27
30
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26
2ERR
SCAS166A − JUNE 1990 − REVISED APRIL 1996
ERROR FLAG FUNCTION TABLE
INPUTS
INTERNAL
TO DEVICE
OUTPUT
PRE-STATE
ERRn −1†
H
OUTPUT
ERR
CLR
CLK
POINT P‡
H
↑
H
H
↑
X
L
L
H
↑
L
X
L
FUNCTION
H
Sample
L
X
X
X
H
† The state of ERR before any changes at CLR, CLK, or point P
‡ Location of point P is shown on local diagram.
Clear
timing waveforms, error flag
H
OEB
L
H
L
OEA
Even
Bi + PARITY
Odd
tsu
th
H
L
CLK
tw
tw
tsu
CLR
H
L
tPHL
tPLH
H
ERR
L
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)§
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±450 mA
Maximum power package dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
§ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
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5
SCAS166A − JUNE 1990 − REVISED APRIL 1996
recommended operating conditions (see Note 3)
54ACT16833
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
∆t/∆v
Low-level output current
High-level input voltage
74ACT16833
2
2
Input transition rise or fall rate
V
V
0.8
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
UNIT
0.8
V
VCC
VCC
V
−24
−24
mA
24
24
mA
VCC
VCC
0
0
V
0
10
0
10
ns/V
−55
125
−40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH
ERR
TEST CONDITIONS
VO = VCC
All outputs
except ERR
II
IOZ‡
Control inputs
ICC
5
MAX
MIN
4.4
4.4
5.4
5.4
5.4
4.5 V
3.94
3.8
3.8
IOH = −24 mA
5.5 V
4.94
IOH = −75 mA†
5.5 V
4.5 V
IOL = 75 mA†
VI = VCC or GND
0.1
IO = 0
4.8
4.8
3.85
3.85
0.1
µA
V
0.1
0.1
0.1
0.1
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
±1
±1
µA
V
5.5 V
±0.1
5.5 V
±0.5
±5
±5
µA
5.5 V
8
80
80
µA
5.5 V
0.9
1
1
mA
Ci
Control inputs
VI = VCC or GND
5V
3.5
pF
Cio
A or B ports,
PARITY
VO = VCC or GND
5V
11.5
pF
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
(*#+&)#( $#($'+(! ,+#"%$! ( ' *#+&)4' #+
"'!3( ,)!' #* "'4'.#,&'(/ )+)$'+!$ ")) )(" #'+
!,'$*$)#(! )+' "'!3( 3#).!/ '0)! (!+%&'(! +'!'+4'! ' +3 #
$)(3' #+ "!$#((%' '!' ,+#"%$! 1#% (#$'/
6
UNIT
5.5 V
5.5 V
VO = VCC or GND
VI = VCC or GND,
MAX
5
4.4
One input at 3.4 V,
Other inputs at VCC or GND
∆ICC§
0.5
MIN
74ACT16833
5.5 V
IOL = 24 mA
A or B ports
54ACT16833
4.5 V
IOL = 50 µA
A
VOL
TA = 25°C
MIN
TYP
MAX
5.5 V
IOH = −50 µA
A
VOH
VCC
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SCAS166A − JUNE 1990 − REVISED APRIL 1996
timing requirements over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1 and timing waveforms)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, Bi + PARITY low after CLK↑
54ACT16833
MIN
MAX
74ACT16833
MIN
CLK high or low
4
4
4
CLR low
4
4
4
Bi + PARITY
7.5
7.5
7.5
CLR inactive
1.5
1.5
1.5
0
0
0
MAX
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1 and timing waveforms)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
A
PARITY
tPZH
tPZL
OEB or OEA
A or B
tPHZ
tPLZ
OEB or OEA
A or B
tPLH
tPHL
MIN
CLR
ERR
CLK
tPLH
tPHL
OEA
PARITY
tPZH
tPZL
OEB
PARITY
tPHZ
tPLZ
OEB
PARITY
TA = 25°C
TYP
MAX
54ACT16833
MIN
MAX
74ACT16833
MIN
MAX
4
7.2
9.2
4
10.4
4
10.4
3.2
6.6
9.6
3.2
10.7
3.2
10.7
3.9
7.9
12
3.9
13.5
3.9
13.5
4.2
8.3
12.4
4.2
13.8
4.2
13.8
3.1
6.7
10.1
3.1
11.2
3.1
11.2
3.8
7.9
11.6
3.8
13
3.8
13
5.5
7.8
10
5.5
10.8
5.5
10.8
5
7.1
9.3
5
10.1
5
10.1
10.7
13.1
15.4
10.7
15.8
10.7
15.8
4.6
7.8
10.3
4.6
11.6
4.6
11.6
4
8
11.8
4
13.2
4
13.2
4.3
8.5
12.3
4.3
13.6
4.3
13.6
2.6
5.7
8.5
2.6
9.5
2.6
9.5
3.4
6.8
9.8
3.4
10.7
3.4
10.7
5.6
7.9
9.5
5.6
10.2
5.6
10.2
5.1
7.2
9.1
5.1
9.7
5.1
9.7
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
A to B
Outputs enabled
Cpd
Power dissipation capacitance per transceiver
UNIT
64
B to A
A to B
Outputs disabled
TYP
72
CL = 50 pF,
B to A
f = 1 MHz
6
pF
10.5
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"'!3( ,)!' #* "'4'.#,&'(/ )+)$'+!$ ")) )(" #'+
!,'$*$)#(! )+' "'!3( 3#).!/ '0)! (!+%&'(! +'!'+4'! ' +3 #
$)(3' #+ "!$#((%' '!' ,+#"%$! 1#% (#$'/
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7
SCAS166A − JUNE 1990 − REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
1.5 V
Data Input
3V
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
Input
1.5 V
1.5 V
0V
tPHL
tPLH
In-Phase
Output
50% VCC
Out-of-Phase
Output
50% VCC
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
50% VCC
VOL
tPLH
tPHL
3V
Output
Waveform 2
S1 at GND
(see Note B)
VOH
50% VCC
VOL
1.5 V
1.5 V
50% VCC
[ VCC
20% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
8
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