SN54ACT74, SN74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS520E – AUGUST 1995 – REVISED JANUARY 2000 D D D SN54ACT74 . . . J OR W PACKAGE SN74ACT74 . . . D, DB, N, OR PW PACKAGE (TOP VIEW) Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic Small-Outline (DW) Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK) and Flatpacks (W), and Standard Plastic (N) and Ceramic (J) DIPs 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q description The ’ACT74 dual positive-edge-triggered devices are D-type flip-flops. 1D 1CLR NC VCC 2CLR SN54ACT74 . . . FK PACKAGE (TOP VIEW) A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs. 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2D NC 2CLK NC 2PRE 1Q GND NC 2Q 2Q 1CLK NC 1PRE NC 1Q The SN54ACT74 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74ACT74 is characterized for operation from –40°C to 85°C. NC – No internal connection FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X L H L L X X H† H† H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 † This configuration is unstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ACT74, SN74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS520E – AUGUST 1995 – REVISED JANUARY 2000 logic symbol† 1PRE 1CLK 1D 1CLR 2PRE 2CLK 2D 2CLR 4 5 S 3 1Q C1 2 1D 1 6 1Q R 10 9 11 2Q 12 8 13 2Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, N, PW, and W packages. logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ACT74, SN74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS520E – AUGUST 1995 – REVISED JANUARY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±200 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 3) SN54ACT74 MAX MIN MAX 4.5 5.5 4.5 5.5 VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 0 VO IOH Output voltage 0 High-level output current IOL ∆t/∆v Low-level output current High-level input voltage SN74ACT74 MIN 2 2 0.8 Input transition rise or fall rate 0 UNIT V V 0.8 V VCC VCC V –24 –24 mA 24 24 mA 8 ns/V VCC VCC 8 0 0 0 V TA Operating free-air temperature –55 125 –40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ACT74, SN74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS520E – AUGUST 1995 – REVISED JANUARY 2000 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 50 µA VOH 24 mA IOH = –24 IOH = –50 mA† IOH = –75 mA† SN54ACT74 SN74ACT74 MIN 4.5 V 4.4 4.49 4.4 5.5 V 5.4 5.49 5.4 5.4 4.5 V 3.86 3.7 3.76 5.5 V 4.86 4.7 4.76 5.5 V MIN MAX MIN IOL = 24 mA IOL = 50 mA† IOL = 75 mA† ∆ICC‡ One input at 3.4 V, Other inputs at GND or VCC IO = 0 V 3.85 4.5 V 0.001 0.1 0.1 5.5 V 0.001 0.1 0.1 0.1 0.1 4.5 V 0.36 0.5 0.44 5.5 V 0.36 0.5 0.44 V 1.65 5.5 V VI = VCC or GND VI = VCC or GND, UNIT 3.86 5.5 V II ICC MAX 4.4 5.5 V IOL = 50 µA VOL TA = 25°C TYP MAX VCC 1.65 5.5 V ±0.1 ±1 ±1 µA 5.5 V 2 40 20 µA 1.6 1.5 mA 5.5 V 0.6 Ci VI = VCC or GND 5V 3 † Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms. ‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC. pF timing characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX fclock Clock frequency 0 tw Pulse duration tsu Set p time, time data before CLK↑ Setup th Hold time, data after CLK↑ 145 SN54ACT74 SN74ACT74 MIN MAX MIN MAX 0 145 0 145 PRE or CLR low 5 7 6 CLK 5 7 6 Data 3 4 3.5 PRE or CLR inactive 0 0.5 0 1 1 1 UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ACT74 PARAMETER fmax tPLH tPHL tPLH tPHL 4 FROM (INPUT) TO (OUTPUT) PRE or CLR Q or Q CLK Q or Q POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TA = 25°C MIN TYP MAX MIN MAX 145 210 1 5.5 9.5 85 1 11.5 1 6 10 1 12.5 1 7.5 11 1 14 1 6 10 1 12 UNIT MHz ns ns SN54ACT74, SN74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS520E – AUGUST 1995 – REVISED JANUARY 2000 switching characteristics over recommended operating free-air temperature (unless otherwise noted) (see Figure 1) SN74ACT74 FROM (INPUT) PARAMETER fmax tPLH tPHL tPLH TO (OUTPUT) PRE or CLR Q or Q CLK Q or Q tPHL TA = 25°C MIN TYP MAX MIN 145 210 125 3 5.5 9.5 2.5 10.5 3 6 10 3 11.5 4 7.5 11 4 13 3.5 6 10 3 11.5 MAX UNIT MHz ns ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance CL = 50 pF, TYP f = 1 MHz 45 UNIT pF PARAMETER MEASUREMENT INFORMATION 2 × VCC 500 Ω From Output Under Test CL = 50 pF (see Note A) S1 Open 500 Ω TEST S1 tPLH/tPHL Open tw LOAD CIRCUIT 3V 3V Input 1.5 V 0V 0V VOLTAGE WAVEFORMS tPHL VOH 50% VCC VOL 50% VCC 3V Timing Input tPLH tPHL Out-of-Phase Output 1.5 V 1.5 V tPLH In-Phase Output 1.5 V Input VOH 50% VCC VOL 50% VCC 1.5 V th tsu 0V 3V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. C. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. 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