SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995 • SN54ALS109A, SN54AS109A . . . J PACKAGE SN74ALS109A, SN74AS109A . . . D OR N PACKAGE (TOP VIEW) Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs TYPICAL MAXIMUM CLOCK FREQUENCY (MHz) TYPICAL POWER DISSIPATION PER FLIP-FLOP (mW) ′ALS109A 50 6 ′AS109A 129 29 TYPE 1CLR 1J 1K 1CLK 1PRE 1Q 1Q GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 2CLR 2J 2K 2CLK 2PRE 2Q 2Q description These devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together. 3 4 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2J 2K NC 2CLK 2PRE 1Q GND NC 2Q 2Q 1K 1CLK NC 1PRE 1Q 2CLR 1J 1CLR NC VCC SN54ALS109A, SN54AS109A . . . FK PACKAGE (TOP VIEW) NC – No internal connection The SN54ALS109A and SN54AS109A are characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS109A and SN74AS109A are characterized for operation from 0°C to 70°C. FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X H H† H L L X X X L H† H H ↑ L L L H H ↑ H L H H ↑ L H Q0 Q0 H H ↑ H H H L Toggle H H L X X Q0 Q0 † The output levels in this configuration are not specified to meet the minimum levels for VOH if the lows at PRE and CLR are near VIL maximum. Furthermore, this configuration is nonstable; that is, it does not persist when either PRE or CLR returns to its inactive (high) level. Copyright 1995, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995 logic symbol† 1PRE 1J 1CLK 5 S 2 4 2J 2CLK 2K 2CLR 7 1K 1K 2PRE 1Q C1 3 1CLR 6 1J 1 1Q R 11 14 10 2Q 12 9 13 2Q 15 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡ Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS109A . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74ALS109A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C ‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS109A VCC VIH Supply voltage VIL IOH Low-level input voltage IOL fclock tw Pulse duration High-level input voltage NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 UNIT V V 0.7 0.8 High-level output current – 0.4 – 0.4 Low-level output current 4 8 mA 34 MHz Clock frequency 0 PRE or CLR low tsu Set p time before CLK↑ Setup th TA Hold time after CLK↑ 2 SN74ALS109A MIN 30 0 15 15 CLK high 16.5 14.5 CLK low 16.5 14.5 Data 15 15 PRE or CLR inactive 10 10 Data Operating free-air temperature 0 – 55 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 0 mA ns ns 0 125 V ns 70 °C SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IIH IIL CLK, J, or K PRE or CLR CLK, J, or K PRE or CLR CLK, J, or K PRE or CLR SN54ALS109A TYP† MAX TEST CONDITIONS MIN VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = – 0.4 mA 5V VCC = 4 4.5 IOL = 4 mA IOL = 8 mA VCC = 5 5.5 5V V, VI = 7 V VCC = 5 5.5 5V V, VI = 2 2.7 7V VCC = 5 5.5 5V V, VI = 0 0.4 4V SN74ALS109A TYP† MAX MIN –1.5 VCC – 2 –1.5 VCC – 2 0.25 UNIT V V 0.4 0.25 0.4 0.35 0.5 0.1 0.1 0.2 0.2 20 20 40 40 – 0.2 – 0.2 – 0.4 – 0.4 V mA µA mA IO‡ VCC = 5.5 V, VO = 2.25 V – 20 –112 – 30 –112 mA ICC VCC = 5.5 V, See Note 1 2.4 4 2.4 4 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX§ SN54ALS109A MIN fmax tPLH tPHL tPLH MAX SN74ALS109A MIN 30 PRE or CLR Q or Q • DALLAS, TEXAS 75265 MAX 34 MHz 3 17 3 13 5 17 5 15 5 16 5 18 5 21 CLK Q or Q tPHL 5 20 § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 UNIT ns ns 3 SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54AS109A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74AS109A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54AS109A SN74AS109A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –2 –2 mA IOL fclock* Low-level output current 20 20 mA 105 MHz High-level input voltage 2 Clock frequency 0 PRE or CLR low tw* 2 Pulse duration CLK high tsu* Set p time before CLK↑ Setup th* TA Hold time after CLK↑ 90 4 4 4 4 5.5 5.5 Data 5.5 5.5 2 2 Data 0 Operating free-air temperature V 0 CLK low PRE or CLR inactive V ns ns 0 – 55 125 ns 0 70 °C * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54AS109A TYP‡ MAX TEST CONDITIONS MIN VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = – 2 mA VOL II VCC = 4.5 V, VCC = 5.5 V, IOL = 20 mA VI = 7 V IIH IIL CLK, J, or K PRE or CLR CLK, J, or K PRE or CLR VCC = 5 5.5 5V V, VI = 2 2.7 7V VCC = 5 5.5 5V V, VI = 0 0.4 4V SN74AS109A TYP‡ MAX MIN –1.2 VCC – 2 –1.2 VCC – 2 0.25 0.5 UNIT V V 0.25 0.5 V 0.1 0.1 mA 20 20 40 40 – 0.5 – 0.5 –1.8 –1.8 µA mA IO§ VCC = 5.5 V, VO = 2.25 V – 30 –112 – 30 –112 mA ICC VCC = 5.5 V, See Note 1 11.5 17 11.5 17 mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. NOTE 1: ICC is measured with J, K, CLK, and PRE grounded, then with J, K, CLK, and CLR grounded. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995 switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX† SN54AS109A SN74AS109A MIN fmax* tPLH tPHL tPLH MAX 90 PRE or CLR Q or Q MIN MAX 105 MHz 2 9 2 8 3.5 11.5 3.5 10.5 2.5 10 2.5 9 CLK Q or Q tPHL 3.5 10.5 3.5 9 * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. † For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns 5 SN54ALS109A, SN54AS109A, SN74ALS109A, SN74AS109A DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SDAS198B – APRIL 1982 – REVISED AUGUST 1995 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V Data Input tw th tsu 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 84000012A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 8400001EA ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC 8400001FA OBSOLETE CFP W 16 None Call TI Call TI JM38510/37102B2A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC JM38510/37102BEA ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC SN54ALS109AJ ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC SN54AS109AJ ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC SN74ALS109AD ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74ALS109ADR ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74ALS109AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74ALS109AN3 OBSOLETE PDIP N 16 None Call TI SN74ALS109ANSR ACTIVE SO NS 16 2000 Pb-Free (RoHS) CU NIPDAU Call TI Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74AS109AD ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74AS109ADR ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74AS109AN ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74AS109ANSR ACTIVE SO NS 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SNJ54ALS109AFK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC SNJ54ALS109AJ ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC SNJ54AS109AFK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC SNJ54AS109AJ ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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