SCES540A − JANUARY 2004 − REVISED FEBRUARY 2004 D Available in the Texas Instruments D D D D D D D D DCT OR DCU PACKAGE (TOP VIEW) NanoStar and NanoFree Packages Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub 1-V Operable Max tpd of 1.9 ns at 1.8 V Low Power Consumption, 10-µA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) 1CLK 1D 2Q GND 1 8 2 7 3 6 4 5 VCC 1Q 2D 2CLK YEP OR YZP PACKAGE (BOTTOM VIEW) GND 2Q 1D 1CLK 4 5 3 6 2 7 1 8 2CLK 2D 1Q VCC description/ordering information This dual positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION −40°C to 85°C ORDERABLE PART NUMBER PACKAGE† TA TOP-SIDE MARKING‡ NanoStar − WCSP (DSBGA) 0.23-mm Large Bump − YEP Tape and reel SN74AUC2G80YEPR NanoFree − WCSP (DSBGA) 0.23-mm Large Bump − YZP (Pb-free) Tape and reel SN74AUC2G80YZPR SSOP − DCT Tape and reel SN74AUC2G80DCTR U80_ _ _ VSSOP − DCU Tape and reel SN74AUC2G80DCUR UX_ _ _ _UX_ † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. ‡ DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site. DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar and NanoFree are trademarks of Texas Instruments. Copyright 2004, Texas Instruments Incorporated ! "#$ ! %#&'" ($) (#"! " !%$""! %$ *$ $! $+! !#$! !(( ,-) (#" %"$!!. ($! $"$!!'- "'#($ $!. '' %$$!) POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCES540A − JANUARY 2004 − REVISED FEBRUARY 2004 FUNCTION TABLE (each flip-flop) INPUTS CLK D OUTPUT Q ↑ H L ↑ L H L X Q0 logic diagram (positive logic) CLK C C C Q TG C C C C D TG TG TG C C C absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 2): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 102°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCES540A − JANUARY 2004 − REVISED FEBRUARY 2004 recommended operating conditions (see Note 3) VCC VIH VIL VI VO Supply voltage High-level input voltage MIN MAX 0.8 2.7 VCC = 0.8 V VCC = 1.1 V to 1.95 V VCC 0.65 × VCC VCC = 2.3 V to 2.7 V VCC = 0.8 V 1.7 V 0 Input voltage Output voltage IOL ∆t/∆v High-level output current Low-level output current V 0.7 0 3.6 V 0 VCC −0.7 V VCC = 0.8 V VCC = 1.1 V IOH V 0.35 × VCC VCC = 1.1 V to 1.95 V VCC = 2.3 V to 2.7 V Low-level input voltage UNIT −3 VCC = 1.4 V VCC = 1.65 V VCC = 2.3 V −5 VCC = 0.8 V VCC = 1.1 V 0.7 mA −8 −9 3 VCC = 1.4 V VCC = 1.65 V 5 VCC = 2.3 V 9 mA 8 Input transition rise or fall rate 20 ns/V TA Operating free-air temperature −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −100 µA IOH = −0.7 mA VOH VOL II Ioff ICC Ci D or CLK inputs VCC MIN 0.8 V to 2.7 V VCC−0.1 0.8 V MAX 1.1 V 0.8 1.4 V 1 IOH = −8 mA IOH = −9 mA 1.65 V 1.2 2.3 V 1.8 IOL = 100 µA IOL = 0.7 mA 0.8 V to 2.7 V V 0.2 0.25 IOL = 3 mA IOL = 5 mA 1.1 V 0.3 1.4 V 0.4 IOL = 8 mA IOL = 9 mA 1.65 V 0.45 2.3 V 0.6 VI = VCC or GND VI or VO = 2.7 V VI = VCC or GND, VI = VCC or GND IO = 0 UNIT 0.55 IOH = −3 mA IOH = −5 mA 0.8 V TYP† V 0 to 2.7 V ±5 µA 0 ±5 µA 10 µA 0.8 V to 2.7 V 2.5 V 2.5 pF † All typical values are at TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCES540A − JANUARY 2004 − REVISED FEBRUARY 2004 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 0.8 V TYP VCC = 1.2 V ± 0.1 V MIN MAX VCC = 1.5 V ± 0.1 V MIN MAX 200 VCC = 1.8 V ± 0.15 V MIN MAX 225 VCC = 2.5 V ± 0.2 V MIN UNIT MAX fclock tw Clock frequency 50 250 275 MHz Pulse duration, CLK high or low 2.4 1 1 1 1 ns tsu Setup time before CLK↑ 1 0.8 0.6 0.6 0.5 ns th Hold time, data after CLK↑ 0 0 0.1 0.1 0.5 ns switching characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) VCC = 0.8 V TO (OUTPUT) TYP MIN 50 200 5 1 fmax tpd CLK VCC = 1.2 V ± 0.1 V Q VCC = 1.5 V ± 0.1 V MAX MIN VCC = 1.8 V ± 0.15 V MAX MIN 225 3.9 0.8 TYP VCC = 2.5 V ± 0.2 V MAX 250 2.5 MIN 275 0.3 1 1.9 UNIT MAX MHz 0.3 1.3 ns switching characteristics over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) PARAMETER VCC = 1.8 V ± 0.15 V TO (OUTPUT) MIN fmax TYP VCC = 2.5 V ± 0.2 V MAX 250 tpd CLK 0.8 Q MIN 275 1.5 2.4 UNIT MAX ns 0.6 1.8 ns operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Data Cpd Power dissipation capacitance CLK Total 4 fclock = 10 MHz VCC = 0.8 V TYP VCC = 1.2 V TYP VCC = 1.5 V TYP VCC = 1.8 V TYP VCC = 2.5 V TYP 16.9 17.2 18.6 21.4 29.5 1.1 1.1 1.2 1.4 2.5 18 18.3 19.8 22.8 32 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT pF SCES540A − JANUARY 2004 − REVISED FEBRUARY 2004 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 RL From Output Under Test Open GND CL (see Note A) RL VCC 0.8 V 1.2 V ± 0.1 V 1.5 V ± 0.1 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V 1.8 V ± 0.15 V 2.5 V ± 0.2 V LOAD CIRCUIT TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND CL RL 15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF 2 kΩ 2 kΩ 2 kΩ 2 kΩ 2 kΩ 1 kΩ 500 Ω V∆ 0.1 V 0.1 V 0.1 V 0.15 V 0.15 V 0.15 V 0.15 V VCC Timing Input VCC/2 0V tw tsu VCC VCC/2 Input th VCC VCC/2 VCC/2 Data Input VCC/2 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC VCC/2 Input 0V tPHL tPLH VOH VCC/2 Output VCC/2 VOL Output Waveform 1 S1 at 2 × VCC (see Note B) VOH Output VCC/2 VCC/2 VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VCC/2 0V tPLZ tPZL VCC VCC/2 Output Waveform 2 S1 at GND (see Note B) VOL + V∆ VOL tPHZ tPZH tPLH tPHL VCC Output Control VCC/2 VCC/2 VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 PACKAGE OPTION ADDENDUM www.ti.com 25-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) SN74AUC2G80DCTR ACTIVE SM8 DCT 8 3000 None CU SNPB Level-1-235C-UNLIM SN74AUC2G80DCUR ACTIVE US8 DCU 8 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74AUC2G80YEPR ACTIVE WCSP YEP 8 3000 None SNPB Level-1-260C-UNLIM SN74AUC2G80YZPR ACTIVE WCSP YZP 8 3000 Pb-Free (RoHS) SNAGCU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS049B – MAY 1999 – REVISED OCTOBER 2002 DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 8 0,13 M 5 0,15 NOM ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ ÇÇÇÇÇ 2,90 2,70 4,25 3,75 Gage Plane PIN 1 INDEX AREA 1 0,25 4 0° – 8° 3,15 2,75 0,60 0,20 1,30 MAX Seating Plane 0,10 0,10 0,00 NOTES: A. B. C. D. 4188781/C 09/02 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion Falls within JEDEC MO-187 variation DA. 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