SN74AUCH32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES476 – AUGUST 2003
D
D
D
D
D
D
Member of the Texas Instruments
Widebus+ Family
Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub 1-V Operable
Max tpd of 2.8 ns at 1.8 V
Low Power Consumption, 40-µA Max ICC
D
D
D
D
±8-mA Output Drive at 1.8 V
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This 32-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for
1.65-V to 1.95-V VCC operation.
The SN74AUCH32374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop.
On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up
at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
–40°C to 85°C LFBGA – GKE
Tape and reel
SN74AUCH32374GKER
MK374
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SN74AUCH32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES476 – AUGUST 2003
GKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
terminal assignments
1
2
3
4
5
6
A
A
1Q2
1Q1
1OE
1CLK
1D1
1D2
B
B
1Q4
1Q3
GND
GND
1D3
1D4
C
C
1Q6
1Q5
1D6
D
1Q8
1Q7
VCC
GND
1D5
D
VCC
GND
1D7
1D8
E
2Q2
2Q1
GND
GND
2D1
2D2
F
2Q4
2Q3
2D4
2Q6
2Q5
VCC
GND
2D3
G
VCC
GND
2D5
2D6
H
2Q7
2Q8
2OE
2CLK
2D8
2D7
E
F
G
H
J
K
J
3Q2
3Q1
3OE
3CLK
3D1
3D2
K
3Q4
3Q3
GND
GND
3D3
3D4
L
3Q6
3Q5
VCC
GND
3D5
3D6
M
3Q8
3Q7
VCC
GND
3D7
3D8
M
N
4Q2
4Q1
GND
GND
4D1
4D2
N
P
4Q4
4Q3
4D4
R
4Q6
4Q5
VCC
GND
4D3
P
VCC
GND
4D5
4D6
R
T
4Q7
4Q8
4OE
4CLK
4D8
4D7
L
T
FUNCTION TABLE
(each flip-flop)
INPUTS
2
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES476 – AUGUST 2003
logic diagram (positive logic)
1OE
1CLK
A3
2OE
A4
2CLK
C1
1D1
A5
A2
1D
H3
H4
C1
1Q1
2D1
E5
To Seven Other Channels
3OE
3CLK
4OE
J4
J5
4CLK
1D
2Q1
To Seven Other Channels
J3
C1
3D1
E2
1D
J2
T3
T4
C1
3Q1
To Seven Other Channels
4D1
N5
1D
N2
4Q1
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
SN74AUCH32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES476 – AUGUST 2003
recommended operating conditions (see Note 3)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 0.8 V
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VIL
Low-level input voltage
VI
Input voltage
VO
∆t/∆v
2.7
VCC
0.65 × VCC
Output voltage
High-level output current
V
V
1.7
0
0.35 × VCC
V
0.7
3.6
V
Active state
0
V
3-state
0
VCC
3.6
VCC = 1.4 V
VCC = 1.65 V
Low-level output current
UNIT
0
VCC = 2.3 V
VCC = 0.8 V
IOL
MAX
0.8
VCC = 1.1 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 0.8 V
VCC = 1.1 V
IOH
MIN
–3
–5
mA
–8
–9
0.7
VCC = 1.1 V
VCC = 1.4 V
3
VCC = 1.65 V
VCC = 2.3 V
8
Input transition rise or fall rate
V
–0.7
5
mA
9
20
ns/V
TA
Operating free-air temperature
–40
85
°C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES476 – AUGUST 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
0.8 V to 2.7 V
IOH = –100 µA
IOH = –0.7 mA
VOH
VOL
II
IBHL‡
IBHH§
IBHLO¶
All inputs
MIN
TYP†
MAX
0.8 V
0.55
IOH = –3 mA
IOH = –5 mA
1.1 V
0.8
1.4 V
1
IOH = –8 mA
IOH = –9 mA
1.65 V
1.2
2.3 V
1.8
IOL = 100 µA
IOL = 0.7 mA
0.8 V to 2.7 V
V
0.2
0.8 V
0.25
IOL = 3 mA
IOL = 5 mA
1.1 V
0.3
1.4 V
0.4
IOL = 8 mA
IOL = 9 mA
1.65 V
0.45
2.3 V
0.6
VI = VCC or GND
VI = 0.35 V
±5
0 to 2.7 V
VI = 0.47 V
VI = 0.57 V
1.1 V
10
1.4 V
15
1.65 V
20
VI = 0.7 V
VI = 0.8 V
2.3 V
40
1.1 V
–5
VI = 0.9 V
VI = 1.07 V
1.4 V
–15
1.65 V
–20
VI = 1.7 V
2.3 V
–40
VI = 0 to VCC
IBHHO#
VI = 0 to VCC
Ioff
IOZ
VI or VO = 2.7 V
VO = VCC or GND
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
1.3 V
75
1.6 V
125
1.95 V
175
2.7 V
275
1.3 V
–75
1.6 V
–125
1.95 V
–175
2.7 V
–275
µA
A
µA
µA
A
µA
A
2.7 V
0.8 V to 2.7 V
2.5 V
V
A
µA
0
IO = 0
UNIT
VCC–0.1
3
±10
µA
±10
µA
40
µA
pF
Co
VO = VCC or GND
2.5 V
5
pF
† All typical values are at TA = 25°C.
‡ The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND and
then raising it to VIL max.
§ The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to VCC and
then lowering it to VIH min.
¶ An external driver must source at least IBHLO to switch this node from low to high.
# An external driver must sink at least IBHHO to switch this node from high to low.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
SN74AUCH32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES476 – AUGUST 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
VCC = 1.2 V
± 0.1 V
VCC = 0.8 V
TYP
MIN
VCC = 1.5 V
± 0.1 V
MAX
MIN
VCC = 1.8 V
± 0.15 V
MAX
250
MIN
MAX
250
VCC = 2.5 V
± 0.2 V
MIN
UNIT
MAX
fclock
tw
Clock frequency
85
250
250
MHz
Pulse duration, CLK high or low
5.9
1.9
1.9
1.9
1.9
ns
tsu
th
Setup time, data before CLK↑
1.4
1.2
0.7
0.6
0.6
ns
Hold time, data after CLK↑
0.1
0.4
0.4
0.4
0.4
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
TYP
MIN
85
250
fmax
VCC = 1.5 V
± 0.1 V
MAX
MIN
MAX
250
VCC = 1.8 V
± 0.15 V
MIN
TYP
VCC = 2.5 V
± 0.2 V
MAX
250
MIN
UNIT
MAX
250
MHz
tpd
CLK
Q
7.3
1
4.5
0.8
2.9
0.7
1.5
2.8
0.7
2.2
ns
ten
OE
Q
7
1.2
5.3
0.8
3.6
0.8
1.5
2.9
0.7
2.2
ns
tdis
OE
Q
8.2
2
7.1
1
4.8
1.4
2.7
4.5
0.5
2.2
ns
operating characteristics, TA = 25°C†
TEST
CONDITIONS
PARAMETER
Cpd‡
(each
output)
Power
dissipation
capacitance
Outputs
enabled,
1 output
switching
1 fdata = 5 MHz
1 fclk = 10 MHz
1 fout = 5 MHz
OE = GND
CL = 0 pF
VCC = 0.8 V
TYP
24
VCC = 1.2 V
TYP
VCC = 1.5 V
TYP
VCC = 1.8 V
TYP
VCC = 2.5 V
TYP
UNIT
24.1
26.2
31.2
pF
24
Outputs
disabled,
1 clock
and 1
data
switching
1 fdata = 5 MHz
1 fclk = 10 MHz
Power
Cpd
fout = not
dissipation
7.5
7.5
8
9.4
13.2
pF
switching
(Z)
capacitance
OE = VCC
CL = 0 pF
1 fdata = 0 MHz
Outputs
1 fclk = 10 MHz
Cpd§
disabled,
Power
fout = not
clock
dissipation
13.8
13.8
14
14.7
17.5
pF
(each
switching
clock) capacitance only
OE = VCC
switching
CL = 0 pF
† Total device Cpd for multiple (n) outputs switching and (y) clocks inputs switching = {n * Cpd (each output)} + {y * Cpd (each clock)}.
‡ Cpd (each output) is the Cpd for each data bit (input and output circuitry) as it operates at 5 MHz (Note: the clock is operating at 10 MHz in this
test, but its ICC component has been subtracted out).
§ Cpd (each clock) is the Cpd for the clock circuitry only as it operates at 10 MHz.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN74AUCH32374
32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES476 – AUGUST 2003
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
RL
From Output
Under Test
GND
CL
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
Open
RL
VCC
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
LOAD CIRCUIT
CL
RL
15 pF
15 pF
15 pF
30 pF
30 pF
2 kΩ
2 kΩ
2 kΩ
1 kΩ
500 Ω
V∆
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
VCC
Timing Input
VCC/2
0V
tw
tsu
VCC
VCC/2
Input
th
VCC
VCC/2
VCC/2
Data Input
VCC/2
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
VCC/2
Input
0V
tPHL
tPLH
VCC/2
VOL
tPHL
VOH
Output
tPLZ
VCC
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
tPZH
VCC/2
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPLH
VCC/2
VCC/2
tPZL
VOH
VCC/2
Output
VCC
Output
Control
VCC/2
VCC/2
VOH – V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AUCH32374GKER
ACTIVE
LFBGA
GKE
96
1000
SN74AUCH32374ZKER
ACTIVE
LFBGA
ZKE
96
1000 Green (RoHS &
no Sb/Br)
None
Lead/Ball Finish
MSL Peak Temp (3)
SNPB
Level-3-220C-168 HR
SNAGCU
Level-3-250C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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