TI SN74AUP1G06DBVT

SN74AUP1G06
www.ti.com
SCES590D – JULY 2004 – REVISED MAY 2010
LOW-POWER SINGLE INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
Check for Samples: SN74AUP1G06
FEATURES
1
•
•
•
•
•
•
•
Available in the Texas Instruments NanoStar™
Package
Low Static-Power Consumption
(ICC = 0.9 mA Max)
Low Dynamic-Power Consumption
(Cpd = 1 pF Typ at 3.3 V)
Low Input Capacitance (Ci = 1.5 pF Typ)
Low Noise – Overshoot and Undershoot <10%
of VCC
Ioff Supports Partial Power-Down-Mode
Operation
Input Hysteresis Allows Slow Input Transition
and Better Switching Noise Immunity at the
Input (Vhys = 250 mV Typ at 3.3 V)
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
tpd = 3.6 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
•
•
•
•
•
•
•
DBV PACKAGE
(TOP VIEW)
N.C.
2
GND
3
1
6
VCC
A
2
5
N.C.
GND
3
4
Y
N.C.
1
A
2
GND
3
5
VCC
4
Y
Y
4
DRY PACKAGE
(TOP VIEW)
N.C.
VCC
5
1
A
DCK PACKAGE
(TOP VIEW)
DSF PACKAGE
(TOP VIEW)
N.C.
1
6
YFP PACKAGE
(TOP VIEW)
VCC
A
A1
1 4 A2
VCC
GND
B1
2 3 B2
Y
A
2
5
N.C.
GND
3
4
Y
See mechanical drawings for dimensions.
N.C. – No internal connection
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2010, Texas Instruments Incorporated
SN74AUP1G06
SCES590D – JULY 2004 – REVISED MAY 2010
www.ti.com
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see
Figure 1 and Figure 2).
Static-Power Consumption
(mA)
Dynamic-Power Consumption
(pF)
100%
100%
80%
80%
Switching Characteristics
at 25 MHz
†
3.5
60%
60%
3.3-V
3.3-V
LVC †
Logic
†
Logic
40%
Voltage - V
3
40%
AUP
0%
†
Input
2
1.5
1
Output
0.5
20%
20%
2.5
0
-0.5
AUP
0%
0
Single, dual, and triple gates
5
†
Figure 1. AUP – The Lowest-Power Family
10
15
20 25 30
Time - ns
35
40
45
AUP1G08 data at CL = 15 pF
Figure 2. Excellent Signal Integrity
The output of this single inverter buffer/driver is open drain, and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
ORDERABLE PART NUMBER
NanoStar™ – WCSP (DSBGA)
0.23-mm Large Bump – YFP
Reel of 3000
SN74AUP1G06YFPR
_ _ _HT_
QFN – DRY
Reel of 5000
SN74AUP1G06DRYR
HT
uQFN – DSF
Reel of 5000
SN74AUP1G06DSFR
HT
Reel of 3000
SN74AUP1G06DBVR
Reel of 250
SN74AUP1G06DBVT
Reel of 3000
SN74AUP1G06DCKR
Reel of 250
SN74AUP1G06DCKT
–40°C to 85°C
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
(1)
(2)
(3)
TOP-SIDE MARKING (3)
H06_
HT_
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DBV/DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
YFP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
INPUT
A
OUTPUT
Y
H
L
L
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
A
2
2
4
Y
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Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G06
SN74AUP1G06
www.ti.com
SCES590D – JULY 2004 – REVISED MAY 2010
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
–0.5
VCC + 0.5
(2)
UNIT
VO
Output voltage range in the high or low state
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
qJA
Tstg
(1)
(2)
(3)
Package thermal impedance (3)
DBV package
206
DCK package
252
DSF package
300
DRY package
234
YFP package
132
Storage temperature range
–65
150
V
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74AUP1G06
SCES590D – JULY 2004 – REVISED MAY 2010
www.ti.com
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 0.8 V
VIH
MAX
0.8
3.6
UNIT
V
VCC
VCC = 1.1 V to 1.95 V
High-level input voltage
MIN
0.65 × VCC
VCC = 2.3 V to 2.7 V
V
1.6
VCC = 3 V to 3.6 V
2
VCC = 0.8 V
0
VCC = 1.1 V to 1.95 V
0.35 × VCC
VIL
Low-level input voltage
VI
Input voltage
0
3.6
VO
Output voltage
0
3.6
V
VCC = 0.8 V
20
mA
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
IOL
(2)
Low-level output current
0.9
VCC = 3 V
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
V
mA
4
VCC = 0.8 V to 3.6 V
–40
200
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Defined by the signal integrity requirements and design-goal priorities
(2)
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
VOL
MAX
MIN
UNIT
MAX
0.8 V to 3.6 V
0.1
0.1
IOL = 1.1 mA
1.1 V
0.3 × VCC
0.3 × VCC
IOL = 1.7 mA
1.4 V
0.31
0.37
IOL = 1.9 mA
1.65 V
0.31
0.35
0.31
0.33
0.44
0.45
0.31
0.33
0.44
0.45
0 V to 3.6 V
0.1
0.5
mA
0V
0.2
0.6
mA
IOL = 2.3 mA
2.3 V
IOL = 2.7 mA
3V
IOL = 4 mA
A input
TYP
IOL = 20 mA
IOL = 3.1 mA
II
TA = –40°C
to 85°C
TA = 25°C
VCC
VI = GND to 3.6 V
V
Ioff
VI or VO = 0 V to 3.6 V
ΔIoff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.2
0.6
mA
ICC
VI = GND or VCC to 3.6 V,
IO = 0
0.8 V to 3.6 V
0.5
0.9
mA
ΔICC
VI = VCC – 0.6 V,
IO = 0
3.3 V
40
50
mA
Ci
VI = VCC or GND
Co
VO = GND
4
0V
1.5
3.6 V
1.7
0V
1.7
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pF
pF
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G06
SN74AUP1G06
www.ti.com
SCES590D – JULY 2004 – REVISED MAY 2010
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
0.8 V
tpd
A
Y
TA = –40°C
to 85°C
TA = 25°C
VCC
MAX
MIN
MAX
UNIT
12.4
1.2 V ± 0.1 V
2.7
12
9.9
2
12.8
1.5 V ± 0.1 V
2.1
3.5
6.2
1.5
7.6
1.8 V ± 0.15 V
2.1
3.1
4.7
1.2
5.9
2.5 V ± 0.2 V
1.4
2.2
3.2
1
3.9
3.3 V ± 0.3 V
1.3
2.2
3.3
0.8
3.6
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
0.8 V
tpd
A
Y
TA = –40°C
to 85°C
TA = 25°C
VCC
MAX
MIN
MAX
UNIT
15.1
1.2 V ± 0.1 V
3.6
12
11.2
2.7
14.1
1.5 V ± 0.1 V
2.9
4.3
7
2.2
8.6
1.8 V ± 0.15 V
2.7
3.9
5.4
1.8
6.7
2.5 V ± 0.2 V
2.1
2.9
3.8
1.4
4.5
3.3 V ± 0.3 V
1.7
3
4.5
1.2
4.9
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
0.8 V
tpd
A
Y
TA = –40°C
to 85°C
TA = 25°C
VCC
MAX
MIN
MAX
UNIT
17.4
1.2 V ± 0.1 V
4.9
12
12.2
3.4
15.2
1.5 V ± 0.1 V
3.5
5
7.7
2.7
9.4
1.8 V ± 0.15 V
3.2
4.8
6.6
2.2
7.3
2.5 V ± 0.2 V
2.5
3.5
4.5
1.7
5.1
3.3 V ± 0.3 V
2
3.8
6
1.5
6.5
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
0.8 V
tpd
A
Y
TA = –40°C
to 85°C
TA = 25°C
VCC
TYP
MAX
MIN
MAX
25.3
1.2 V ± 0.1 V
7.6
12
16
5.6
19.3
1.5 V ± 0.1 V
5.9
7.6
10.1
4.3
12
1.8 V ± 0.15 V
4.8
7.4
10.7
3.6
11
2.5 V ± 0.2 V
3.7
5.4
7.1
2.8
7.8
3.3 V ± 0.3 V
3.2
6.5
10.5
2.5
10.8
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UNIT
ns
5
SN74AUP1G06
SCES590D – JULY 2004 – REVISED MAY 2010
www.ti.com
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
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VCC
TYP
0.8 V
1
1.2 V ± 0.1 V
1
1.5 V ± 0.1 V
1
1.8 V ± 0.15 V
1
2.5 V ± 0.2 V
1
3.3 V ± 0.3 V
1
UNIT
pF
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G06
SN74AUP1G06
www.ti.com
SCES590D – JULY 2004 – REVISED MAY 2010
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Width)
From Output
Under Test
CL
(see Note A)
1MW
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
VCC/2
0V
tPLH
tsu
VOH
VM
Output
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A .
B.
C.
D.
E.
th
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, tr/tf = 3 ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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SCES590D – JULY 2004 – REVISED MAY 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 ´ VCC
5 kW
From Output
Under Test
CL
(see Note A)
S1
GND
5 kW
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 ´ VCC
GND
LOAD CIRCUIT
CL
VM
VI
VD
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 ´ VCC
(see Note B)
VCC/2
0V
tPZL
tPLZ
VCC
VCC/2
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL + VD
VOL
tPHZ
VCC/2
VOH - VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
8
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Apr-2010
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74AUP1G06DBVR
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DBVRE4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DBVRG4
ACTIVE
SOT-23
DBV
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DBVTE4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DCKR
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DCKRE4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DCKRG4
ACTIVE
SC70
DCK
5
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DCKTE4
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DRLR
ACTIVE
SOT
DRL
5
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DRLRG4
ACTIVE
SOT
DRL
5
4000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DRYR
ACTIVE
SON
DRY
6
5000 Green (RoHS &
no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06DSFR
ACTIVE
SON
DSF
6
5000 Green (RoHS &
no Sb/Br)
NIPDAU
Level-1-260C-UNLIM
SN74AUP1G06YFPR
ACTIVE
DSBGA
YFP
4
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Apr-2010
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
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to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
SN74AUP1G06DBVR
SOT-23
3000
180.0
9.2
DBV
5
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
SN74AUP1G06DBVT
SOT-23
DBV
5
250
180.0
9.2
3.23
3.17
1.37
4.0
8.0
Q3
SN74AUP1G06DCKR
SC70
DCK
5
3000
180.0
9.2
2.24
2.34
1.22
4.0
8.0
Q3
SN74AUP1G06DCKT
SC70
DCK
5
250
180.0
9.2
2.24
2.34
1.22
4.0
8.0
Q3
SN74AUP1G06DRLR
SOT
DRL
5
4000
180.0
9.2
1.78
1.78
0.69
4.0
8.0
Q3
SN74AUP1G06DRYR
SON
DRY
6
5000
180.0
8.4
1.25
1.6
0.7
4.0
8.0
Q1
SN74AUP1G06DSFR
SON
DSF
6
5000
180.0
8.4
1.16
1.16
0.63
4.0
8.0
Q2
SN74AUP1G06YFPR
DSBGA
YFP
4
3000
178.0
9.2
0.89
0.89
0.58
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Jul-2010
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUP1G06DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74AUP1G06DBVT
SOT-23
DBV
5
250
202.0
201.0
28.0
SN74AUP1G06DCKR
SC70
DCK
5
3000
202.0
201.0
28.0
SN74AUP1G06DCKT
SC70
DCK
5
250
202.0
201.0
28.0
SN74AUP1G06DRLR
SOT
DRL
5
4000
202.0
201.0
28.0
SN74AUP1G06DRYR
SON
DRY
6
5000
202.0
201.0
28.0
SN74AUP1G06DSFR
SON
DSF
6
5000
202.0
201.0
28.0
SN74AUP1G06YFPR
DSBGA
YFP
4
3000
270.0
225.0
227.0
Pack Materials-Page 2
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