SN54F86, SN74F86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SDFS019B – JANUARY 1989 – REVISED JANUARY 1997 D SN54F86 . . . J PACKAGE SN74F86 . . . D OR N PACKAGE (TOP VIEW) Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs 1A 1B 1Y 2A 2B 2Y GND description These devices contain four independent 2-input exclusive-OR gates. They perform the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic. A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the output. OUTPUT Y L L L L H H H L H H H L 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3B 2Y GND NC 3Y 3A B 13 1B 1A NC VCC 4B 1Y NC 2A NC 2B FUNCTION TABLE (each gate) INPUTS 14 2 SN54F86 . . . FK PACKAGE (TOP VIEW) The SN54F86 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74F86 is characterized for operation from 0°C to 70°C. A 1 NC – No internal connection logic symbol† 1A 1B 2A 2B 3A 3B 4A 4B 1 =1 3 2 4 6 5 1Y 2Y 9 8 10 3Y 12 11 13 4Y † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54F86, SN74F86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SDFS019B – JANUARY 1989 – REVISED JANUARY 1997 exclusive-OR logic An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. EXCLUSIVE OR =1 These are five equivalent exclusive-OR symbols valid for an ’F86 gate in positive logic; negation may be shown at any two ports. LOGIC-IDENTITY ELEMENT EVEN-PARITY ELEMENT = ODD-PARITY ELEMENT 2k The output is active (low) if all inputs stand at the same logic level (i.e., A = B). 2k + 1 The output is active (low) if an even number of inputs (i.e., 0 or 2) are active. The output is active (high) if an odd number of outputs (i.e., only 1 of the 2) are active. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input voltage ratings may be exceeded provided the input current ratings are observed. 2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51, except for through-hole packages, which use a trace length of zero. recommended operating conditions SN54F86 SN74F86 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IIK Low-level input voltage 0.8 0.8 V Input clamp current –18 –18 mA IOH IOL High-level output current –1 –1 mA 20 mA TA Operating free-air temperature 70 °C 2 High-level input voltage 2 Low-level output current 2 20 –55 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 125 0 V V SN54F86, SN74F86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SDFS019B – JANUARY 1989 – REVISED JANUARY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IIH IIL IOS‡ ICCH TEST CONDITIONS VCC = 4.5 V, VCC = 4.5 V, II = –18 mA IOH = –1 mA VCC = 4.75 V, VCC = 4.5 V, IOH = –1 mA IOL = 20 mA VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V VCC = 5.5 V, VCC = 5.5 V, VI = 0.5 V VO = 0 MIN SN54F86 TYP† MAX MIN SN74F86 TYP† MAX –1.2 2.5 3.4 –1.2 2.5 3.4 0.5 0.5 V 0.1 0.3 0.1 mA 20 20 µA – 0.6 mA –150 mA 23 mA 28 mA – 0.6 –60 V V 2.7 0.3 UNIT –150 –60 VCC = 5.5 V, See Note 3 15 23 15 ICCL VCC = 5.5 V, VI = 4.5 V 18 28 18 † All typical values are at VCC = 5 V, TA = 25°C. ‡ Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. NOTE 3: ICCH is measured with outputs open, and the A or B input (not both) at 4.5 V. Remaining inputs are grounded. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 5 V, CL = 50 pF, RL = 500 Ω, TA = 25°C VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500Ω, TA = MIN to MAX§ ′F86 MIN tPLH tPHL A or B (other input low) Y tPLH tPHL A or B (other input high) Y UNIT SN54F86 SN74F86 MIN MAX MIN MAX 5.5 3 7 3 6.5 5.5 2.6 8 3 6.5 5.3 7 3.5 10 3.5 8 4.7 6.5 3 8 3 7.5 TYP MAX 3 4 3 4.2 3.5 3 ns ns § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54F86, SN74F86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SDFS019B – JANUARY 1989 – REVISED JANUARY 1997 PARAMETER MEASUREMENT INFORMATION 7 V (tPZL, tPLZ, O.C.) S1 Open (all others) From Output Under Test Test Point CL (see Note A) R1 From Output Under Test R1 Test Point CL (see Note A) R2 LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS RL = R1 = R2 LOAD CIRCUIT FOR 3-STATE AND OPEN-COLLECTOR OUTPUTS High-Level Pulse (see Note C) 3V 1.5 V 0V tw 3V Timing Input (see Note C) 3V 1.5 V Low-Level Pulse 0V th tsu Data Input (see Note C) 1.5 V 1.5 V 0V 3V VOLTAGE WAVEFORMS PULSE DURATION 1.5 V 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Output Control (low-level enable) 3V Input (see Note C) 1.5 V 1.5 V 1.5 V 0V tPZL 1.5 V tPLZ 0V tPLH In-Phase Output (see Note E) tPHL VOH 1.5 V VOL 1.5 V tPHZ 1.5 V 1.5 V 0.3 V tPZH tPLH VOH 3.5 V 1.5 V VOL tPHL Out-of-Phase Output (see Note E) Waveform 1 (see Notes B and E) VOH Waveform 2 (see Notes B and E) VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES (see Note D) 1.5 V 0.3 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, tr = tf ≤ 2.5 ns, duty cycle = 50%. D. When measuring propagation delay times of 3-state outputs, switch S1 is open. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated