SN54HC595 SN74HC595 www.ti.com SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009 8-BIT SHIFT REGISTERS WITH 3-STATE OUTPUT REGISTERS Check for Samples: SN54HC595 SN74HC595 FEATURES 1 • • • • • • • • 8-Bit Serial-In, Parallel-Out Shift Wide Operating Voltage Range of 2 V to 6 V High-Current 3-State Outputs Can Drive Up To 15 LSTTL Loads Low Power Consumption: 80-μA (Max) ICC tpd = 13 ns (Typ) ±6-mA Output Drive at 5 V Low Input Current: 1 μA (Max) Shift Register Has Direct Clear SN54HC595...J OR W PACKAGE SN74HC595...D, DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) QB QC QD QE QF QG QH GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER OE RCLK SRCLK SRCLR QH′ DESCRIPTION QC QB NC VCC QA 4 3 2 1 20 1 9 18 SER 5 17 6 16 7 15 8 9 10 11 14 12 1 3 OE NC RCLK SRCLK SRCLR QD QE NC QF QG QH Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. SN54HC595...FK PACKAGE (TOP VIEW) GND NC Q H' The 'HC595 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage register. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. NC – No internal connection 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1982–2009, Texas Instruments Incorporated SN54HC595 SN74HC595 SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009 www.ti.com ORDERING INFORMATION (1) TA PACKAGE PDIP − N SN74HC595N SN74HC595D Reel of 2500 SN74HC595DR Reel of 250 SN74HC595DT Tube of 40 SN74HC595DW Reel of 2000 SN74HC595DWR SOP − NS Reel of 2000 SN74HC595NSR HC595 SSOP − DB Reel of 2000 SN74HC595DBR HC595 Tube of 90 SN74HC595PW Reel of 2000 SN74HC595PWR CDIP − J Tube of 25 SNJ54HC595J SNJ54HC595J CFP − W Tube of 150 SNJ54HC595W SNJ54HC595W LCCC − FK Tube of 55 SNJ54HC595FK SNJ54HC595FK TSSOP – PW (1) (2) TOP-SIDE MARKING Tube of 40 SOIC − DW –55°C to 125°C ORDERABLE PART NUMBER Tube of 25 SOIC − D –40°C to 85°C (2) SN74HC595N HC595 HC595 HC595 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Table 1. FUNCTION TABLE INPUTS 2 FUNCTION SER SRCLK SRCLR RCLK OE X X X X H Outputs QA−QH are disabled. X X X X L Outputs QA−QH are enabled. X X L X X Shift register is cleared. L ↑ H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively. X X X ↑ X Shift-register data is stored in the storage register. Submit Documentation Feedback Copyright © 1982–2009, Texas Instruments Incorporated Product Folder Link(s): SN54HC595 SN74HC595 SN54HC595 SN74HC595 www.ti.com SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009 LOGIC DIAGRAM (POSITIVE LOGIC) OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D C1 R 3R C3 3S 15 2S 2R C2 R 3R C3 3S 1 2S 2R C2 R 3R C3 3S 2 2S 2R C2 R 3R C3 3S 3 2S 2R C2 R 3R C3 3S 4 2S 2R C2 R 3R C3 3S 5 2S 2R C2 R 3R C3 3S 6 2S 2R C2 R 3R C3 3S 7 QA QB QC 9 QD QE QF QG QH QH′ Pin numbers shown are for the D, DB, DW, J, N, NS, PW, and W packages. Copyright © 1982–2009, Texas Instruments Incorporated Product Folder Link(s): SN54HC595 SN74HC595 Submit Documentation Feedback 3 SN54HC595 SN74HC595 SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009 www.ti.com TIMING DIAGRAM SRCLK SER RCLK SRCLR OE QA QB QC QD QE QF QG QH QH’ NOTE: 4 implies that the output is in 3-State mode. Submit Documentation Feedback Copyright © 1982–2009, Texas Instruments Incorporated Product Folder Link(s): SN54HC595 SN74HC595 SN54HC595 SN74HC595 www.ti.com SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VCC Supply voltage range IIK Input clamp current (2) −0.5 V to 7 V (2) IOK Output clamp current IO Continuous output current VI < 0 or VI > VCC ±20 mA VO < 0 or VO > VCC ±20 mA VO = 0 to VCC ±35 mA Continuous current through VCC or GND Package thermal impedance (3) θJA Tstg (1) (2) (3) ±70 mA D package 73°C/W DB package 82°C/W DW package 57°C/W N package 67°C/W NS package 64°C/W PW package 108°C/W −65°C to 150°C Storage temperature range Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS (1) SN54HC595 VCC Supply voltage VCC = 2 V VIH High-level input voltage VCC = 4.5 V VCC = 6 V SN74HC595 MIN NOM MAX 2 5 6 MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 VCC = 2 V VCC = 4.5 V UNIT V V 4.2 0.5 0.5 1.35 1.35 VIL Low-level input voltage VI Input voltage 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC V VCC = 6 V 1.8 VCC = 2 V Δt/Δv TA (1) (2) Input transition rise/fall time (2) Operating free-air temperature 1.8 1000 1000 VCC = 4.5 V 500 500 VCC = 6 V 400 400 –55 125 V –40 85 ns °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. Copyright © 1982–2009, Texas Instruments Incorporated Product Folder Link(s): SN54HC595 SN74HC595 Submit Documentation Feedback 5 SN54HC595 SN74HC595 SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 μA VOH VI = VIH or VIL QH′, IOH = −4 mA QA−QH, IOH = −6 mA QH′, IOH = −5.2 mA QA−QH, IOH = −7.8 mA IOL = 20 μA VOL VI = VIH or VIL QH′, IOL = 4 mA QA−QH, IOL = 6 mA QH′, IOL = 5.2 mA QA−QH, IOL = 7.8 mA II TA = 25°C MIN TYP SN54HC595 MAX MIN MAX SN74HC595 MIN 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 3.98 4.3 3.7 3.84 3.98 4.3 3.7 3.84 5.48 5.8 5.2 5.34 5.48 5.8 5.2 5.34 4.5 V 6V MAX V 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 0.17 0.26 0.4 0.33 0.17 0.26 0.4 0.33 0.15 0.26 0.4 0.33 0.15 0.26 0.4 0.33 4.5 V 6V UNIT V VI = VCC or 0 6V ±0.1 ±100 ±1000 ±1000 nA IOZ VO = VCC or 0, QA−QH 6V ±0.01 ±0.5 ±10 ±5 µA ICC VI = VCC or 0, IO = 0 6V 8 160 80 µA 10 10 10 pF Ci 6 VCC Submit Documentation Feedback 2V to 6 V 3 Copyright © 1982–2009, Texas Instruments Incorporated Product Folder Link(s): SN54HC595 SN74HC595 SN54HC595 SN74HC595 www.ti.com SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009 TIMING REQUIREMENTS over operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency SRCLK or RCLK high or low tw Pulse duration SRCLR low SER before SRCLK↑ SRCLK↑ before RCLK↑ (1) tsu Setup time SRCLR low before RCLK↑ SRCLR high (inactive) before SRCLK↑ th (1) Hold time, SER after SRCLK↑ TA = 25°C MIN SN54HC595 MAX MIN MAX SN74HC595 MIN MAX 2V 6 4.2 5 4.5 V 31 21 25 6V 36 25 29 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 75 113 94 4.5 V 15 23 19 6V 13 19 16 2V 50 75 65 4.5 V 10 15 13 6V 9 13 11 2V 50 75 60 4.5 V 10 15 12 6V 9 13 11 2V 0 0 0 4.5 V 0 0 0 6V 0 0 0 UNIT MHz ns ns ns This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. Copyright © 1982–2009, Texas Instruments Incorporated Product Folder Link(s): SN54HC595 SN74HC595 Submit Documentation Feedback 7 SN54HC595 SN74HC595 SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009 www.ti.com SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) fmax SRCLK QH′ tpd QA−QH RCLK tPHL ten tdis SRCLR QH′ QA−QH OE QA−QH OE QA−QH tt QH′ VCC TA = 25°C MIN TYP SN54HC595 MAX MIN MAX SN74HC595 MIN 2V 6 26 4.2 5 4.5 V 31 38 21 25 6V 36 42 25 29 MAX UNIT MHz 2V 50 160 240 200 4.5 V 17 32 48 40 6V 14 27 41 34 2V 50 150 225 187 4.5 V 17 30 45 37 6V 14 26 38 32 2V 51 175 261 219 4.5 V 18 35 52 44 6V 15 30 44 37 2V 40 150 255 187 4.5 V 15 30 45 37 6V 13 26 38 32 2V 42 200 300 250 4.5 V 23 40 60 50 6V 20 34 51 43 2V 28 60 90 75 4.5 V 8 12 18 15 6V 6 10 15 13 2V 28 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 ns ns ns ns ns SWITCHING CHARACTERISTICS over recommended operating free-air temperature range, CL = 150 pF (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) VCC tpd RCLK QA−QH ten QA−QH OE QA−QH tt TA = 25°C MIN SN54HC595 MIN MAX SN74HC595 TYP MAX MIN MAX 2V 60 200 300 250 4.5 V 22 40 60 50 6V 19 34 51 43 2V 70 200 298 250 4.5 V 23 40 60 50 6V 19 34 51 43 2V 45 210 315 265 4.5 V 17 42 63 53 6V 13 36 53 45 UNIT ns ns ns OPERATING CHARACTERISTICS TA = 25°C PARAMETER Cpd 8 Power dissipation capacitance Submit Documentation Feedback TEST CONDITIONS No load TYP UNIT 400 pF Copyright © 1982–2009, Texas Instruments Incorporated Product Folder Link(s): SN54HC595 SN74HC595 SN54HC595 SN74HC595 www.ti.com SCLS041H – DECEMBER 1982 – REVISED NOVEMBER 2009 PARAMETER MEASUREMENT INFORMATION VCC S1 Test Point From Output Under Test PARAMETER RL CL (see Note A) tPZH ten 1 kΩ tPZL tPHZ tdis S2 RL tPLZ 1 kΩ Reference Input VCC Data Input VCC 50% 10% 50% VCC 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% Closed Closed Open Open Open VCC th 90% 90% VCC 50% 10% 0 V tf 50% 10% tf Output Control (Low-Level Enabling) VCC 50% 50% 0V tPZL VOH 50% 10% V OL tf tPLZ Output Waveform 1 (See Note B) 90% tr VOH VOL VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES ≈VCC ≈VCC 50% 10% tPZH tPLH 50% 10% Open VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES 50% tPLH Open tr VOLTAGE WAVEFORMS PULSE DURATIONS 50% Closed 0V 0V Input Closed tsu 0V 50% Open 50% 50% tw Low-Level Pulse S2 50 pF or 150 pF LOAD CIRCUIT 50% S1 50 pF tpd or tt High-Level Pulse CL 50 pF or 150 pF VOL tPHZ Output Waveform 2 (See Note B) 50% 90% VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS NOTES: A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. D. For clock inputs, fmax is measured when the input duty cycle is 50%. E. The outputs are measured one at a time, with one input transition per measurement. F. t PLZ and tPHZ are the same as tdis. G. tPZL and tPZH are the same as ten. H. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms Copyright © 1982–2009, Texas Instruments Incorporated Product Folder Link(s): SN54HC595 SN74HC595 Submit Documentation Feedback 9 PACKAGE OPTION ADDENDUM www.ti.com 27-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) 5962-86816012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 5962-8681601EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type Purchase Samples 5962-8681601VEA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type Purchase Samples 5962-8681601VFA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type Purchase Samples SN54HC595J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type Contact TI Distributor or Sales Office SN74HC595D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595DBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595DBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595DBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC595DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC595DRG3 PREVIEW SOIC D 16 2500 TBD SN74HC595DRG4 ACTIVE SOIC D 16 2500 SN74HC595DT ACTIVE SOIC D 16 SN74HC595DTE4 ACTIVE SOIC D SN74HC595DTG4 ACTIVE SOIC SN74HC595DW ACTIVE SOIC Call TI Samples Not Available Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples Addendum-Page 1 Call TI Purchase Samples PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 27-May-2010 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) SN74HC595DWE4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595DWG4 ACTIVE SOIC DW 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595DWR ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC595DWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC595DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC595N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor or Sales Office SN74HC595NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type Contact TI Distributor or Sales Office SN74HC595NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC595PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC595PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC595PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SNJ54HC595FK ACTIVE LCCC FK 20 1 TBD SNJ54HC595J ACTIVE CDIP J 16 1 TBD Addendum-Page 2 POST-PLATE N / A for Pkg Type A42 N / A for Pkg Type Contact TI Distributor or Sales Office Contact TI Distributor or Sales Office PACKAGE OPTION ADDENDUM www.ti.com Orderable Device SNJ54HC595W 27-May-2010 Status (1) Package Type Package Drawing OBSOLETE Pins Package Qty Eco Plan 16 TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI Samples Not Available (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC595, SN54HC595-SP, SN74HC595 : • Catalog: SN74HC595, SN54HC595 • Enhanced Product: SN74HC595-EP, SN74HC595-EP • Military: SN54HC595 • Space: SN54HC595-SP Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 27-May-2010 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Enhanced Product - Supports Defense, Aerospace and Medical Applications • Military - QML certified for Military and Defense Applications • Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 13-Oct-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC595DBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74HC595DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC595DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC595DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 SN74HC595NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC595PWR TSSOP PW 16 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Oct-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC595DBR SSOP DB 16 2000 346.0 346.0 33.0 SN74HC595DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC595DR SOIC D 16 2500 346.0 346.0 33.0 SN74HC595DWR SOIC DW 16 2000 346.0 346.0 33.0 SN74HC595NSR SO NS 16 2000 346.0 346.0 33.0 SN74HC595PWR TSSOP PW 16 2000 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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