SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003 D D D D D Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 13 ns ±4-mA Output Drive at 5 V D D D D D Low Input Current of 1 µA Max Complementary Outputs Direct Overriding Load (Data) Inputs Gated Clock Inputs Parallel-to-Serial Data Conversion SN54HC165 . . . FK PACKAGE (TOP VIEW) 1 16 2 15 3 14 4 13 5 12 6 7 8 11 10 9 VCC CLK INH D C B A SER QH E F NC G H 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 D C NC B A QH GND NC QH SER SH/LD CLK E F G H QH GND CLK SH/LD NC VCC CLK INH SN54HC165 . . . J OR W PACKAGE SN74HC165 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) NC − No internal connection description/ordering information The ’HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The ’HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output. ORDERING INFORMATION PACKAGE† TA PDIP − N SOIC − D −40°C 85°C −40 C to 85 C Tube of 25 SN74HC165N Tube of 40 SN74HC165D Reel of 2500 SN74HC165DR TOP-SIDE MARKING SN74HC165N HC165 Reel of 250 SN74HC165DT SOP − NS Reel of 2000 SN74HC165NSR HC165 SSOP − DB Reel of 2000 SN74HC165DBR HC165 Tube of 90 SN74HC165PW Reel of 2000 SN74HC165PWR Reel of 250 SN74HC165PWT CDIP − J Tube of 25 SNJ54HC165J SNJ54HC165J CFP − W Tube of 150 SNJ54HC165W SNJ54HC165W LCCC − FK Tube of 55 SNJ54HC165FK TSSOP − PW −55°C −55 C to 125 125°C C ORDERABLE PART NUMBER HC165 SNJ54HC165FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2003, Texas Instruments Incorporated !" # $%&" !# '%()$!" *!"&+ *%$"# $ " #'&$$!"# '& ",& "&# &-!# #"%&"# #"!*!* .!!"/+ *%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ '*%$"# $')!" " 122 !)) '!!&"&# !& "&#"&* %)&## ",&.#& "&*+ !)) ",& '*%$"# '*%$" '$&##0 *&# " &$&##!)/ $)%*& "&#"0 !)) '!!&"&#+ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003 description/ordering information (continued) Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH should be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs. FUNCTION TABLE INPUTS FUNCTION SH/LD CLK CLK INH L X X H H X No change H X H L ↑ No change Shift† H Parallel load L Shift† † Shift = content of each internal register shifts toward serial output QH. Data at SER is shifted into the first register. ↑ H logic diagram (positive logic) A SH/LD CLK INH CLK SER 1 B 11 C 12 D 13 E 14 F 3 G 4 H 5 6 9 15 10 S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R S C1 1D R 7 Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages. 2 QH 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 QH SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003 typical shift, load, and inhibit sequence CLK CLK INH SER L SH/LD Data Inputs A H B L C H D L E H F L G H H H QH H H L H L H L H QH L L H L H L H L Inhibit Serial Shift Load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions (see Note 3) SN54HC165 VCC VIH Supply voltage High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL VI VO ∆t/∆v‡ Low-level input voltage MIN NOM MAX 2 5 6 MIN NOM MAX 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 VCC = 4.5 V VCC = 6 V Input voltage 0 Output voltage 0 Input transition rise/fall time SN74HC165 VCC = 2 V VCC = 4.5 V VCC = 6 V 0.5 1.35 1.35 1.8 1.8 0 0 V V 0.5 VCC VCC UNIT VCC VCC 1000 1000 500 500 400 400 V V V ns TA Operating free-air temperature −55 125 −40 85 °C NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 µA VOH VI = VIH or VIL IOH = −4 mA IOH = −5.2 mA IOL = 20 µA VOL VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA II ICC Ci VI = VCC or 0 VI = VCC or 0, IO = 0 VCC MIN TA = 25°C TYP MAX SN54HC165 MIN MAX SN74HC165 MIN 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 8 160 80 µA 3 10 10 10 pF 6V 2 V to 6 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 5 SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency SH/LD low tw Pulse duration CLK high or low SH/LD high before CLK↑ SER before CLK↑ tsu Setup time CLK INH low before CLK↑ CLK INH high before CLK↑ Data before SH/LD↓ SER data after CLK↑ th Hold time PAR data after SH/LD↓ 6 POST OFFICE BOX 655303 TA = 25°C MIN MAX SN54HC165 MIN MAX SN74HC165 MIN MAX 2V 6 4.2 5 4.5 V 31 21 25 6V 36 25 29 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 40 60 50 4.5 V 8 12 10 6V 7 10 9 2V 100 150 125 4.5 V 20 30 25 6V 17 25 21 2V 40 60 50 4.5 V 8 12 10 6V 7 10 9 2V 100 150 125 4.5 V 20 30 25 6V 17 26 21 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 2V 5 5 5 4.5 V 5 5 5 6V 5 5 5 • DALLAS, TEXAS 75265 UNIT MHz ns ns ns SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax SH/LD tpd CLK H tt QH or QH QH or QH QH or QH Any VCC MIN TA = 25°C TYP MAX SN54HC165 MIN MAX SN74HC165 MIN 2V 6 13 4.2 5 4.5 V 31 50 21 25 6V 36 62 25 29 MAX UNIT MHz 2V 80 150 225 190 4.5 V 20 30 45 38 6V 16 26 38 32 2V 75 150 225 190 4.5 V 15 30 45 38 6V 13 26 38 32 2V 75 150 225 190 4.5 V 15 30 45 38 6V 13 26 38 32 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 ns ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 75 UNIT pF 7 SCLS116E − DECEMBER 1982 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% 50% 10% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 27-May-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) 84095012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type 8409501EA ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type Purchase Samples Purchase Samples 8409501FA ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type Purchase Samples SN54HC165J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type Contact TI Distributor or Sales Office SN74HC165D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC165DBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC165DBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC165DBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC165DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC165DG4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC165DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC165DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC165DRG3 PREVIEW SOIC D 16 2500 TBD Call TI Samples Not Available SN74HC165DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC165DT ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC165DTE4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC165DTG4 ACTIVE SOIC D 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC165N ACTIVE PDIP N 16 25 Pb-Free (RoHS) SN74HC165N3 OBSOLETE PDIP N 16 TBD Addendum-Page 1 Call TI CU NIPDAU N / A for Pkg Type Call TI Call TI Contact TI Distributor or Sales Office Samples Not Available PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 27-May-2010 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) SN74HC165NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) SN74HC165NSR ACTIVE SO NS 16 2000 SN74HC165NSRE4 ACTIVE SO NS 16 SN74HC165NSRG4 ACTIVE SO NS SN74HC165PW ACTIVE TSSOP SN74HC165PWE4 ACTIVE SN74HC165PWG4 Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU N / A for Pkg Type Contact TI Distributor or Sales Office Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Purchase Samples SN74HC165PWLE OBSOLETE TSSOP PW 16 Call TI Samples Not Available SN74HC165PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC165PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC165PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC165PWT ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC165PWTE4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SN74HC165PWTG4 ACTIVE TSSOP PW 16 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Contact TI Distributor or Sales Office SNJ54HC165FK ACTIVE LCCC FK 20 1 TBD SNJ54HC165J ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type Contact TI Distributor or Sales Office SNJ54HC165W ACTIVE CFP W 16 1 TBD A42 N / A for Pkg Type Contact TI Distributor or Sales Office TBD (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 2 Call TI POST-PLATE N / A for Pkg Type Contact TI Distributor or Sales Office PACKAGE OPTION ADDENDUM www.ti.com 27-May-2010 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN54HC165, SN74HC165 : • Catalog: SN74HC165 • Automotive: SN74HC165-Q1, SN74HC165-Q1 • Enhanced Product: SN74HC165-EP, SN74HC165-EP • Military: SN54HC165 NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 27-May-2010 • Enhanced Product - Supports Defense, Aerospace and Medical Applications • Military - QML certified for Military and Defense Applications Addendum-Page 4 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2010 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74HC165DBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74HC165DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC165DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74HC165NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74HC165PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 SN74HC165PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2010 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74HC165DBR SSOP DB 16 2000 346.0 346.0 33.0 SN74HC165DR SOIC D 16 2500 346.0 346.0 33.0 SN74HC165DR SOIC D 16 2500 333.2 345.9 28.6 SN74HC165NSR SO NS 16 2000 346.0 346.0 33.0 SN74HC165PWR TSSOP PW 16 2000 346.0 346.0 29.0 SN74HC165PWT TSSOP PW 16 250 346.0 346.0 29.0 Pack Materials-Page 2 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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