SCLS400G − APRIL 1998 − REVISED APRIL 2005
D 2-V to 5.5-V VCC Operation
D Max tpd of 7.5 ns at 5 V
D Typical VOLP (Output Ground Bounce)
D
D
D
D
D
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Contain Four Flip-Flops With Double-Rail
Outputs
Applications Include:
− Buffer/Storage Registers
− Shift Registers
− Pattern Generators
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
CLR
1Q
1Q
1D
2D
2Q
2Q
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4Q
4Q
4D
3D
3Q
3Q
CLK
SN54LV175A . . . FK PACKAGE
(TOP VIEW)
1Q
CLR
NC
VCC
4Q
D
SN54LV175A . . . J OR W PACKAGE
SN74LV175A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1Q
1D
NC
2D
2Q
description/ordering information
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2Q
GND
NC
CLK
3Q
The ’LV175A devices are quadruple D-type
flip-flops designed for 2-V to 5.5-V VCC operation.
4Q
4D
NC
3D
3Q
These devices have a direct clear (CLR) input and
feature complementary outputs from each
flip-flop.
NC − No internal connection
ORDERING INFORMATION
TOP-SIDE
MARKING
Tube of 40
SN74LV175AD
Reel of 2500
SN74LV175ADR
SOP − NS
Reel of 2000
SN74LV175ANSR
74LV175A
SSOP − DB
Reel of 2000
SN74LV175ADBR
LV175A
Tube of 90
SN74LV175APW
Reel of 2000
SN74LV175APWR
Reel of 250
SN74LV175APWT
TVSOP − DGV
Reel of 2000
SN74LV175ADGVR
LV175A
CDIP − J
Tube of 25
SNJ54LV175AJ
SNJ54LV175AJ
CFP − W
Tube of 150
SNJ54LV175AW
SNJ54LV175AW
LCCC − FK
Tube of 55
SNJ54LV175AFK
SOIC − D
−40°C to 85°C
TSSOP − PW
−55°C
−55
C to 125
125°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
LV175A
LV175A
SNJ54LV175AFK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
!"#$% !%&% %'(#&% !"(($% & ' )"*+!&% &$, ("! !%'(# )$!'!&% )$( $ $(# ' $-& %("#$% &%&( .&((&%/,
("!% )(!$%0 $ % %$!$&(+/ %!+"$ $%0 ' &++
)&(&#$$(,
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1
SCLS400G − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the
positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
FUNCTION TABLE
(each flip-flop)
OUTPUTS
INPUTS
CLR
CLK
D
Q
Q
L
X
X
L
H
H
↑
H
H
L
H
↑
L
L
H
H
L
X
Q0
Q0
logic diagram (positive logic)
CLR
CLK
1D
1
9
4
1D
2
1Q
C1
R
To Three Other Channels
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
2
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3
1Q
SCLS400G − APRIL 1998 − REVISED APRIL 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
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3
SCLS400G − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 4)
SN54LV175A
VCC
Supply voltage
VIH
VCC = 2 V
VCC = 2.3 V to 2.7 V
High-level input voltage
VIL
Low-level input voltage
VI
VO
Input voltage
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
2
5.5
MAX
2
5.5
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
VCC × 0.7
UNIT
V
V
0.5
0.5
VCC × 0.3
VCC × 0.3
VCC × 0.3
VCC × 0.3
VCC × 0.3
5.5
0
0
0
VCC
−50
VCC = 2 V
VCC = 2.3 V to 2.7 V
V
VCC
−50
µA
0
V
−2
−6
−6
−12
−12
50
50
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
2
2
6
6
VCC = 4.5 V to 5.5 V
VCC = 2.3 V to 2.7 V
12
12
200
200
100
100
20
20
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
V
VCC × 0.3
5.5
−2
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
Input transition rise or fall rate
MIN
1.5
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
Low-level output current
∆t/∆v
MAX
VCC = 2 V
VCC = 2.3 V to 2.7 V
High-level output current
IOL
MIN
1.5
Output voltage
IOH
SN74LV175A
mA
µA
mA
ns/V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV175A
PARAMETER
VOH
VOL
TEST CONDITIONS
IOH = −50 µA
IOH = −2 mA
IOL = 50 µA
IOL = 2 mA
IOL = 6 mA
IOL = 12 mA
VI = 5.5 V or GND
VI = VCC or GND,
Ioff
Ci
VI or VO = 0 to 5.5 V
VI = VCC or GND
MIN
2 V to 5.5 V
IOH = −6 mA
IOH = −12 mA
II
ICC
VCC
IO = 0
TYP
MIN
2.3 V
VCC−0.1
2
VCC−0.1
2
3V
2.48
2.48
4.5 V
3.8
TYP
MAX
UNIT
V
3.8
2 V to 5.5 V
0.1
0.1
2.3 V
0.4
0.4
3V
0.44
0.44
4.5 V
V
0.55
0.55
0 to 5.5 V
±1
±1
µA
5.5 V
20
20
µA
0
5
5
µA
3.3 V
1.4
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$0% )&$ ' $1$+)#$%, &(&!$(! && &% $(
)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$,
4
SN74LV175A
MAX
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1.4
pF
SCLS400G − APRIL 1998 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
CLR low
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
SN54LV175A
MIN
MAX
SN74LV175A
MIN
6
6
6
6.5
7
7
Data
7
7.5
7.5
CLR inactive
7
7.5
7.5
0.5
1
1
CLK high or low
MAX
UNIT
ns
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
SN54LV175A
MIN
MAX
SN74LV175A
MIN
CLR low
5
5
5
CLK high or low
5
5
5
Data
5
5
5
CLR inactive
5
5
5
1
1
1
MAX
UNIT
ns
ns
ns
timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V
(unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
tpd
CLR
Any
CLK
Any
CLR
Any
CLK
Any
tsk(o)
MIN
MAX
SN74LV175A
MIN
CLR low
5
5
5
CLK high or low
5
5
5
Data
4
4
4
CLR inactive
5
5
5
1
1
1
switching characteristics over recommended operating
VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
SN54LV175A
free-air
TA = 25°C
TYP
MAX
SN54LV175A
CL = 15 pF
50*
105*
45*
45
CL = 50 pF
40
80
35
35
CL = 15 pF
CL = 50 pF
ns
ns
range,
SN74LV175A
MIN
MAX
MIN
MAX
16.6*
1*
20*
1
20
9.3*
18.8*
1*
22*
1
22
10.4
21.6
1
25.5
1
25.5
12
23.3
1
27
1
27
2
UNIT
MHz
7.9*
CL = 50 pF
UNIT
ns
temperature
LOAD
CAPACITANCE
MIN
MAX
2
ns
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
%'(#&% !%!$(% )("! % $ '(#&1$ (
$0% )&$ ' $1$+)#$%, &(&!$(! && &% $(
)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$,
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5
SCLS400G − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
CLR
tpd
tpd
TA = 25°C
TYP
MAX
Any
CLR
Any
CLK
Any
SN54LV175A
CL = 15 pF
90*
155*
75*
75
CL = 50 pF
50
120
45
45
CL = 50 pF
MIN
MAX
range,
SN74LV175A
MIN
CL = 15 pF
tsk(o)
temperature
LOAD
CAPACITANCE
Any
CLK
free-air
MIN
MAX
MHz
5.5*
10.1*
1*
12*
1
12
6.5*
11.5*
1*
13.5*
1
13.5
7.4
13.6
1
15.5
1
15.5
8.4
15
1
17
1
17
1.5
CL = 50 pF
UNIT
1.5
ns
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
tpd
CLR
Any
CLK
Any
CLR
Any
CLK
Any
LOAD
CAPACITANCE
TA = 25°C
MIN
TYP
MAX
temperature
SN54LV175A
MIN
MAX
MIN
150*
215*
125*
125
CL = 50 pF
85
165
75
75
CL = 50 pF
range,
SN74LV175A
CL = 15 pF
CL = 15 pF
tsk(o)
free-air
MAX
MHz
3.7*
6.4*
1*
7.5*
1
7.5
4.6*
7.3*
1*
8.5*
1
8.5
5.3
8.4
1
9.5
1
9.5
6
9.3
1
10.5
1
10.5
1
CL = 50 pF
UNIT
1
ns
ns
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5)
SN74LV175A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
VOL(V)
Quiet output, maximum dynamic VOL
0.3
0.8
V
Quiet output, minimum dynamic VOL
−0.3
−0.8
V
VOH(V)
VIH(D)
Quiet output, minimum dynamic VOH
3
High-level dynamic input voltage
V
2.31
V
VIL(D)
Low-level dynamic input voltage
NOTE 5: Characteristics are for surface-mount packages only.
0.99
V
VCC
3.3 V
TYP
UNIT
5V
14.5
operating characteristics, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
%'(#&% !%!$(% )("! % $ '(#&1$ (
$0% )&$ ' $1$+)#$%, &(&!$(! && &% $(
)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$,
6
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f = 10 MHz
13.6
pF
SCLS400G − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
Timing Input
50% VCC
0V
tw
50% VCC
50% VCC
th
tsu
VCC
Input
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Data Input
VCC
50% VCC
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
0V
VOH
50% VCC
VOL
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPLZ
tPZL
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
VOH
50% VCC
VOL
VCC
Output
Control
≈VCC
50% VCC
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN74LV175AD
ACTIVE
SOIC
D
16
SN74LV175ADBR
ACTIVE
SSOP
DB
SN74LV175ADBRE4
ACTIVE
SSOP
SN74LV175ADE4
ACTIVE
SN74LV175ADGVR
40
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
DB
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
TVSOP
DGV
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV175ADGVRE4
ACTIVE
TVSOP
DGV
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV175ADR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV175ADRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV175ANSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV175ANSRE4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV175APW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV175APWE4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV175APWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV175APWRE4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV175APWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LV175APWTE4
ACTIVE
TSSOP
PW
16
250
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
40
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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