SN74LVC1G38 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT www.ti.com SCES538A – JANUARY 2004 – REVISED APRIL 2005 FEATURES • • • • • • • • • DBV OR DCK PACKAGE (TOP VIEW) Available in the Texas Instruments NanoStar™ and NanoFree™ Packages Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 4.5 ns at 3.3 V Low Power Consumption, 10-µA Max ICC ±24-mA Output Drive at 3.3 V Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) A B GND 1 5 VCC 4 Y 2 3 YEP OR YZP PACKAGE (BOTTOM VIEW) GND B A 3 4 Y 2 1 5 VCC DESCRIPTION/ORDERING INFORMATION The SN74LVC1G38 is designed for 1.65-V to 5.5-V VCC operation. This device is a single two-input NAND buffer gate with open-drain output. It performs the Boolean function Y = A ⋅ B or Y = A + B in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. ORDERING INFORMATION PACKAGE (1) TA NanoStar™ – WCSP (DSBGA) 0.23-mm Large Bump – YEP NanoFree™ – WCSP (DSBGA) 0.23-mm Large Bump – YZP (Pb-free) –40°C to 85°C SOT (SOT-23) – DBV SOT (SC-70) – DCK (1) (2) ORDERABLE PART NUMBER TOP-SIDE MARKING (2) SN74LVC1G38YEPR Reel of 3000 _ _ _D7_ SN74LVC1G38YZPR Reel of 3000 SN74LVC1G38DBVR Reel of 250 SN74LVC1G38DBVT Reel of 3000 SN74LVC1G38DCKR Reel of 250 SN74LVC1G38DCKT C38_ D7_ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅ = Pb-free). Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NanoStar, NanoFree are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2005, Texas Instruments Incorporated SN74LVC1G38 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT www.ti.com SCES538A – JANUARY 2004 – REVISED APRIL 2005 FUNCTION TABLE INPUTS B OUTPUT Y L L H L H H H L H H H L A LOGIC DIAGRAM (POSITIVE LOGIC) A 1 4 B Y 2 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V state (2) –0.5 UNIT VO Voltage range applied to any output in the high-impedance or power-off 6.5 V IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND θJA Package thermal impedance (3) Tstg Storage temperature range DBV package 206 DCK package 252 YEP/YZP package (1) (2) (3) 2 °C/W 132 –65 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The package thermal impedance is calculated in accordance with JESD 51-7. SN74LVC1G38 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT www.ti.com SCES538A – JANUARY 2004 – REVISED APRIL 2005 Recommended Operating Conditions VCC (1) Operating Supply voltage MAX 1.65 5.5 Data retention only 1.7 VCC = 3 V to 3.6 V 0.7 × VCC VCC = 1.65 V to 1.95 V Low-level input voltage V 2 VCC = 4.5 V to 5.5 V VIL V 0.65 × VCC VCC = 2.3 V to 2.7 V High-level input voltage UNIT 1.5 VCC = 1.65 V to 1.95 V VIH MIN 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V V 0.3 × VCC VI Input voltage 0 5.5 V VO Output voltage 0 5.5 V VCC = 1.65 V 4 VCC = 2.3 V IOL Low-level output current ∆t/∆v 8 16 VCC = 3 V Input transition rise or fall rate VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 VCC = 5 V ± 0.5 V TA ns/V 5 Operating free-air temperature (1) mA 24 –40 85 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOL = 100 µA VOL 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 IOL = 16 mA IOL = 32 mA A or B inputs 0.4 3V IOL = 24 mA II TYP (1) MAX MIN 1.65 V to 5.5 V V 0.55 4.5 V VI = 5.5 V or GND UNIT 0.55 1.65 V to 5.5 V ±1 µA 0 ±10 µA 1.65 V to 5.5 V 10 µA 3 V to 5.5 V 500 µA Ioff VI or VO = 5.5 V ICC VI = 5.5 V or GND, IO = 0 ∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND 3.3 V 3.5 pF Co VO = VCC or GND 3.3 V 4.5 pF (1) All typical values are at VCC = 3.3 V, TA = 25°C. Switching Characteristics over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 2.9 7.4 1.7 3.8 1.5 4.9 0.9 2.4 UNIT ns 3 SN74LVC1G38 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT www.ti.com SCES538A – JANUARY 2004 – REVISED APRIL 2005 Switching Characteristics over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A or B Y VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V MIN MAX MIN MAX MIN MAX MIN MAX 2.8 10 1.6 6 1.4 4.5 1 3.9 UNIT ns Operating Characteristics TA = 25°C Cpd 4 PARAMETER TEST CONDITIONS Power dissipation capacitance f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 3 3 4 6 UNIT pF SN74LVC1G38 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT www.ti.com SCES538A – JANUARY 2004 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION (OPEN DRAIN) VLOAD S1 RL From Output Under Test Open TEST GND RL CL (see Note A) S1 tPZL (see Notes E and F) VLOAD tPLZ (see Notes E and G) VLOAD tPHZ/tPZH VLOAD LOAD CIRCUIT INPUT VCC VI 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VM tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns VCC VCC 3V VCC VLOAD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC CL RL V∆ 15 pF 15 pF 15 pF 15 pF 1 MΩ 1 MΩ 1 MΩ 1MΩ 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu th VI VM Input VM VM Data Input VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V Output VM VOL tPHL VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS tPLZ VLOAD/2 VM tPZH VOH Output VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM tPZL VOH VM VI Output Control tPHL tPLH VI Output Waveform 2 S1 at VLOAD (see Note B) VOL + V∆ VOL tPHZ VM VLOAD/2 - V∆ VLOAD/2 ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VM. G. tPLZ is measured at VOL + V∆. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms 5 SN74LVC1G38 SINGLE 2-INPUT NAND GATE WITH OPEN-DRAIN OUTPUT www.ti.com SCES538A – JANUARY 2004 – REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION (OPEN DRAIN) VLOAD S1 RL From Output Under Test Open TEST GND RL CL (see Note A) S1 tPZL (see Notes E and F) VLOAD tPLZ (see Notes E and G) VLOAD tPHZ/tPZH VLOAD LOAD CIRCUIT INPUT VCC VI 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VM tr/tf ≤ 2 ns ≤ 2 ns ≤ 2.5 ns ≤ 2.5 ns VCC VCC 3V VCC VLOAD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC CL RL V∆ 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu th VI VM Input VM VM Data Input VM 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VI VM Input VM 0V Output VM VOL tPHL VM VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS tPLZ VLOAD/2 VM tPZH VOH Output VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH VM VM tPZL VOH VM VI Output Control tPHL tPLH VI Output Waveform 2 S1 at VLOAD (see Note B) VOL + V∆ VOL tPHZ VM VLOAD/2 - V∆ VLOAD/2 ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. Since this device has open-drain outputs, tPLZ and tPZL are the same as tpd. F. tPZL is measured at VM. G. tPLZ is measured at VOL + V∆. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 6 PACKAGE OPTION ADDENDUM www.ti.com 26-Apr-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVC1G38DBVR ACTIVE SOT-23 DBV 5 3000 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G38DBVT ACTIVE SOT-23 DBV 5 250 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G38DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G38DCKT ACTIVE SC70 DCK 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVC1G38YEPR ACTIVE WCSP YEP 5 3000 TBD SNPB Level-1-260C-UNLIM SN74LVC1G38YZPR ACTIVE WCSP YZP 5 3000 Pb-Free (RoHS) SNAGCU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 MECHANICAL DATA MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002 DCK (R-PDSO-G5) PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,15 0,65 5 0,10 M 4 1,40 1,10 1 0,13 NOM 2,40 1,80 3 Gage Plane 2,15 1,85 0,15 0°–8° 0,46 0,26 Seating Plane 1,10 0,80 0,10 0,00 0,10 4093553-2/D 01/02 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. 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