SN74LVCH16541A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS567G – MARCH 1996 – REVISED JUNE 1998 D D D D D D D D D D DGG OR DL PACKAGE (TOP VIEW) Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Power Off Disables Outputs, Permitting Live Insertion Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JESD 17 Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Package Options Include Thin-Shrink Small-Outline (DGG) and Plastic 300-mil Shrink Small-Outline (DL) Packages 1OE1 1Y1 1Y2 GND 1Y3 1Y4 VCC 1Y5 1Y6 GND 1Y7 1Y8 2Y1 2Y2 GND 2Y3 2Y4 VCC 2Y5 2Y6 GND 2Y7 2Y8 2OE1 description 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 1OE2 1A1 1A2 GND 1A3 1A4 VCC 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 VCC 2A5 2A6 GND 2A7 2A8 2OE2 This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVCH16541A is a noninverting 16-bit buffer composed of two 8-bit sections with separate output-enable signals. For either 8-bit buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 8-bit buffer section are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74LVCH16541A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVCH16541A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS567G – MARCH 1996 – REVISED JUNE 1998 FUNCTION TABLE (each 8-bit section) INPUTS OE1 OE2 A OUTPUT Y L L L L H L L H H X X Z X H X Z logic symbol† 1OE1 1 & EN1 48 1OE2 2OE1 2OE2 1A1 1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 2A5 2A6 2A7 2A8 24 & EN2 25 47 1 2 1 46 3 44 5 43 6 41 8 40 9 38 11 37 12 36 13 1 2 35 14 33 16 32 17 30 19 29 20 27 22 26 23 1Y1 1Y2 1Y3 1Y4 1Y5 1Y6 1Y7 1Y8 2Y1 2Y2 2Y3 2Y4 2Y5 2Y6 2Y7 2Y8 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. logic diagram (positive logic) 1OE1 1OE2 1A1 1 2OE1 48 47 2OE2 2 1Y1 2A1 24 25 36 To Seven Other Channels 2 POST OFFICE BOX 655303 13 2Y1 To Seven Other Channels • DALLAS, TEXAS 75265 SN74LVCH16541A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS567G – MARCH 1996 – REVISED JUNE 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The value of VCC is provided in the recommended operating conditions table. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) VCC Supply voltage VIH High-level input voltage Operating Data retention only VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 1.65 V to 1.95 V VIL VI VO IOH Low-level input voltage Output voltage High level output current High-level Low level output current Low-level ∆t/∆v Input transition rise or fall rate MAX 3.6 1.5 UNIT V 0.65 × VCC V 1.7 2 0.35 × VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V Input voltage IOL MIN 1.65 0.7 V 0.8 0 5.5 V High or low state 0 3 state 0 VCC 5.5 V VCC = 1.65 V VCC = 2.3 V –4 VCC = 2.7 V VCC = 3 V –12 –8 mA –24 VCC = 1.65 V VCC = 2.3 V 4 VCC = 2.7 V VCC = 3 V 12 8 mA 24 0 10 ns/V TA Operating free-air temperature –40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74LVCH16541A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS567G – MARCH 1996 – REVISED JUNE 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC 1.65 V to 3.6 V IOH = –100 µA IOH = –4 mA VOH IOH = –8 mA 12 mA IOH = –12 IOH = –24 mA IOL = 100 µA VOL II 1.65 V VCC–0.2 1.2 2.3 V 1.7 2.7 V 2.2 3V 2.4 3V 2.2 MAX 1.65 V to 3.6 V 0.2 1.65 V 0.45 2.3 V 0.7 IOL = 12 mA IOL = 24 mA 2.7 V 0.4 3V 0.55 VI = 0 to 5.5 V VI = 0.58 V 3.6 V ±5 ‡ VI or VO = 5.5 V IOZ VO = 0 to 5.5 V ICC VI = VCC or GND 3.6 V ≤ VI ≤ 5.5 V¶ ∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND IO = 0 µA –45 75 3V Ioff µA 45 23V 2.3 VI = 2 V VI = 0 to 3.6 V§ V ‡ 1 65 V 1.65 VI = 1.7 V VI = 0.8 V UNIT V IOL = 4 mA IOL = 8 mA VI = 1.07 V VI = 0.7 V II(hold) ( ) TYP† MIN –75 3.6 V ±500 0 ±10 µA 3.6 V ± 10 µA 20 36V 3.6 20 2.7 V to 3.6 V 500 3.3 V Co VO = VCC or GND 3.3 V † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This information was not available at the time of publication. § This is the bus-hold maximum dynamic current required to switch the input from one state to another. ¶ This applies in the disabled state only. µA µA 5 pF 6.5 pF switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3) FROM (INPUT) TO (OUTPUT) tpd A ten tdis PARAMETER VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V MIN MAX MIN MAX Y ‡ ‡ ‡ OE Y ‡ ‡ OE Y ‡ ‡ POST OFFICE BOX 655303 UNIT MIN MAX ‡ 5 1.1 4.2 ns ‡ ‡ 6.9 1.5 5.6 ns ‡ ‡ 7.4 1.9 6.8 ns • DALLAS, TEXAS 75265 MIN VCC = 3.3 V ± 0.3 V MAX ‡ This information was not available at the time of publication. 4 VCC = 2.7 V SN74LVCH16541A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS567G – MARCH 1996 – REVISED JUNE 1998 operating characteristics, TA = 25°C TEST CONDITIONS PARAMETER Cpd Power dissipation capacitance per buffer/driver VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V TYP TYP TYP † † 35 † † 4 Outputs enabled Outputs disabled f = 10 MHz UNIT pF † This information was not available at the time of publication. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN74LVCH16541A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS567G – MARCH 1996 – REVISED JUNE 1998 PARAMETER MEASUREMENT INFORMATION VCC = 1.8 V ± 0.15 V 2 × VCC S1 1k Ω From Output Under Test Open GND CL = 30 pF (see Note A) 1k Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC Open LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 VCC/2 0V tPLH Output Control (low-level enabling) tPLZ VCC VCC/2 tPZH VOH VCC/2 VOL VCC/2 0V Output Waveform 1 S1 at 2 × VCC (see Note B) tPHL VCC/2 VCC VCC/2 tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at Open (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74LVCH16541A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS567G – MARCH 1996 – REVISED JUNE 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.5 V ± 0.2 V 2 × VCC S1 500 Ω From Output Under Test Open GND CL = 30 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND LOAD CIRCUIT tw VCC Timing Input VCC/2 VCC/2 VCC/2 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC/2 Output Control (low-level enabling) VCC VCC/2 VCC/2 0V tPLH Output Waveform 1 S1 at 2 × VCC (see Note B) VOH VCC/2 tPLZ VCC VCC/2 tPZH tPHL VCC/2 VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCC/2 0V tPZL VCC Input VOLTAGE WAVEFORMS PULSE DURATION th VCC Data Input VCC/2 0V 0V tsu Output VCC VCC/2 Input Output Waveform 2 S1 at GND (see Note B) VOL + 0.15 V VOL tPHZ VCC/2 VOH VOH – 0.15 V 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN74LVCH16541A 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS567G – MARCH 1996 – REVISED JUNE 1998 PARAMETER MEASUREMENT INFORMATION VCC = 2.7 V AND 3.3 V ± 0.3 V 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tpd tPLZ/tPZL tPHZ/tPZH Open 6V GND tw LOAD CIRCUIT 2.7 V 2.7 V Timing Input 0V 0V VOLTAGE WAVEFORMS PULSE DURATION th 2.7 V Data Input 1.5 V 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 1.5 V 1.5 V 0V tPLH tPHL VOH 1.5 V Output Control (low-level enabling) 2.7 V 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V 0V tPZL 2.7 V Output 1.5 V 1.5 V tsu Input 1.5 V Input tPLZ 3V 1.5 V tPZH VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH 0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 3. Load Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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