SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O – JULY 1995 – REVISED FEBRUARY 2007 FEATURES 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 2OE 1Y1 2A4 1Y2 2A3 1Y3 2A2 1Y4 2A1 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 20 3 4 19 2OE 18 1Y1 17 2A4 5 6 16 1Y2 15 2A3 7 8 14 1Y3 13 2A2 12 1Y4 9 10 11 1A2 2Y3 1A3 2Y2 1A4 4 2OE 1 2 SN54LVCH244A . . . FK PACKAGE (TOP VIEW) 2Y4 1A1 1OE VCC SN74LVCH244A . . . RGY PACKAGE (TOP VIEW) 3 2 1 20 19 18 5 6 17 7 8 15 14 9 10 11 12 13 16 1Y1 2A4 1Y2 2A3 1Y3 2Y1 GND 2A1 1Y4 2A2 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND • VCC SN54LVCH244A . . . J OR W PACKAGE SN74LVCH244A . . . DB, DBQ, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) • 2A1 • • Ioff Supports Partial-Power-Down Mode Operation Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) 1OE • • Operate From 1.65 V to 3.6 V Inputs Accept Voltages to 5.5 V Max tpd of 5.9 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Support Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC) GND • • • • DESCRIPTION/ORDERING INFORMATION The SN54LVCH244A octal buffer/line driver is designed for 2.7-V to 3.6-V VCC operation, and the SN74LVCH244A octal buffer/line driver is designed for 1.65-V to 3.6-V VCC operation. These devices are organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE is low, these devices pass data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1995–2007, Texas Instruments Incorporated SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O – JULY 1995 – REVISED FEBRUARY 2007 ORDERING INFORMATION PACKAGE (1) TA QFN – RGY SN74LVCH244ARGYR Tube of 25 SN74LVCH244ADW Reel of 2000 SN74LVCH244ADWR SOP – NS Reel of 2000 SN74LVCH244ANSR LVCH244A SSOP – DB Reel of 2000 SN74LVCH244ADBR LCH244A SSOP (QSOP) – DBQ Reel of 2500 SN74LVCH244ADBQR LVCH244A Tube of 70 SN74LVCH244APW Reel of 2000 SN74LVCH244APWR Reel of 250 SN74LVCH244APWT TVSOP – DGV Reel of 2000 SN74LVCH244ADGVR LCH244A CDIP – J Tube of 20 SNJ54LVCH244AJ SNJ54LVCH244AJ CFP – W Tube of 85 SNJ54LVCH244AW SNJ54LVCH244AW LCCC – FK Tube of 55 SNJ54LVCH244AFK SNJ54LVCH244AFK TSSOP – PW –55°C to 125°C (1) TOP-SIDE MARKING Reel of 1000 SOIC – DW –40°C to 85°C ORDERABLE PART NUMBER LCH244A LVCH244A LCH244A Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (EACH BUFFER) INPUTS OE A OUTPUT Y L H H L L L H X Z LOGIC DIAGRAM (POSITIVE LOGIC) 1OE 1A1 1A2 1A3 1A4 2 1 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 11 9 13 7 15 5 17 3 Submit Documentation Feedback 2Y1 2Y2 2Y3 2Y4 SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O – JULY 1995 – REVISED FEBRUARY 2007 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 state (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off VO Voltage range applied to any output in the high or low state (2) (3) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current ±50 mA ±100 mA Continuous current through VCC or GND DB θJA Package thermal impedance (1) (2) (3) (4) (5) 70 DBQ package (4) 68 DGV package (4) 92 DW package (4) 58 package (4) 60 PW package (4) 83 RGY package (5) 37 NS Tstg package (4) Storage temperature range V –65 150 °C/W °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. The value of VCC is provided in the recommended operating conditions table. The package thermal impedance is calculated in accordance with JESD 51-7. The package thermal impedance is calculated in accordance with JESD 51-5. Submit Documentation Feedback 3 SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O – JULY 1995 – REVISED FEBRUARY 2007 Recommended Operating Conditions (1) SN54LVCH244A VCC Supply voltage VIH High-level input voltage Operating Data retention only MIN MAX MIN MAX 2 3.6 1.65 3.6 1.5 1.5 VCC = 2.3 V to 2.7 V 1.7 2 Low-level input voltage Input voltage VO Output voltage 0.7 0.8 High-level output current 0 5.5 0 5.5 High or low state 0 VCC 0 VCC 3-state 0 5.5 0 5.5 ∆t/∆v Input transition rise or fall rate TA Operating free-air temperature (1) 4 Low-level output current V V –4 VCC = 2.3 V –8 VCC = 2.7 V –12 –12 VCC = 3 V –24 –24 VCC = 1.65 V IOL V 0.8 VCC = 1.65 V IOH V 0.35 × VCC VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VI V 2 VCC = 1.65 V to 1.95 V VIL UNIT 0.65 × VCC VCC = 1.65 V to 1.95 V VCC = 2.7 V to 3.6 V SN74LVCH244A mA 4 VCC = 2.3 V 8 VCC = 2.7 V 12 12 VCC = 3 V 24 24 10 –55 125 –40 mA 10 ns/V 85 °C All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O – JULY 1995 – REVISED FEBRUARY 2007 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 2.7 V to 3.6 V 1.2 1.7 2.4 3V 2.2 2.2 0.2 0.2 1.65 V 0.45 IOL = 8 mA 2.3 V 0.7 IOL = 12 mA 2.7 V 0.4 0.4 IOL = 24 mA 3V 0.55 0.55 ±5 ±5 µA ±10 µA VI = 0 to 5.5 V 3.6 V VI or VO = 5.5 V 0 1.65 V (2) 45 2.3 V VI = 1.7 V VI = 0 to 3.6 V (2) 3V VI = 2 V (1) (2) (3) (4) 2.2 2.4 IOL = 4 mA VI = 0.8 V ∆ICC 2.2 3V 2.7 V to 3.6 V VI = 0.7 V ICC 2.7 V V 1.65 V to 3.6 V VI = 1.07 V IOZ VCC – 0.2 2.3 V VI = 0.58 V II(hold) UNIT VCC – 0.2 IOH = –8 mA IOL = 100 µA Ioff MIN TYP (1) MAX 1.65 V IOH = –24 mA II SN74LVCH244A MIN TYP (1) MAX IOH = –4 mA IOH = –12 mA VOL SN54LVCH244A 1.65 V to 3.6 V IOH = –100 µA VOH VCC V (3) VO = 0 to 5.5 V VI = VCC or GND 3.6 V ≤ VI ≤ 5.5 V (4) IO = 0 One input at VCC – 0.6 V, Other inputs at VCC or GND µA –45 75 75 –75 –75 3..6 V ±500 ±500 3.6 V ±15 ±10 10 10 10 10 500 500 3.6 V 2.7 V to 3.6 V µA µA µA Ci VI = VCC or GND 3.3 V 4 12 4 pF Co VO = VCC or GND 3.3 V 5.5 12 5.5 pF All typical values are at VCC = 3.3 V, TA = 25°C. This information was not available at the time of publication. This is the bus-hold maximum dynamic current required to switch the input from one state to another. This applies in the disabled state only. Submit Documentation Feedback 5 SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O – JULY 1995 – REVISED FEBRUARY 2007 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVCH244A PARAMETER FROM (INPUT) TO (OUTPUT) MIN MAX MIN MAX tpd A Y 7.5 1 6.5 ns ten OE Y 9 1 8 ns tdis OE Y 8 1 7 ns VCC = 2.7 V VCC = 3.3 V ± 0.3 V UNIT Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN74LVCH244A PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 1.8 V ± 0.15 V MIN MAX MIN MAX MIN MAX tpd A Y (1) (1) (1) (1) 6.9 1.5 5.9 ns ten OE Y (1) (1) (1) (1) 8.6 1 7.6 ns Y (1) (1) (1) (1) 6.8 1.5 5.8 ns MIN MAX tdis (1) OE VCC = 2.5 V ± 0.2 V VCC = 2.7 V VCC = 3.3 V ± 0.3 V UNIT This information was not available at the time of publication. Operating Characteristics TA = 25°C TEST CONDITIONS PARAMETER Cpd (1) 6 Power dissipation capacitance per buffer/driver Outputs enabled Outputs disabled VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V TYP TYP TYP (1) (1) 47 (1) (1) 2 f = 10 MHz This information was not available at the time of publication. Submit Documentation Feedback UNIT pF SN54LVCH244A,, SN74LVCH244A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCES009O – JULY 1995 – REVISED FEBRUARY 2007 PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test CL (see Note A) Open GND RL TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open VLOAD GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 2.7 V 3.3 V ± 0.3 V VI tr/tf VCC VCC 2.7 V 2.7 V ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 ns VM VLOAD CL RL V∆ VCC/2 VCC/2 1.5 V 1.5 V 2 × VCC 2 × VCC 6V 6V 30 pF 30 pF 50 pF 50 pF 1 kΩ 500 Ω 500 Ω 500 Ω 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tw tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VM VM VOL tPHL VM VM 0V Output Waveform 1 S1 at VLOAD (see Note B) tPLH tPLZ VLOAD/2 VM tPZH VOH Output VM tPZL tPHL VOH Output VI Output Control VM VOL Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS VOL + V∆ VOL tPHZ VM VOH − V∆ VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms Submit Documentation Feedback 7 PACKAGE OPTION ADDENDUM www.ti.com 26-May-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 5962-9754201Q2A ACTIVE LCCC FK 20 1 TBD 5962-9754201QRA ACTIVE CDIP J 20 1 TBD 5962-9754201QSA ACTIVE CFP W 20 1 TBD 5962-9754201V2A ACTIVE LCCC FK 20 1 TBD 5962-9754201VRA ACTIVE CDIP J 20 1 TBD 1 Lead/Ball Finish MSL Peak Temp (3) POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type A42 N / A for Pkg Type POST-PLATE N / A for Pkg Type A42 SNPB N / A for Pkg Type TBD A42 N / A for Pkg Type TBD Call TI 5962-9754201VSA ACTIVE CFP W 20 SN74LVCH244ADBLE OBSOLETE SSOP DB 20 SN74LVCH244ADBQR ACTIVE SSOP/ QSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LVCH244ADBQRE4 ACTIVE SSOP/ QSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LVCH244ADBQRG4 ACTIVE SSOP/ QSOP DBQ 20 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LVCH244ADBR ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244ADBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244ADBRG4 ACTIVE SSOP DB 20 2000 SN74LVCH244ADGVR ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244ADGVRE4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244ADGVRG4 ACTIVE TVSOP DGV 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244ADW ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244ADWE4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244ADWR ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244ADWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244ANSR ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244ANSRE4 ACTIVE SO NS 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244APW ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244APWE4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244APWG4 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244APWLE OBSOLETE TSSOP PW 20 SN74LVCH244APWR ACTIVE TSSOP PW 20 TBD TBD 2000 Green (RoHS & Addendum-Page 1 Call TI Call TI CU NIPDAU Call TI Call TI Call TI Level-1-260C-UNLIM PACKAGE OPTION ADDENDUM www.ti.com 26-May-2007 Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN74LVCH244APWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244APWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244APWT ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244APWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244APWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74LVCH244ARGYR ACTIVE QFN RGY 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN74LVCH244ARGYRG4 ACTIVE QFN RGY 20 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SNJ54LVCH244AFK ACTIVE LCCC FK 20 1 TBD SNJ54LVCH244AJ ACTIVE CDIP J 20 1 TBD A42 SNPB N / A for Pkg Type SNJ54LVCH244AW ACTIVE CFP W 20 1 TBD A42 N / A for Pkg Type Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) POST-PLATE N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 TAPE AND REEL INFORMATION Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com Device 19-May-2007 Package Pins Site Reel Diameter (mm) Reel Width (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVCH244ADBQR DBQ 20 MLA 330 16 6.5 9.0 2.1 8 16 Q1 SN74LVCH244ADBR DB 20 MLA 330 16 8.2 7.5 2.5 12 16 Q1 SN74LVCH244ADGVR DGV 20 MLA 330 12 7.0 5.6 1.6 8 12 Q1 SN74LVCH244ADWR DW 20 MLA 330 24 10.8 13.0 2.7 12 24 Q1 SN74LVCH244ANSR NS 20 MLA 330 24 8.2 13.0 2.5 12 24 Q1 SN74LVCH244APWR PW 20 MLA 330 16 6.95 7.1 1.6 8 16 Q1 SN74LVCH244ARGYR RGY 20 MLA 180 12 3.8 4.8 1.6 8 12 Q1 TAPE AND REEL BOX INFORMATION Device Package Pins Site Length (mm) Width (mm) Height (mm) SN74LVCH244ADBQR DBQ 20 MLA 0.0 0.0 0.0 SN74LVCH244ADBR DB 20 MLA 342.9 336.6 28.58 SN74LVCH244ADGVR DGV 20 MLA 338.1 340.5 20.64 SN74LVCH244ADWR DW 20 MLA 333.2 333.2 31.75 SN74LVCH244ANSR NS 20 MLA 333.2 333.2 31.75 SN74LVCH244APWR PW 20 MLA 342.9 336.6 28.58 SN74LVCH244ARGYR RGY 20 MLA 190.0 212.7 31.75 Pack Materials-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 19-May-2007 Pack Materials-Page 3 MECHANICAL DATA MLCC006B – OCTOBER 1996 FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER 28 TERMINAL SHOWN 18 17 16 15 14 13 NO. OF TERMINALS ** 12 19 11 20 10 A B MIN MAX MIN MAX 20 0.342 (8,69) 0.358 (9,09) 0.307 (7,80) 0.358 (9,09) 28 0.442 (11,23) 0.458 (11,63) 0.406 (10,31) 0.458 (11,63) 21 9 22 8 44 0.640 (16,26) 0.660 (16,76) 0.495 (12,58) 0.560 (14,22) 23 7 52 0.739 (18,78) 0.761 (19,32) 0.495 (12,58) 0.560 (14,22) 24 6 68 0.938 (23,83) 0.962 (24,43) 0.850 (21,6) 0.858 (21,8) 84 1.141 (28,99) 1.165 (29,59) 1.047 (26,6) 1.063 (27,0) B SQ A SQ 25 5 26 27 28 1 2 3 4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25) 0.020 (0,51) 0.010 (0,25) 0.055 (1,40) 0.045 (1,14) 0.045 (1,14) 0.035 (0,89) 0.045 (1,14) 0.035 (0,89) 0.028 (0,71) 0.022 (0,54) 0.050 (1,27) 4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°–8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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