SN74LVT16835 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS309D – MARCH 1994 – REVISED NOVEMBER 1996 D D D D D D D D D D DGG OR DL PACKAGE (TOP VIEW) State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low-Static Power Dissipation Member of the Texas Instruments Widebus Family Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Supports Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Supports Live Insertion Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise Flow-Through Architecture Optimizes PCB Layout Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages Using 25-mil Center-to-Center Spacings NC NC Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VCC Y16 Y17 GND Y18 OE LE description The SN74LVT16835 is an 18-bit universal bus driver designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. 1 56 2 55 3 54 4 53 5 52 6 51 7 50 8 49 9 48 10 47 11 46 12 45 13 44 14 43 15 42 16 41 17 40 18 39 19 38 20 37 21 36 22 35 23 34 24 33 25 32 26 31 27 30 28 29 GND NC A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 CLK GND NC – No internal connection Data flow from A to Y is controlled by the output-enable (OE) input. This device operates in the transparent mode when the latch-enable (LE) input is high. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is low, the A-bus data is stored in the latch/flip-flop on the low-to-high transition of the clock. When OE is high, the outputs are in the high-impedance state. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN74LVT16835 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG) packages, which provide twice the input/output (I/O) pins and functionality of standard small-outline packages in the same printed circuit board area. The SN74LVT16835 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN74LVT16835 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS309D – MARCH 1994 – REVISED NOVEMBER 1996 FUNCTION TABLE INPUTS OE LE CLK A OUTPUT Y H X X X Z L H X L L L H X H H L L ↑ L L L L ↑ H L L H X H Y0† X Y0‡ † Output level before the indicated steady-state input conditions were established, provided that CLK was high before LE went low ‡ Output level before the indicated steady-state input conditions were established L L L logic symbol§ 27 OE CLK LE EN1 30 28 2C3 C3 G2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 3 1 1 3D 52 6 51 8 49 9 48 10 47 12 45 13 44 14 43 15 42 16 41 17 40 19 38 20 37 21 36 23 34 24 33 26 31 § This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 54 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 SN74LVT16835 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS309D – MARCH 1994 – REVISED NOVEMBER 1996 logic diagram (positive logic) OE CLK LE A1 27 30 28 54 1D C1 3 Y1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high state or power-off state, VO (see Note 1) . . . . –0.5 V to 7 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . 1 W DL package . . . . . . . . . . . . . . . . . . . 1.4 W Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN74LVT16835 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS309D – MARCH 1994 – REVISED NOVEMBER 1996 recommended operating conditions (see Note 4) MIN MAX 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 5.5 V IOH IOL High-level output current –32 mA Low-level output current 64 mA ∆t/∆v Input transition rise or fall rate 10 ns/V 85 °C High-level input voltage 2 V 0.8 Outputs enabled TA Operating free-air temperature NOTE 4: Unused control inputs must be held high or low to prevent them from floating. –40 V V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS II(hold) I(h ld) VCC = 2 2.7 7V IOL = 100 µA IOL = 24 mA 0.2 IOL = 16 mA IOL = 32 mA 0.4 IOL = 64 mA VI = 5.5 V 0.55 VCC = 0 or 3.6 V, VCC = 3.6 V, VCC = 3.6 V VCC = 3 V IOZH IOZL VCC = 3.6 V, VCC = 3.6 V, ICC VCC = 3.6 3 6 V, V VI = VCC or GND VCC–0.2 2.4 V 2 0.5 10 VI = VCC or GND VI = VCC ±1 VI = 5.5 V 20 VI = 0 –5 1 ±100 VI or VO = 0 to 4.5 V VI = 0.8 V 75 VI = 2 V VO = 3 V Ci VO = 0.5 V Data pins 4.5 • DALLAS, TEXAS 75265 µA 0.2 3.5 POST OFFICE BOX 655303 µA mA 0.12 Co VO = 3 V or 0 11 † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. 4 1 –1 5 Outputs disabled VI = 3 V or 0 µA 0.12 Outputs low VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Control inputs µA µ µA –75 IO = 0, 0 V 0.5 Outputs high ∆ICC‡ V IOH = –8 mA IOH = –32 mA VCC = 0, A inputs UNIT –1.2 VCC = 2.7 V, VCC = 3 V II Ioff MAX II = –18 mA IOH = –100 µA VCC = 3 V A inputs TYP† VCC = 2.7 V, VCC = 2.7 V to 3.6 V, VOL Control inputs MIN mA pF pF SN74LVT16835 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS309D – MARCH 1994 – REVISED NOVEMBER 1996 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) VCC = 3.3 V ± 0.3 V fclock Clock frequency tw Pulse duration tsu th Setup time Hold time VCC = 2.7 V MIN MAX MIN MAX 0 150 0 125 LE high 3.3 3.3 CLK high or low 3.3 3.3 Data before CLK↑ 1.6 2.1 Data before LE↓, CLK high 2.6 1.9 Data before LE↓, CLK low 2 1.3 Data after CLK↑ 2 2.1 0.9 1.2 Data after LE↓ UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN TYP† MAX 150 A Y LE Y CLK Y OE Y OE Y tPLZ † All typical values are at VCC = 3.3 V, TA = 25°C. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC = 2.7 V MIN MAX 150 UNIT MHz 1.7 3 5.4 6.8 1.6 3.2 5.9 7.7 2.3 4 7 8.5 2.7 4.3 7.9 9.7 2.5 4.1 7.9 9.2 3.5 5.4 8.9 10.4 1.2 3 5 5.9 1.5 3 5.8 6.9 2.7 4.6 7.4 8.3 2.8 4.7 6.7 7.2 ns ns ns ns ns 5 SN74LVT16835 3.3-V ABT 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS SCBS309D – MARCH 1994 – REVISED NOVEMBER 1996 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT 1.5 V Timing Input 0V tw tsu 2.7 V 1.5 V Input 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.5 V 0V tPLH 1.5 V Output 1.5 V VOL VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 1.5 V 0V tPLZ Output Waveform 1 S1 at 6 V (see Note B) tPLH tPHL 1.5 V tPZL tPHL VOH 2.7 V Output Control Output Waveform 2 S1 at GND (see Note B) 3V 1.5 V VOL + 0.3 V VOL tPZH tPHZ 1.5 V VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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