TI SN74LVT244BDBR

SCAS354J − FEBRUARY 1994 − REVISED SEPTEMBER 2003
D Supports Mixed-Mode Signal Operation
D
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
1
20
19 2OE
18 1Y1
2
3
17 2A4
16 1Y2
4
5
15 2A3
14 1Y3
6
7
13 2A2
12 1Y4
8
9
10
11
2A1
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
RGY PACKAGE
(TOP VIEW)
VCC
DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
1OE
D
D
Insertion
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
GND
D
D Ioff and Power-Up 3-State Support Hot
(5-V Input and Output Voltages With
3.3-V VCC)
Supports Unregulated Battery Operation
Down to 2.7 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
description/ordering information
This octal buffer and line driver is designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
The SN74LVT244B is organized as two 4-bit line drivers with separate output-enable (OE) inputs. When OE
is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
ORDERING INFORMATION
QFN − RGY
TOP-SIDE
MARKING
Tape and reel
SN74LVT244BRGYR
Tube
SN74LVT244BDW
Tape and reel
SN74LVT244BDWR
SOP − NS
Tape and reel
SN74LVT244BNSR
LVT244B
SSOP − DB
Tape and reel
SN74LVT244BDBR
LX244B
Tube
SN74LVT244BPW
Tape and reel
SN74LVT244BPWR
SOIC − DW
−40°C
−40
C to 85
85°C
C
ORDERABLE
PART NUMBER
PACKAGE†
TA
TSSOP − PW
VFBGA − GQN
VFBGA − ZQN (Pb-free)
LX244B
LVT244B
LX244B
SN74LVT244BGQNR
Tape and reel
SN74LVT244BZQNR
LX244B
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  2003, Texas Instruments Incorporated
!" # $%&" !# '%()$!" *!"&
*%$"# $ " #'&$$!"# '& "+& "&# &,!# #"%&"#
#"!*!* -!!". *%$" '$&##/ *&# " &$&##!). $)%*&
"&#"/ !)) '!!&"&#
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1
SCAS354J − FEBRUARY 1994 − REVISED SEPTEMBER 2003
description/ordering information (continued)
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
terminal assignments
4
1
2
3
4
A
A
1A1
1OE
B
1A2
2A4
VCC
2Y4
2OE
B
C
C
1A3
2Y3
2A3
1Y2
D
D
1A4
2A2
2Y2
1Y3
E
E
GND
2Y1
2A1
1Y4
1Y1
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
1
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
19
11
9
13
7
15
5
17
3
Pin numbers shown are for the DB, DW, NS, PW, and RGY packages.
2
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2Y1
2Y2
2Y3
2Y4
SCAS354J − FEBRUARY 1994 − REVISED SEPTEMBER 2003
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Current into any output in the high state, IO (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
(see Note 3): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
(see Note 3): GQN/ZQN package . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 5)
MIN
MAX
2.7
3.6
UNIT
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
5.5
V
IOH
IOL
High-level output current
−32
mA
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
TA
Power-up ramp rate
200
Operating free-air temperature
−40
High-level input voltage
2
V
0.8
Low-level output current
Outputs enabled
V
V
64
mA
10
ns/V
µs/V
85
°C
NOTE 5: All unused inputs of the device must at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SCAS354J − FEBRUARY 1994 − REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
−1.2
V
VIK
VCC = 2.7 V,
VCC = 2.7 V to 3.6 V,
II = −18 mA
IOH = −100 µA
VOH
VCC = 2.7 V,
VCC = 3 V,
IOH = −8 mA
IOH = −32 mA
IOL = 100 µA
IOL = 24 mA
0.2
VCC = 2.7 V
IOL = 16 mA
IOL = 32 mA
0.4
IOL = 64 mA
VI = 5.5 V
0.55
VOL
VCC = 3 V
Control inputs
VCC = 0 or 3.6 V,
VCC = 3.6 V,
Data inputs
VCC = 3.6 V
II
VCC−0.2
2.4
V
2
0.5
V
0.5
10
±1
VI = VCC or GND
VI = VCC
1
VI = 0
VI or VO = 0 to 4.5 V
µA
A
−5
±100
µA
5
µA
−5
µA
±100
µA
Ioff
IOZH
VCC = 0,
VCC = 3.6 V,
IOZL
VCC = 3.6 V,
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don’t care
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don’t care
±100
µA
ICC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
VO = 3 V
VO = 0.5 V
Outputs high
5
Outputs disabled
∆ICC‡
VCC = 3 V to 3.6 V, One input at VCC − 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
VO = 3 V or 0
Co
0.19
Outputs low
mA
0.19
0.2
mA
4
pF
7
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A
Y
tPZH
tPZL
OE
Y
tPHZ
tPLZ
OE
Y
PARAMETER
† All typical values are at VCC = 3.3 V, TA = 25°C.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
TYP†
MAX
1.1
2.3
3.5
3.8
1.3
2.1
3.3
3.6
1.1
2.5
4.5
5.3
1.4
2.7
4.4
4.9
1.9
2.8
4.4
4.5
1.8
2.9
4.4
4.4
MIN
UNIT
MAX
ns
ns
ns
SCAS354J − FEBRUARY 1994 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
6V
Open
S1
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
2.7 V
Input
1.5 V
th
2.7 V
1.5 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
2.7 V
1.5 V
Input
Output
Control
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
VOH
1.5 V
Output
1.5 V
VOL
VOH
Output
1.5 V
tPLZ
3V
1.5 V
tPZH
tPLH
tPHL
1.5 V
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPZL
tPHL
tPLH
1.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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5
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
SN74LVT244BDB
OBSOLETE
SSOP
DB
20
SN74LVT244BDBLE
OBSOLETE
SSOP
DB
20
SN74LVT244BDBR
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BDBRE4
ACTIVE
SSOP
DB
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BDW
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BDWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BDWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BDWR
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BDWRE4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BDWRG4
ACTIVE
SOIC
DW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BGQNR
ACTIVE
GQN
20
1000
SNPB
Level-1-240C-UNLIM
SN74LVT244BNSR
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BNSRG4
ACTIVE
SO
NS
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BPW
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BPWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BPWLE
OBSOLETE
TSSOP
PW
20
TBD
Call TI
SN74LVT244BPWR
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BPWRE4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BPWRG4
ACTIVE
TSSOP
PW
20
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVT244BRGYR
ACTIVE
QFN
RGY
20
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74LVT244BRGYRG4
ACTIVE
QFN
RGY
20
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SN74LVT244BZQNR
ACTIVE
ZQN
20
1000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
BGA MI
CROSTA
R JUNI
OR
BGA MI
CROSTA
R JUNI
OR
Pins Package Eco Plan (2)
Qty
Green (RoHS &
no Sb/Br)
TBD
(1)
TBD
Lead/Ball Finish
CU NIPDAU
Call TI
MSL Peak Temp (3)
Level-1-260C-UNLIM
Call TI
Call TI
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
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