SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS710D – OCTOBER 1997 – REVISED APRIL 1999 D D D D D D D SN54LVTH2952 . . . JT PACKAGE SN74LVTH2952 . . . DB, DGV, DW, OR PW PACKAGE (TOP VIEW) B8 B7 B6 B5 B4 B3 B2 B1 OEAB CLKAB CLKENAB GND 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 VCC A8 A7 A6 A5 A4 A3 A2 A1 OEBA CLKBA CLKENBA SN54LVTH2952 . . . FK PACKAGE (TOP VIEW) B5 B4 B3 NC B2 B1 OEAB 5 4 3 2 1 28 27 26 25 6 24 7 23 8 22 9 21 10 20 19 11 12 13 14 15 16 17 18 CLKAB CLKENAB GND NC description These octal bus transceivers and registers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. 1 A6 A5 A4 NC A3 A2 A1 CLKENBA CLKBA OEBA D State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Ioff and Power-Up 3-State Support Hot Insertion Bus-Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.7 V Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Latch-Up Performance Exceeds 500 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Thin Very Small-Outline (DGV) Packages, Ceramic Chip Carriers (FK), and Ceramic (JT) DIPs B6 B7 B8 NC VCC A8 A7 D NC – No internal connection The ’LVTH2952 devices consist of two 8-bit back-to-back registers that store data flowing in both directions between two bidirectional buses. Data on the A or B bus is stored in the registers on the low-to-high transition of the clock (CLKAB or CLKBA) input, provided that the clock-enable (CLKENAB or CLKENBA) input is low. Taking the output-enable (OEAB or OEBA) input low accesses the data on either port. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS710D – OCTOBER 1997 – REVISED APRIL 1999 description (continued) These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The SN54LVTH2952 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LVTH2952 is characterized for operation from –40°C to 85°C. FUNCTION TABLE† INPUTS OUTPUT B CLKENAB CLKAB OEAB A H X L X X H or L L X L ↑ L L L L ↑ L H H B0‡ B0‡ X X H X Z † A-to-B data flow is shown; B-to-A data flow is similar but uses CLKENBA, CLKBA, and OEBA. ‡ Level of B before the indicated steady-state input conditions were established logic symbol§ OEBA CLKENBA CLKBA OEAB CLKENAB CLKAB A1 A2 A3 A4 A5 A6 A7 A8 15 13 14 9 11 10 16 EN3 G1 1 C5 EN4 G2 2 C6 3 1 5D 6D 1 4 17 7 18 6 19 5 20 4 21 3 22 2 23 1 § This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the DB, DGV, DW, JT, and PW packages. 2 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 B1 B2 B3 B4 B5 B6 B7 B8 SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS710D – OCTOBER 1997 – REVISED APRIL 1999 logic diagram (positive logic) 11 CLKENAB CLKAB 10 9 OEAB 13 CLKENBA 14 CLKBA 15 OEBA C1 16 8 1D A1 B1 C1 1D To Seven Other Channels Pin numbers shown are for the DB, DGV, DW, JT, and PW packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS710D – OCTOBER 1997 – REVISED APRIL 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high-impedance or power-off state, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Voltage range applied to any output in the high state, VO (see Note 1) . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Current into any output in the low state, IO: SN54LVTH2952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA SN74LVTH2952 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA Current into any output in the high state, IO (see Note 2): SN54LVTH2952 . . . . . . . . . . . . . . . . . . . . . . 48 mA SN74LVTH2952 . . . . . . . . . . . . . . . . . . . . . . 64 mA Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Package thermal impedance, θJA (see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139°C/W DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This current flows only when the output is in the high state and VO > VCC. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LVTH2952 SN74LVTH2952 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.5 V IOH IOL High-level output current –24 –32 mA Low-level output current 48 64 mA ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature –55 High-level input voltage 2 Outputs enabled 2 10 V 10 –40 ns/V µs/V 200 125 V 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS710D – OCTOBER 1997 – REVISED APRIL 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 2.7 V, IOH = –8 mA IOH = –24 mA VCC = 3 V VCC = 2 2.7 7V VOL VCC = 3 V Control inputs VCC = 3.6 V, VCC = 0 or 3.6 V, II A or B ports‡ Ioff II(hold) ( ) VCC = 3.6 V VCC = 0, A or B ports SN54LVTH2952 TYP† MAX TEST CONDITIONS VCC = 3 V VCC = 3.6 V§, MIN SN74LVTH2952 TYP† MAX MIN –1.2 VCC–0.2 2.4 –1.2 VCC–0.2 2.4 V V 2 IOH = –32 mA IOL = 100 µA UNIT 2 0.2 0.2 IOL = 24 mA IOL = 16 mA 0.5 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 V 0.55 IOL = 64 mA VI = VCC or GND 0.55 VI = 5.5 V VI = 5.5 V VI = VCC VI = 0 VI or VO = 0 to 4.5 V VI = 0.8 V VI = 2 V VI = 0 to 3.6 V ±1 ±1 10 10 20 20 1 1 –5 –5 ±100 75 75 –75 –75 µA µA µA ±500 IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don’t care ±100∗ ±100 µA IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V, OE = don’t care ±100∗ ±100 µA 0.19 0.19 ICC VCC = 3.6 V, IO = 0, VI = VCC or GND Outputs high Outputs low Outputs disabled ∆ICC¶ VCC = 3 V to 3.6 V, One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = 3 V or 0 VO = 3 V or 0 4 5 5 0.19 0.19 0.2 0.2 4 mA mA pF Cio 9 9 pF ∗ On products compliant to MIL-PRF-38535, this parameter is not production tested. † All typical values are at VCC = 3.3 V, TA = 25°C. ‡ Unused terminals at VCC or GND § This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another. ¶ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS710D – OCTOBER 1997 – REVISED APRIL 1999 timing requirement over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVTH2952 VCC = 3.3 V ± 0.3 V MIN fclock tw Clock frequency Pulse duration Setup time CE before CLK↑ th Hold time VCC = 2.7 V MIN 150 A or B before CLK↑ tsu MAX SN74LVTH2952 VCC = 3.3 V ± 0.3 V MAX MIN 150 MAX VCC = 2.7 V MIN 150 3.3 3.3 3.3 3.3 CLK low 3.3 3.3 3.3 3.3 Data high 1.6 2.2 1.5 2.1 Data low 1.6 2.2 1.5 2.1 Data high 1.6 1.9 1.5 1.8 2 2.6 1.9 2.5 1 0.2 1 0.2 1.2 0.2 1.2 0.2 Data low A or B after CLK↑ CE after CLK↑ MAX 150 CLK high UNIT MHz ns ns ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVTH2952 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN fmax tPLH tPHL tPZH tPZL tPHZ VCC = 2.7 V MAX 150 CLKBA or CLKAB A or B OEBA or OEAB A or B OEBA or OEAB A or B tPLZ † All typical values are at TA = 25°C. SN74LVTH2952 MIN MAX 150 MIN TYP† VCC = 2.7 V MAX 150 MIN MHz 4.8 5.5 1.3 2.9 4.6 5.3 1.2 4.8 5.5 1.3 3.1 4.6 5.3 1 4.8 5.9 1.1 2.6 4.6 5.8 1 4.8 5.9 1.1 3 4.6 5.8 1.2 5.6 6 1.3 3.6 5.4 5.9 1.5 5.4 5.6 1.6 3.6 5.1 5.3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MAX 150 1.2 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 VCC = 3.3 V ± 0.3 V ns ns ns SN54LVTH2952, SN74LVTH2952 3.3-V ABT OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS710D – OCTOBER 1997 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT FOR OUTPUTS 2.7 V 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V Input 1.5 V 1.5 V 0V tPLH tPHL VOH 1.5 V Output 1.5 V VOL tPHL tPLH VOH Output 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 2.7 V Output Control Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V 1.5 V 0V tPZL tPLZ 3V 1.5 V tPZH VOL + 0.3 V VOL tPHZ 1.5 V VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1999, Texas Instruments Incorporated