SN751177, SN751178 DUAL DIFFERENTIAL DRIVERS AND RECEIVERS SLLS059D – FEBRUARY 1990 – REVISED MAY 1999 D D D D D D D D D D D Meet or Exceed the Requirements of ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.10 and V.11 Designed for Multipoint Bus Transmission on Long Bus Lines in Noise Environments Driver Positive- and Negative-Current Limiting Thermal Shutdown Protection Driver 3-State Outputs Receiver Common-Mode Input Voltage Range of –12 V to 12 V Receiver Input Sensitivity . . . ±200 mV Receiver Hysteresis . . . 50 mV Typ Receiver Input Impedance . . . 12 kΩ Min Receiver 3-State Outputs (SN751177 Only) Operate From Single 5-V Supply SN751177 . . . N OR NS† PACKAGE (TOP VIEW) 1B 1A 1R RE 2R 2A 2B GND 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1D 1Y 1Z DE 2Z 2Y 2D SN751178 . . . N OR NS† PACKAGE (TOP VIEW) 1B 1A 1R 1DE 2R 2A 2B GND description The SN751177 and SN751178 dual differential drivers and receivers are monolithic integrated circuits that are designed for balanced multipoint bus transmission at rates up to 10 Mbit/s. They are designed to improve the performance of full-duplex data communications over long bus lines and meet ANSI Standards TIA/EIA-422-B and TIA/EIA-485-A and ITU Recommendations V.10 and V.11. 1 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 1D 1Y 1Z 2DE 2Z 2Y 2D † The NS package is only available taped and reeled. The SN751177 and SN751178 driver outputs provide limiting for both positive and negative currents and thermal-shutdown protection from line-fault conditions on the transmission bus line. The receiver features high input impedance of at least 12 kΩ, an input sensitivity of ±200 mV over a common-mode input voltage range of –12 V to 12 V, and typical input hysteresis of 50 mV. Fail-safe design ensures that if the receiver inputs are open, the receiver outputs always will be high. The SN751177 and SN751178 are characterized for operation from –20°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN751177, SN751178 DUAL DIFFERENTIAL DRIVERS AND RECEIVERS SLLS059D – FEBRUARY 1990 – REVISED MAY 1999 Function Tables SN751177, SN751178 (each driver) OUTPUTS INPUT D ENABLE DE H H H L L H L H X L Z Z Y Z H = high level, L = low level, X = irrelevant, Z = high impedance (off) SN751177 (each receiver) DIFFERENTIAL INPUTS A–B ENABLE RE OUTPUT R VID ≥ 0.2 V –0.2 V < VID < 0.2 V L H L ? VID ≤ –0.2 V X L L H Z Open L H H = high level, L = low level, ? = indeterminate, X = irrelevant, Z = high impedance (off) SN751178 (each receiver) DIFFERENTIAL INPUTS A–B OUTPUT R VID ≥ 0.2 V –0.2 V < VID < 0.2 V H VID ≤ –0.2 V H = high level, L ? = indeterminate 2 POST OFFICE BOX 655303 ? L = low level, • DALLAS, TEXAS 75265 SN751177, SN751178 DUAL DIFFERENTIAL DRIVERS AND RECEIVERS SLLS059D – FEBRUARY 1990 – REVISED MAY 1999 logic symbols† logic diagrams (positive logic) SN751177 DE 12 4 RE 1D 1R 2D 2R SN751177 EN1 DE 12 EN2 14 1 15 13 1 2 3 2 1 9 10 1 11 1 6 5 2 7 RE 1Y 4 14 1Z 1D 15 13 1A 2 1B 1R 3 1 2Y 10 2Z 2D 2A 9 11 6 2B 2R 5 7 1Y 1Z 1A 1B 2Y 2Z 2A 2B SN751178 1DE 1D 4 14 EN 15 13 2 1R 2DE 2D 2R 3 12 1 10 EN 9 11 6 5 7 SN751178 1Y 1Z 1DE 1A 1D 4 14 15 1B 13 2 2Y 1R 2Z 2DE 2A 2D 3 1 12 10 9 2B 11 6 2R † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 5 7 1Y 1Z 1A 1B 2Y 2Z 2A 2B schematics of inputs EQUIVALENT OF DRIVER OR ENABLE INPUT VCC EQUIVALENT OF RECEIVER INPUT VCC R(eq) Input Input Driver Input: R(eq) = 6 kΩ NOM Enable Input: R(eq) = 4 kΩ NOM R(eq) = Equivalent Resistor All resistor values are nominal. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN751177, SN751178 DUAL DIFFERENTIAL DRIVERS AND RECEIVERS SLLS059D – FEBRUARY 1990 – REVISED MAY 1999 schematics of outputs TYPICAL OF ALL DRIVER OUTPUTS TYPICAL OF ALL RECEIVER OUTPUTS VCC 85 Ω NOM VCC Output Output GND All resistor values are nominal. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI (DE, RE, and D inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Receiver input voltage range, VI (A or B inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V to 25 V Receiver differential input voltage range, VID (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25 V to 25 V Driver output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to 15 V Receiver low-level output current, IOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA Package thermal impedance, θJA (see Note 3): N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential input voltage, are with respect to the network ground terminal. 2. Differential input voltage is measured at the noninverting terminal with respect to the inverting terminal. 3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN751177, SN751178 DUAL DIFFERENTIAL DRIVERS AND RECEIVERS SLLS059D – FEBRUARY 1990 – REVISED MAY 1999 recommended operating conditions Supply voltage, VCC High-level input voltage, VIH MIN NOM MAX UNIT 4.75 5 5.25 V 2 DE RE, RE and D inp ts DE, inputs Low-level input voltage, VIL –7† Common-mode output voltage, VOC V 0.8 V 12 V –60 mA 60 mA Common-mode input voltage, VIC ±12 V Differential input voltage, VID ±12 V Driver High-level output current, IOH Low-level output current, IOL Receiver High-level output current, IOH Low-level output current, IOL –400 µA 16 mA Operating free-air temperature, TA –20 85 °C † The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode output and threshold voltage levels only. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN751177, SN751178 DUAL DIFFERENTIAL DRIVERS AND RECEIVERS SLLS059D – FEBRUARY 1990 – REVISED MAY 1999 DRIVER SECTIONS electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VIK VOH Input clamp voltage VOL |VOD1| Low-level output voltage |VOD2| TEST CONDITIONS II = –18 mA VIH = 2 V, High-level output voltage VIH = 2 V, IO = 0 Differential output voltage Differential output voltage g VOD3 Differential output voltage ∆|VOD| Change in magnitude of differential output voltage (see Note 5) VOC Common-mode output voltage ∆|VOC| Change in magnitude of common-mode output voltage (see Note 5) IO IOZ Output current with power off IIH IIL High-level input current IOS ICC VIL = 0.8 V, VIL = 0.8 V, TYP† IOH = –33 mA IOH = 33 mA See Figure 1 RL = 54 Ω, See Figure 1 RL = 54 Ω or 100 Ω, UNIT –1.5 V 3.7 V 1.1 V 1.5 RL = 100 Ω Ω, MAX 6 2 or 1/2 VOD1‡ See Note 4 High-impedance-state output current MIN See Figure 1 V 1.5 5 1.5 5 V ±0.2 V 3 V ±0.2 V ±100 µA ±100 µA 20 µA –100 µA –1§ VCC = 0, VO = –7 V to 12 V VO = –7 V to 12 V Low-level input current VIH = 2.7 V VIL = 0.4 V –250 Short-circuit output current (see Note 6) VO = –7 V VO = VCC VO = 12 V 250 Supply current No load V 250 Outputs enabled 80 110 Outputs disabled 50 80 mA mA † All typical values are at VCC = 5 V and TA = 25°C. ‡ The minimum VOD2 with a 100-Ω load is either 1/2 VOD1 or 2 V, whichever is greater. § The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode output and threshold voltage levels only. NOTES: 4. See TIA/EIA-485-A Figure 3.5, Test Termination Measurement 2 5. ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively, that occur when the input is changed from a high level to a low level. 6. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. switching characteristics at VCC = 5 V, CL = 50 pF, TA = 25°C PARAMETER 6 TEST CONDITIONS td(OD) tt(OD) Differential output delay time tPLH tPHL Propagation delay time, low- to high-level output tPZH tPZL tPHZ tPLZ RL = 54 Ω Ω, Differential output transition time See Figure 3 MIN TYP MAX 20 25 UNIT ns 27 35 ns 20 25 ns 20 25 ns RL = 27 Ω Ω, See Figure 4 Output enable time to high level RL = 110 Ω, See Figure 5 80 120 ns Output enable time to low level RL = 110 Ω, See Figure 6 40 60 ns Output disable time from high level RL = 110 Ω, See Figure 5 90 120 ns Output disable time from low level RL = 110 Ω, See Figure 6 30 45 ns Propagation delay time, high- to low-level output POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN751177, SN751178 DUAL DIFFERENTIAL DRIVERS AND RECEIVERS SLLS059D – FEBRUARY 1990 – REVISED MAY 1999 SYMBOL EQUIVALENTS DATA-SHEET PARAMETER TIA/EIA-422-B TIA/EIA-485-A VO Vt (RL = 100 Ω) VO Vt (RL = 54 Ω) Vt (Test Termination Measurement 2) ∆|VOD| | |Vt| – |Vt| | | |Vt| – |Vt| | VOC ∆|VOC| |VOS| |VOS| |VOS – VOS| |VOD1| |VOD2| |VOD3| |VOS – VOS| IOS IO |Isa|, |Isb| |Ixa|, |Ixb| Iia, Iib RECEIVER SECTIONS electrical characteristics over recommended ranges of common-mode input voltage, supply voltage, and operating free-air temperature (unless otherwise noted) PARAMETER VIT+ TEST CONDITIONS Positive-going input threshold voltage VIT– Negative-going input threshold voltage Vhys VIK Input hysteresis voltage (VIT+ – VIT–) VOH High-level output voltage VO = 2.7 V, VO = 0.5 V, Low level output voltage Low-level IOZ High-impedance-state output current SN751177 II = –18 mA VID = 200 mV, VID = –200 200 mV SN751177 II Line input current (see Note 7) IIH IIL High-level enable input current SN751177 Low-level enable input current SN751177 IOS ICC Short-circuit output current (see Note 6) Supply current TYP† IO = –0.4 mA IO = 16 mA MAX 0.2 –0.2‡ 2.7 IOL = 16 mA 0.5 ±20 VI = 12 V VI = –7 V 1 –0.8 VIH = 2.7 V VIL = 0.4 V –15 No load, Outputs enabled V V 0.45 VO = 0.4 V to 2.4 V Other input at 0 V V mV –1.5 IOH = –400 µA IOL = 8 mA UNIT V 50 Enable clamp voltage VOL MIN 80 V µA mA 20 µA –100 µA –85 µA 110 mA ri Input resistance 12 kΩ † All typical values are at VCC = 5 V and TA = 25°C. ‡ The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode output and threshold voltage levels only. NOTES: 6. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. 7. Refer to ANSI Standards TIA/EIA-422-B, TIA/EIA-423-A, and TIA/EIA-485-A for exact conditions. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN751177, SN751178 DUAL DIFFERENTIAL DRIVERS AND RECEIVERS SLLS059D – FEBRUARY 1990 – REVISED MAY 1999 switching characteristics at VCC = 5 V, CL = 15 pF, TA = 25°C PARAMETER TEST CONDITIONS tPLH tPHL Propagation delay time, low- to high-level output tPZH tPZL Output enable time to high level tPHZ tPLZ Output disable time from high level 1 5 V to 1.5 1 5 V, V VID = –1.5 Propagation delay time, high- to low-level output Output enable time to low level SN751177 MIN TYP MAX 20 35 ns 22 35 ns 17 25 ns 20 27 ns 25 40 ns 30 40 ns See Figure 7 See Figure 8 Output disable time from low level UNIT PARAMETER MEASUREMENT INFORMATION RL 2 VOD2 RL 2 VOC Figure 1. Driver Test Circuit, VOD and VOC VID VOH VOL –IOH +IOL Figure 2. Receiver Test Circuit, VOH and VOL RL = 54 Ω CL = 50 pF Output (see Note A) 3V Input 3V 1.5 V 1.5 V 0V td(OD) Generator (see Note B) 50 Ω Output td(OD) 50% 10% 90% 90% ≈ 2.5 V 50% 10% tt(OD) TEST CIRCUIT ≈ –2.5 V tt(OD) VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns. Figure 3. Driver Differential Output-Delay and Transition-Time Test Circuit and Voltage Waveforms 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN751177, SN751178 DUAL DIFFERENTIAL DRIVERS AND RECEIVERS SLLS059D – FEBRUARY 1990 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION 3V 1.5 V Input 1.5 V 0V 2.3 V tPLH RL = 27 Ω S1 Output Generator (see Note B) 50 Ω CL = 15 pF (see Note A) 3V tPHL VOH Y Output 2.3 V 2.3 V VOL tPHL tPLH VOH Z Output 2.3 V 2.3 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns. Figure 4. Driver Propagation-Time Test Circuit and Voltage Waveforms Output S1 3V 1.5 V Input 1.5 V 0 V or 3 V Generator (see Note B) 0V 50 Ω CL = 15 pF (see Note A) tPZH RL = 110 Ω 0.5 V VOH Output 2.3 V Voff ≈ 0 V tPHZ TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns. Figure 5. Driver Enable- and Disable-Time Test Circuit and Voltage Waveforms 5V RL = 110 Ω S1 Output 3V Input 1.5 V 1.5 V 0V 0 V or 3 V Generator (see Note B) 50 Ω tPZL CL = 15 pF (see Note A) tPLZ 5V 2.3 V Output VOL 0.5 V TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns. Figure 6. Driver Enable- and Disable-Time Test Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN751177, SN751178 DUAL DIFFERENTIAL DRIVERS AND RECEIVERS SLLS059D – FEBRUARY 1990 – REVISED MAY 1999 PARAMETER MEASUREMENT INFORMATION 3V Output Generator (see Note B) 50 Ω 1.5 V Input 0V tPLH CL = 15 pF (see Note A) 1.5 V 1.5 V 0V tPHL 1.3 V Output VOH 1.3 V VOL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns. Figure 7. Receiver Propagation-Time Test Circuit and Voltage Waveforms S1 1.5 V 2 kΩ S2 5V –1.5 V CL = 15 pF (see Note A) Generator (see Note B) 5 kΩ 1N916 or Equivalent 50 Ω S3 TEST CIRCUIT 3V 1.5 V 0 V S1 to 1.5 V S3 Closed VOH S2 Open Input tPZH Output 1.5 V 3V 1.5 V 0V Input tPZL ≈ 4.5 V 1.5 V VOL Output 0V 3V 3V Input Input 1.5 V 0V tPHZ VOH 1.5 V 0V S1 to 1.5 V S2 Closed S3 Closed Output tPLZ ≈ 1.3 V Output 0.5 V S1 to –1.5 V S2 Closed S3 Open ≈ 1.3 V S1 to –1.5 V S2 Closed S3 Closed 0.5 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns. Figure 8. Receiver Output Enable- and Disable-Time Test Circuit and Voltage Waveforms 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 4-Jun-2007 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty SN751177N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN751177NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN751177NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN751177NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN751177NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN751178N ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN751178NE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type SN751178NSR ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN751178NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN751178NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN751177NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN751178NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN751177NSR SO NS 16 2000 346.0 346.0 33.0 SN751178NSR SO NS 16 2000 346.0 346.0 33.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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