SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
D Three Differential Transceivers in One
Package
SN65LBC170DB (marked as BL170)
SN75LBC170DB (marked as BL170)
(TOP VIEW)
D Signaling Rates† Up to 30 Mbps
D Low Power and High Speed
D Designed for TIA/EIA-485, TIA/EIA-422, ISO
D
D
D
D
D
D
D
D
8482, and ANSI X3.277 (HVD SCSI Fast–20)
Applications
Common-Mode Bus Voltage Range
–7 V to 12 V
ESD Protection on Bus Terminals
Exceeds 12 kV
Driver Output Current up to ±60 mA
Thermal Shutdown Protection
Driver Positive and Negative Current
Limiting
Power-Up, Power-Down Glitch-Free
Operation
Pin-Compatible With the SN75ALS170
Available in Shrink Small-Outline Package
1D
1DIR
NC
GND
2D
2DIR
3D
3DIR
These devices combine three 3-state differential
line drivers and three differential input line
receivers, all of which operate from a single 5-V
power supply.
The driver differential outputs and the receiver
differential inputs are connected internally to form
three differential input/output (I/O) bus ports that
are designed to offer minimum loading to the bus
whenever the driver is disabled or VCC = 0. These
ports feature a wide common-mode voltage range
making the device suitable for party-line
applications over long cable runs.
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1B
1A
NC
VCC
2B
2A
3B
3A
SN65LBC170DW (marked as 65LBC170)
SN75LBC170DW (marked as 75LBC170)
(TOP VIEW)
1D
1DIR
NC
GND
NC
2D
2DIR
NC
3D
3DIR
description
The SN65LBC170 and SN75LBC170 are
monolithic integrated circuits designed for
bidirectional data communication on multipoint
bus-transmission lines. Potential applications
include serial or parallel data transmission, cabled
peripheral buses with twin axial, ribbon, or
twisted-pair cabling. These devices are suitable
for FAST-20 SCSI and can transmit or receive
data pulses as short as 25 ns, with skew less
than 3 ns.
1
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1B
1A
NC
NC
VCC
2B
2A
3B
3A
NC
NC – No internal connection
logic diagram
1DIR
1A
1B
1D
2DIR
2A
2B
2D
3DIR
3A
3B
3D
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
description (continued)
The driver’s active-high enable and the receiver’s active-low enable are tied together internally and provide a
direction input for each driver/receiver pair.
The SN75LBC170 is characterized for operation over the temperature range of 0°C to 70°C. The SN65LBC170
is characterized for operation over the temperature range of –40°C to 85°C.
AVAILABLE OPTIONS†
PACKAGE
TA
PLASTIC SHRINK SMALL-OUTLINE
(JEDEC MO-150)
PLASTIC SMALL-OUTLINE
(JEDEC MS-013)
0°C to 70°C
SN75LBC170DB
SN75LBC170DW
– 40°C to 85°C
SN65LBC170DB
SN65LBC170DW
† Add R suffix for taped and reel
Function Tables
EACH DRIVER
INPUT
D
ENABLE
DIR
H
L
OPEN
X
X
H
H
H
L
OPEN
EACH RECEIVER
OUTPUTS
B
A
DIFFERENTIAL INPUT ENABLE OUTPUT
(VA–VB)
DIR
D
L
H
VID ≥ 0.2 V
L
H
H
Z
X
H
L
L
Z
X
– 0.2 V < VID < 0.2 V
VID ≤ – 0.2 V
X
OPEN
L
L
H
L
?
L
Z
H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
equivalent input and output schematic diagrams
DIR INPUTS
A INPUT
B INPUT
VCC
VCC
100 kΩ
16 V
VCC
4 kΩ
4 kΩ
16 V
18 kΩ
18 kΩ
Input
1 kΩ
Input
Input
100 kΩ
16 V
16 V
4 kΩ
4 kΩ
100 kΩ
8V
A AND B OUTPUT
D I/O
VCC
VCC
VCC
16 V
4 kΩ
18 kΩ
Output
40 Ω
100 kΩ
4 kΩ
8V
2
POST OFFICE BOX 655303
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16 V
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
absolute maximum ratings†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Voltage range at any bus I/O terminal (steady state) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to 15 V
Voltage input range, A and B, (transient pulse through 100 Ω, see Figure 12) . . . . . . . . . . . . . . –30 V to 30 V
Voltage range at any D or DIR terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Electrostatic discharge: Human body model (A, B, GND) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 12 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 kV
Charged-device model (all pins) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Power Dissipation Rating Table
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114–A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
POWER DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR}
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
DB
995 mW
8.0 mW/°C
635 mW
515 mW
DW
1480 mW
11.8 mW/°C
950 mW
770 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
Supply voltage, VCC
Voltage at any bus I/O terminal
High-level input voltage, VIH
Low-level input voltage, VIL
Differential input voltage, VID
Output current
Operating free
free-air
air temperature,
temperature TA
MIN
NOM
MAX
UNIT
4.75
5
5.25
V
–7
12
V
2
0
VCC
0.8
V
A with respect to B
–12
12
V
Driver
–60
60
–8
8
SN75LBC170
0
70
SN65LBC170
–40
85
A, B
D DIR
D,
Receiver
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mA
°C
3
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
DRIVER SECTION
electrical characteristics over recommended operating conditions
PARAMETER
VIK
VO
Input clamp voltage
TEST CONDITIONS
D and DIR
Open-circuit output voltage (single-ended)
II = 18 mA
A or B, No load
St d t t diff
ti l output
t t voltage
lt
Steady-state
differential
magnitude‡
RL = 54 Ω,
See Figure 1
With common-mode loading, See Figure 2
∆VOD
Change in differential output voltage
magnitude, | VOD(H) | – |VOD(L) |
VOC(SS)
Steady-state common-mode output voltage
∆VOC(SS)
Change in steady-state common-mode output
voltage (VOC(H) – VOC(L))
II
IO
Input current
TYP†
–1.5
–0.7
0
No load
|VOD(SS)|
MIN
See Figure 1
D, DIR
UNIT
V
4.3
VCC
VCC
V
3.8
1
1.6
2.4
V
1
1.6
2.4
–0.2
Ω
RL = 54 Ω,
CL = 50 pF
MAX
2
0.2
2.4
V
2.8
–0.2
0.2
V
–100
100
µA
Output current with power off
VCC = 0 V,
VO = –7 V to 12 V
–700
900
µA
IOS
Short-circuit output current
VO = –7 V to 12 V, See Figure 7
–250
250
mA
ICC
Supply current (driver enabled)
D at 0 V or VCC,
DIR at VCC, No load
14
20
mA
† All typical values are at VCC = 5 V and TA = 25°C.
‡ The minimum VOD may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the possibly
lower output signal into account in determining the maximum signal-transmission distance.
switching characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
tPLH
tPHL
Differential output propagation delay, low-to high
4
8.5
12
Differential output propagation delay, high-to-low
4
8.5
11
tr
tf
Differential output rise time
3
7.5
11
3
7.5
11
tsk(p)
tsk(o)
Pulse skew | (tPLH – tPHL) |
Output skew§
tsk(pp)
tPLH
Part-to-part skew¶
RL = 54 Ω, CL = 50 pF,
F, See Figure 3
Differential output fall time
1.5
2
3
7
10
tPHL
tr
Differential output propagation delay, high-to-low
3
7.5
10
Differential output rise time
3
7.5
12
tf
tsk(p)
Differential output fall time
3
7.5
12
tPZH
tPHZ
See Figure 4,
4
(HVD SCSI double-terminated load)
Pulse skew | (tPLH – tPHL) |
Output skew§
Output disable time from high level
ns
3
1.5
Part-to-part skew¶
Output enable time to high level
ns
2
Differential output propagation delay, low-to high
tsk(o)
tsk(pp)
UNIT
2.5
See Figure 5
15
25
18
25
ns
tPZL
Output enable time to low level
10
25
See Figure 6
ns
tPLZ
Output disable time from low level
17
25
§ Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
¶ Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test
circuits.
4
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SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
RECEIVER SECTION
electrical characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
VIT+
VIT–
Positive-going differential input voltage threshold
Vhys
VOH
Hysteresis voltage (VIT+ – VIT–)
VOL
Low-level output voltage
VID = 200 mV, IOH = –8 mA, See Figure 8
VID = –200 mV, IOL = –8 mA, See Figure 8
II
Line input current
Other input = 0 V
RI
Input resistance
A, B
Negative-going differential input voltage threshold
MIN
TYP†
MAX
V
–0.2
See Figure 8
40
High-level output voltage
ICC
Supply current (receiver enabled)
† All typical values are at VCC = 5 V and TA = 25°C.
UNIT
0.2
VI = 12 V
VI = –7 V
4
4.7
0
0.2
mV
VCC
0.4
V
0.9
mA
–0.7
12
kΩ
A, B, D, and DIR open
16
mA
switching characteristics over recommended operating conditions
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
tPLH
tPHL
Propagation delay time, low-to-high level output
7
16
ns
Propagation delay time, high-to-low level output
7
16
ns
tr
tf
Receiver output rise time
3
ns
Receiver output fall time
1.3
3
ns
tPZH
tPHZ
Receiver output enable time to high level
26
40
tPZL
tPLZ
Receiver output enable time to low level
tsk(p)
tsk(o)
Pulse skew (| tPLH – tPHL |)
Output skew‡
See Figure 9
Receiver output disable time from high level
1.3
See Figure 10
40
29
Receiver output enable time to high level
See Figure 11
ns
40
40
2
ns
ns
1.5
ns
tsk(pp)
Part-to-part skew§
3
ns
‡ Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
§ Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test
circuits.
POST OFFICE BOX 655303
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5
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
IO
27 Ω
II
0 V or 3 V
IO
VO
VOD
50 pF†
27 Ω
VOC
VO
† Includes probe and jig capacitance
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 Ω
Input
VOD
60 Ω
VTEST = –7 V to 12 V
375 Ω
VTEST
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
3V
RL = 54 Ω
Signal
Generator{
Input
CL = 50 pF}
1.5 V
1.5 V
0V
VOD
tPLH
50 Ω
Output
tPHL
90% 90%
10%
tr
† PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
‡ Includes probe and jig capacitance
Figure 3. Driver Switching Test Circuit and Waveforms, 485-Loading
6
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10%
tf
VOD(H)
0V
VOD(L)
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
5V
S1
0V
375 Ω
3V
60 pF‡
165 Ω
Input
1.5 V
1.5 V
0V
tPLH
75 Ω
Signal
Generator{
tPHL
VOD
50 Ω
165 Ω
10%
60 pF‡
375 Ω
5V
VOD(H)
0V
VOD(L)
90% 90%
Output
10%
tr
tf
S2
0V
† PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
‡ Includes probe and jig capacitance
Figure 4. Driver Switching Test Circuit and Waveforms, HVD SCSI-Loading (double terminated)
A
1.5 V
Output
0 V or 3 V{
1.5 V
0V
B
RL = 110 Ω
CL = 50 pF§
Input
Generator}
3V
Input
S1
0.5 V
tPZH
Output
VOH
2.3 V
0V
50 Ω
tPHZ
† 3 V if testing A output, 0 V if testing B output
‡ PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
w Includes probe and jig capacitance
Figure 5. Driver Enable/Disable Test, High Output
5V
RL = 110 Ω
A
Input
S1
0 V or 3 V{
3V
1.5 V
1.5 V
0V
Output
tPZL
B
CL = 50 pF§
Input
Output
tPLZ
5V
2.3 V
VOL
Generator‡
50 Ω
0.5 V
† 0 V if testing A output, 3 V if testing B output
‡ PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
w Includes probe and jig capacitance
Figure 6. Driver Enable/Disable Test, Low Output
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7
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
IOS
VO
IO
VID
Voltage
Source
VO
Figure 7. Driver Short-Circuit Test
Generator{
Figure 8. Receiver DC Parameters
50 Ω
Input B
A
D
VID
Generator{
1.5 V
Input A
0V
B
CL = 15 pF}
50 Ω
3V
IO
tPLH
VO
tPHL
Output
1.5 V
10%
90%
90%
VOH
1.5 V
10% V
OL
tr
† PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
‡ Includes probe and jig capacitance
tf
Figure 9. Receiver Switching Test Circuit and Waveforms
1.5 V
VCC
A
D
B
1 kΩ
1.5 V
0V
tPZH
tPHZ
1.5 V
50 Ω
VOH
VOH –0.5 V
GND
† PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
‡ Includes probe and jig capacitance
Figure 10. Receiver Enable/Disable Test, High Output
8
1.5 V
CL = 15 pF}
DIR
Generator{
3V
DIR
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
PARAMETER MEASUREMENT INFORMATION
–1.5 V
VCC
A
D
B
DIR
3V
DIR
1 kΩ
1.5 V
1.5 V
0V
CL = 15 pF}
tPZL
tPLZ
VCC
1.5 V
Generator{
50 Ω
VOL + 0.5 V
VOL
† PRR = 1 MHz, 50% Duty Cycle, tr < 6 ns, tf < 6 ns, Zo = 50 Ω
‡ Includes probe and jig capacitance
Figure 11. Receiver Enable/Disable Test, Low Output
100 Ω
Pulse
Generator,
15-µs Duration,
1% Duty Cycle
VTEST
0V
15 µs
1.5 ms
–VTEST
Figure 12. Test Circuit and Waveform, Transient Over Voltage Test
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SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
2.5
3.5
VOD – Differential Output Voltage – V
VOD – Differential Output Voltage – V
4
3
VCC = 5.25 V
2.5
VCC = 5 V
2
1.5
VCC = 4.75 V
1
0.5
0
0
20
40
60
80
IO – Output Current – mA
VCC = 5 V
1.5
VCC = 4.75 V
1
0.5
0
–60
100
VCC = 5.25 V
2
–40
Figure 13
165
160
10
I CC – Supply Current – mA
Driver Propagation Delay – ns
11
SCSI Load
9
8
RS–485 Load
6
All 3 Channels Driving
RL = 54 Ω,
CL = 50 pF (Each Channel),
Pseudorandom NRZ Data
155
150
145
140
5
–20
0
20
40
60
TA – Free-Air Temperature – °C
80
135
0.1
Figure 15
10
100
SUPPLY CURRENT
vs
SIGNALING RATE
12
4
–40
80
Figure 14
DRIVER PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
7
–20
0
20
40
60
TA – Free-Air Temperature – °C
1
10
Signaling Rate – Mbps
Figure 16
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100
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
RECEIVER PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
800
t pd – Receiver Propagation Delay Time – ns
12
600
Bus Input Current – µ A
VCC = 0 V
400
VCC = 5 V
200
0
–200
–400
–600
–10
–5
0
5
10
11
10
tPHL
9
tPLH
8
7
6
5
4
–40
15
–20
Bus Input Voltage – V
Figure 17
0
20
40
60
TA – Free-Air Temperature°C
80
Figure 18
SN65LBC170
(as Driver)
15 Meters, Cat. 5
Twisted-Pair Cable
Signal
Generator
SN65LBC170
(as Receiver)
100 Ω
15 pF
Figure 19. Circuit Diagram for Signaling Characteristics
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11
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
25 ns
Receiver Output
(5 V/div)
Figure 20. Signal Waveforms at 30 Mbps
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
12.5 ns
Receiver Output
(5 V/div)
Figure 21. Eye Patterns, Pseudorandom Data at 30 Mbps
12
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SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
TYPICAL CHARACTERISTICS
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
25 ns
Receiver Output
(5 V/div)
Figure 22. Signal Waveforms at 50 Mbps
Driver Input
(5 V/div)
Driver Output
(2 V/div)
Receiver Input
(2 V/div)
12.5 ns
Receiver Output
(5 V/div)
Figure 23. Eye Patterns, Pseudorandom Data at 50 Mbps
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SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,15 NOM
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /D 09/00
NOTES: A.
B.
C.
D.
14
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SN65LBC170, SN75LBC170
TRIPLE DIFFERENTIAL TRANSCEIVERS
SLLS459B – NOVEMBER 2000 – REVISED FEBRUARY 2002
MECHANICAL DATA
DW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
16 PINS SHOWN
0.050 (1,27)
0.020 (0,51)
0.014 (0,35)
16
0.010 (0,25) M
9
0.419 (10,65)
0.400 (10,15)
0.010 (0,25) NOM
0.299 (7,59)
0.291 (7,39)
Gage Plane
0.010 (0,25)
1
8
0°–ā8°
A
0.050 (1,27)
0.016 (0,40)
Seating Plane
0.104 (2,65) MAX
0.012 (0,30)
0.004 (0,10)
PINS **
0.004 (0,10)
16
20
24
28
A MAX
0.410
(10,41)
0.510
(12,95)
0.610
(15,49)
0.710
(18,03)
A MIN
0.400
(10,16)
0.500
(12,70)
0.600
(15,24)
0.700
(17,78)
DIM
4040000 / D 01/00
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MS-013
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
SN65LBC170DB
ACTIVE
SSOP
DB
16
80
None
CU NIPDAU
Level-1-220C-UNLIM
SN65LBC170DBR
ACTIVE
SSOP
DB
16
2000
None
CU NIPDAU
Level-1-220C-UNLIM
SN65LBC170DW
ACTIVE
SOIC
DW
20
25
None
CU NIPDAU
Level-1-220C-UNLIM
SN65LBC170DWR
ACTIVE
SOIC
DW
20
2500
None
CU NIPDAU
Level-1-220C-UNLIM
SN75LBC170DB
ACTIVE
SSOP
DB
16
80
None
CU NIPDAU
Level-1-220C-UNLIM
Level-1-220C-UNLIM
SN75LBC170DBR
ACTIVE
SSOP
DB
16
2000
None
CU NIPDAU
SN75LBC170DBRG4
PREVIEW
SSOP
DB
16
2000
None
Call TI
SN75LBC170DW
ACTIVE
SOIC
DW
20
50
None
CU NIPDAU
Level-1-220C-UNLIM
SN75LBC170DWR
ACTIVE
SOIC
DW
20
2500
None
CU NIPDAU
Level-1-220C-UNLIM
Call TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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