SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com FLATLINK™ TRANSMITTER Check for Samples: SN75LVDS83A FEATURES 1 • 2 • • • • • • • • LVDS Display Serdes Interfaces Directly to LCD Display Panels with Integrated LVDS Package Options: 8.1mm x 14mm TSSOP 3.3V Tolerant Data Inputs Transfer Rate up to 100Mpps (Mega Pixel Per Second); Pixel Clock Frequency Range 10MHz to 100MHz Suited for Display Resolutions Ranging From HVGA up to HD With Low EMI Operates From a Single 3.3V Supply and 170mW (typ.) at 75MHz 28 Data Channels Plus Clock In Low-Voltage TTL to 4 Data Channels Plus Clock Out • • • Low-Voltage Differential Consumes Less Than 1mW When Disabled Selectable Rising or Falling Clock Edge Triggered Inputs ESD: 5kV HBM Support Spread Spectrum Clocking (SSC) Compatible with all OMAP™2x, OMAP™3x, and DaVinci™ Application Processors APPLICATIONS • • • LCD Display Panel Driver UMPC and Netbook PC Digital Picture Frame DESCRIPTION The SN75LVDS83A FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS receiver. When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. swiv Application processor TM (e.g. OMAP ) el SN75LVDS83A FlatLinkTM Transmitter TSSOP: 8 x 14mm DGG 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. OMAP, DaVinci, FlatLink are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2011, Texas Instruments Incorporated SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DESCRIPTION (CONTINUED) The SN75LVDS83A requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is selecting a clock rising edge by inputting a high level to CLKSEL or a falling edge with a low-level input, and the possible use of the Shutdown/Clear (SHTDN). SHTDN is an active-low input to inhibit the clock, and shut off the LVDS output drivers for lower power consumption. A low-level on this signal clears all internal registers to a low-level. The SN75LVDS83A is characterized for operation over ambient air temperatures of -10°C to 70°C. Alternative device option: The SN75LVDS83B is an alternative to the SN75LVDS83A for clock frequency range of 10MHz–135MHz. The SN75LVDS83B is available in a smaller BGA package in addition to the TSSOP package. ORDERING INFORMATION (1) (1) PART NUMBER PART MARKING PACKAGE SN75LVDS83ADGG LVDS83A 56-pin DGG TUBE SN75LVDS83ADGGR LVDS83A 56-pin DGG LARGE T&R For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or refer to our web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) VALUE UNIT -0.5 to 4 V Voltage range at any output terminal –0.5 to VCC + 0.5 V Voltage range at any input terminal –0.5 to VCC + 0.5 V Continuous power dissipation See the Dissipation Rating Table Supply voltage range, VCC, LVDSVCC, PLLVCC (2) Human Body Model (HBM) (3) all pins ESD rating Charged Device Model (CDM) (4) Machine Model (MM) (5) all pins (1) (2) (3) (4) (5) 2 all pins 5 kV 500 V 150 V Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. All voltages are with respect to the GND terminals. In accordance with JEDEC Standard 22, Test Method A114-A. In accordance with JEDEC Standard 22, Test Method C101. In accordance with JEDEC Standard 22, Test Method A115-A. Copyright © 2009–2011, Texas Instruments Incorporated SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX Supply voltage, VCC 3 3.3 3.6 LVDS output supply voltage, LVDSVCC 3 3.3 3.6 PLL analog supply voltage, PLLVCC 3 3.3 3.6 Power supply noise on any VCC terminal UNIT V 0.1 High-level input voltage, VIH VCC/2 + 0.5 Low-level input voltage, VIL Differential load impedance, ZL Operating free-air temperature, TA V VCC/2 - 0.5 V 90 132 Ω -10 70 C DISSIPATION RATINGS PACKAGE CIRCUIT BOARD MODEL (1) TJA ≤ 25°C DERATING FACTOR (2) ABOVE TJA = 25°C TJA = 70°C POWER RATING Low-K 1111 mW 12.3mW/°C 555 mW High-K 1730 mW 19mW/°C 865 mW DGG (1) (2) In accordance with the High-K and Low-K thermal metric definitions of EIA/JESD51-2. This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. TIMING REQUIREMENTS PARAMETER Input clock period, tc MIN MAX UNIT 10 100 ns Input clock modulation (SSC) w/ modulation frequency 30 kHz 8% w/ modulation frequency 50 kHz High-level input clock pulse width duration, tw 6% 0.4 tc Input signal transition time, tt Data set up time, D0 through D27 before CLKIN (See Figure 3) Data hold time, D0 through D27 after CLKIN Copyright © 2009–2011, Texas Instruments Incorporated 0.6 tc ns 3 ns 2 ns 0.8 ns 3 SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com DGG PACKAGE (TOP VIEW) VCC 1 56 D5 2 3 55 54 D7 GND D8 4 53 5 52 GND D1 6 51 D0 D9 D10 7 50 8 49 D27 GND VCC D11 9 10 48 47 D12 11 46 D13 12 45 Y1P GND D14 13 44 14 15 43 42 LVDSVCC GND Y2M 16 41 17 18 40 39 19 38 D19 GND 20 37 CLKOUTP Y3M Y3P 21 36 GND D20 22 23 35 34 GND D21 D22 24 33 D23 25 32 VCC D24 D25 26 31 27 30 28 29 D6 D15 D16 CLKSEL D17 D18 D4 D3 D2 Y0M Y0P Y1M Y2P CLKOUTM PLLVCC GND SHTDN CLKIN D26 GND DGG PIN LIST 4 Pin # Signal Pin # Signal Pin # Signal Pin # Signal 1 VCC 15 D15 29 GND 43 GND 2 D5 16 D16 30 D26 44 LVDSVCC 3 D6 17 CLKSEL 31 CLKIN 45 Y1P 4 D7 18 D17 32 SHTDN 46 Y1M 5 GND 19 D18 33 GND 47 Y0P 6 D8 20 D19 34 PLLVCC 48 Y0M 7 D9 21 GND 35 GND 49 GND 8 D10 22 D20 36 GND 50 D27 D0 9 VCC 23 D21 37 Y3P 51 10 D11 24 D22 38 Y3M 52 D1 11 D12 25 D23 39 CLKOUTP 53 GND 12 D13 26 VCC 40 CLKOUTM 54 D2 13 GND 27 D24 41 Y2P 55 D3 14 D14 28 D25 42 Y2M 56 D4 Copyright © 2009–2011, Texas Instruments Incorporated SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com PIN FUNCTIONS TERMINAL I/O Y0P, Y0M, Y1P, Y1M, Y2P, Y2M Y3P, Y3M DESCRIPTION Differential LVDS data outputs. Outputs are high-impedance when SHTDN is pulled low (de-asserted) LVDS Out Differential LVDS Data outputs. Output is high-impedance when SHTDN is pulled low (de-asserted). Note: if the application only requires 18-bit color, this output can be left open. CLKP, CLKM Differential LVDS pixel clock output. Output is high-impedance when SHTDN is pulled low (de-asserted). D0 – D27 Data inputs. To connect a graphic source successfully to a display, the bit assignment of D[27:0] is critical (and not necessarily intuitive). For input bit assignment see Figure 14 to Figure 17 for details. Note: if application only requires 18-bit color, connect unused inputs D5, D10, D11, D16, D17, D23, and D27 to GND. CLKIN CMOS IN with pulldn Input pixel clock; rising or falling clock polarity is selectable by Control input CLKSEL. SHTDN Device shut down; pull low (de-assert) to shut down the device (low power, resets all registers) and high (assert) for normal operation. CLKSEL Selects between rising edge input clock trigger (CLKSEL = VIH) and falling edge input clock trigger (CLKSEL = VIL). VCC 3.3V digital Supply Voltage PLLVCC LVDSVCC GND (1) Power Supply (1) 3.3V PLL analog supply 3.3V LVDS output analog supply Supply Ground for VCC, LVDSVCC, and PLLVCC. For a multilayer pcb, it is recommended to keep one common GND layer underneath the device and connect all ground terminals directly to this plane. Copyright © 2009–2011, Texas Instruments Incorporated 5 SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM Parallel-Load 7-bit Shift Register D0, D1, D2, D3, D4, D6, D7 7 Y0P A,B,...G SHIFT/LOAD >CLK Y0M Parallel-Load 7-bit Shift Register D8, D9, D12, D13, D14, D15, D18 7 Y1P A,B,...G SHIFT/LOAD >CLK Y1M Parallel-Load 7-bit Shift Register D19, D20, D21, D22, D24, D25, D26 7 Y2P A,B,...G SHIFT/LOAD >CLK Y2M Parallel-Load 7-bit Shift Register D27, D5, D10, D11, D16, D17, D23 7 Y3P Y3M A,B,...G SHIFT/LOAD >CLK Control Logic SHTDN 7X Clock/PLL 7XCLK CLKIN CLKOUTP CLKOUTM >CLK CLKINH CLKSEL 6 RISING/FALLING EDGE Copyright © 2009–2011, Texas Instruments Incorporated SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com Dn CLKIN or CLKIN CLKOUT Previous cycle Next Current cycle Y0 D0-1 D7 D6 D4 D3 D2 D1 D0 D7+1 Y1 D8-1 D18 D15 D14 D13 D12 D9 D8 D18+1 Y2 D19-1 D26 D25 D24 D22 D21 D20 D19 D26+1 Y3 D27-1 D23 D17 D16 D11 D10 D5 D27 D23+1 Figure 1. Typical SN75LVDS83A Load and Shift Sequences LVDSVCC VCC 5W D or SHTDN 50W 7V YnP or YnM 10kW 300kW 7V Figure 2. Equivalent Input and Output Schematic Diagrams Copyright © 2009–2011, Texas Instruments Incorporated 7 SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER VT Input voltage threshold |VOD| Differential steady-state output voltage magnitude TEST CONDITIONS MIN TYP (1) MAX VCC/2 250 UNIT V 450 mV RL = 100Ω, See Figure 4 Δ|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states VOC(SS) Steady-state common-mode output voltage VOC(PP) Peak-to-peak common-mode output voltage See Figure 4 tR/F (Dx, CLKin) = 1ns IIH High-level input current VIH = VCC IIL Low-level input current VIL = 0 V ±10 μA VOY = 0 V ±24 mA VOD = 0 V ±12 mA ±20 μA 1 1.125 IOS Short-circuit output current IOZ High-impedance state output current VO = 0 V to VCC Rpdn Input pull-down integrated resistor on all inputs (Dx, CLKSEL, SHTDN, CLKIN) IQ Quiescent current ICC Supply current (average) 1.375 disabled, all inputs at GND; SHTDN = VIL (1) 8 mV V 100 mV 25 μA 100 kΩ 2 100 μA SHTDN = VIH, RL = 100Ω (5 places), grayscale pattern (Figure 5) VCC = 3.3V, fCLK = 75MHz 52.3 62.2 mA SHTDN = VIH, RL = 100Ω (5 places), 50% transition density pattern (Figure 5), VCC = 3.3V, fCLK = 75MHz 53.9 67.1 mA SHTDN = VIH, RL = 100Ω (5 places), worst-case pattern (Figure 6), VCC = 3.6V, fCLK = 75MHz 65 79.3 mA 96.8 mA SHTDN = VIH, RL = 100Ω (5 places), worst-case pattern (Figure 6), fCLK = 100MHz CI 35 Input capacitance 2 pF All typical values are at VCC = 3.3 V, TA = 25°C. Copyright © 2009–2011, Texas Instruments Incorporated SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX -0.1 0 0.1 ns UNIT t0 Delay time, CLKOUT↑ after Yn valid (serial bit position 0, equal D1, D9, D20, D5) t1 Delay time, CLKOUT↑ after Yn valid (serial bit position 1, equal D0, D8, D19, D27) 1 /7 tc - 0.1 1 /7 tc + 0.1 ns t2 Delay time, CLKOUT↑ after Yn valid (serial bit position 2, equal D7, D18, D26. D23) 2 /7 tc - 0.1 2 /7 tc + 0.1 ns t3 Delay time, CLKOUT↑ after Yn valid (serial bit position 3; equal D6, D15, D25, D17) 3 /7 tc - 0.1 3 /7 tc + 0.1 ns t4 Delay time, CLKOUT↑ after Yn valid (serial bit position 4, equal D4, D14, D24, D16) 4 /7 tc - 0.1 4 /7 tc + 0.1 ns t5 Delay time, CLKOUT↑ after Yn valid (serial bit position 5, equal D3, D13, D22, D11) 5 /7 tc - 0.1 5 /7 tc + 0.1 ns t6 Delay time, CLKOUT↑ after Yn valid (serial bit position 6, equal D2, D12, D21, D10) 6 /7 tc - 0.1 6 /7 tc + 0.1 ns tsk(o) Output skew, tn - n/7 tC Target Potential adjustment after char 0.1 (0.15) ns t7 Delay time, CLKIN↓ to CLKOUT↓ tC = 10 ns (±0.2%), |Input clock jitter| < 50 ps, See Figure 7 tc(o) Output clock period Δtc(o) Output clock cycle-to-cycle jitter (3) See Figure 7, tC = 10 ns, |Input clock jitter| < 25 ps (2) -0.1 (-0.15) TBD ns tc ns tC = 10 ns; clean reference clock, see Figure 8 ±40 tC = 10 ns with 0.05UI added noise modulated at 3MHz, see Figure 8 ±44 tC = 10 ns with 0.1UI added noise modulated at 3MHz, see Figure 8 ±42 ps tw High-level output clock pulse duration tr/f Differential output voltage transition time (tr or tf) fCLKSee Figure 4 ten Enable time, SHTDN↑ to phase lock (Yn valid) fCLK = 100MHz, See Figure 9 6 ms tdis Disable time, SHTDN↓ to off-state (CLKOUT high-impedance) fCLK = 100MHz, See Figure 10 7 ns (1) (2) (3) 4 /7 tc 225 ns 500 ps All typical values are at VCC = 3.3 V, TA = 25°C. |Input clock jitter| is the magnitude of the change in the input clock period. The output clock cycle-to-cycle jitter is the largest recorded change in the output clock period from one cycle to the next cycle observed over 15,000 cycles. Tektronix TDSJIT3 Jitter Analysis software was used to derive the maximum and minimum jitter value. Copyright © 2009–2011, Texas Instruments Incorporated 9 SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION tsu thold Dn CLKIN All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns. CLKSEL = 0V. Figure 3. Set Up and Hold Time Definition 49.9W ± 1% (2 PLCS) YP VOD VOC YM 100% 80% VOD(H) 0V VOD(L) 20% 0% tf tr VOC(PP) VOC(SS) VOC(SS) 0V Figure 4. Test Load and Voltage Definitions for LVDS Outputs. CLKIN D0,8,16 D1,9,17 D2,10,18 D3,11,19 D4-7,12-15,20-23 D24-27 The 16 grayscale test pattern test device power consumption for a typical display pattern. Figure 5. 16 Grayscale Test Pattern 10 Copyright © 2009–2011, Texas Instruments Incorporated SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) T CLKIN EVEN Dn ODD Dn The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Figure 6. Worst-Case Power Test Pattern t7 CLKIN CLKOUT t6 t5 t4 t3 t2 t1 t0 Yn ~2.5V 1.40V CLKIN VOD(H) CLKOUT or Yn 0.00V ~0.5V t7 VOD(L) t0-6 CLKOUT is shown with CLKSEL at high-level. CLKIN polarity depends on CLKSEL input level. Figure 7. SN75LVDS83A Timing Definitions Copyright © 2009–2011, Texas Instruments Incorporated 11 SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Reference + Device Under Test VCO + Modulation v(t) = A sin(2 pfmodt) HP8656B Signal Generator, 0.1 MHz-990 MHz RF Output HP8665A Synthesized Signal Generator, 0.1 MHz-4200 MHz Device Under Test RF Output Modulation Input CLKIN CLKOUT DTS2070C Digital TimeScope Input Figure 8. Output Clock Jitter Test Set Up CLKIN Dn ten SHTDN Invalid Yn Valid Figure 9. Enable Time Waveforms CLKIN tdis SHTDN CLKOUT Figure 10. Disable Time Waveforms 12 Copyright © 2009–2011, Texas Instruments Incorporated SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS AVERAGE GRAYSCALE ICC vs CLOCK FREQUENCY 800 Total Device Current (Using Grayscale pattern) Over Pixel Clock Frequency Output Jitter 90 700 80 600 Period Clock Jitter - ps-pp ICC - Average Supply Current - mA 100 OUTPUT CLOCK JITTER vs INPUT CLOCK JITTER 70 VCC = 3.6V 60 50 VCC = 3.3V 40 Input Jitter 500 400 300 200 CLK Frequency During Test = 100MHz 30 100 VCC = 3V 20 10 20 30 40 50 60 70 80 90 100 0 0.01 fclk - Clock Frequency - MHz 0.10 1 10 f(mod) - Input Modular Frequency - MHz Figure 11. Figure 12. TYPICAL PRBS OUTPUT SIGNAL OVER ONE CLOCK PERIOD PRBS Data Signal V - Voltage - 80mV/div CLKL Signal Clock Signal: 100MHz tk - Time - 1.2ns/div Figure 13. Copyright © 2009–2011, Texas Instruments Incorporated 13 SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com APPLICATION INFORMATION This section describes the power up sequence, provides information on device connectivity to various GPU and LCD display panels, and offers a pcb routing example. Power Up Sequence The SN75LVDS83A does not require a specific power up sequence. The user experience can be impacted by the way a system powers up and powers down an LCD screen. The following sequence is recommended: Power up sequence (SN75LVDS83A SHTDN input initially low): 1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off. 2. Wait for additional 0-200ms to ensure display noise will not occur. 3. Enable video source output; start sending black video data. 4. Toggle LVDS83A shutdown to SHTDN = VIH 5. Send >1ms of black video data; this allows the LVDS83A to be phase locked, and the display to show black data first. 6. Start sending true image data. 7. Enable backlight. Power Down sequence (SN75LVDS83A SHTDN input initially high): 1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low. 2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive this for >2 frame times. 3. Set SN75LVDS83A input SHTDN = GND; wait for 250ns. 4. Disable the video output of the video source. 5. Remove power from the LCD panel for lowest system power. Signal Connectivity While there is no formal industry standardized specification for the input interface of LVDS LCD panels, the industry has aligned over the years on a certain data format (bit order). Figure 14 through Figure 17 show how each signal should be connected from the graphic source through the SN75LVDS83A input, output and LVDS LCD panel input. Detailed notes are provided with each figure. 14 Copyright © 2009–2011, Texas Instruments Incorporated SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com 4.8k 3.3V Rpullup Rpulldown (See Note A) Y0M Y0P 100 FPC Cable LVDS timing 100 Controller (8bpc, 24bpp) Panel connector Y2M Y2P to column driver Main board connector Y1M Y1P 100 Y3M Y3P 100 CLKOUTM CLKOUTP 100 to row driver 24-bpp LCD Display VCC PLLVCC LVDSVCC CLKSEL D27 D5 D0 D1 D2 D3 D4 D6 D10 D11 D7 D8 D9 D12 D13 D14 D16 D17 D15 D18 D19 D20 D21 D22 D24 D25 D26 D23 CLKIN SHTDN FORMAT2 D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN GND R0(LSB) R1 R2 R3 R4 R5 R6 R7(MSB) G0(LSB) G1 G2 G3 G4 G5 G6 G7(MSB) B0(LSB) B1 B2 B3 B4 B5 B6 B7(MSB) HSYNC VSYNC ENABLE RSVD CLK SN75LVDS83A FORMAT1 GND 24-bpc GPU 3.3V C1* 3.3V C2* (See Note B) Main Board Note A. FORMAT: The majority of 24-bit LCD display panels require the two LSBs of each color to be transferred over the 4th serial data output Y3. Other 24-bit LCD display panels require the two LSB of each color to be transmitted over the Y3 output. The system designer needs to verify which format is expected by checking the LCD display data sheet. • Format 1: use with displays expecting the 2 MSB to be transmitted over the 4th data channel Y3. This is the dominant data format in today's LCD panels • Format 2: use with displays expecting the 2 LSB to be transmitted over the 4th data channel. Note B. Rpullup: install only to use rising edge triggered clocking. Rpulldown: install only to use falling edge triggered clocking. • C1: decoupling cap for the VDDIO supply; install at least 1 × 0.1μF and 1 × 0.01μF • C2: decoupling cap for the VDD supply; install at least 1 × 0.1μF and 1 × 0.01μF. Figure 14. 24-Bit Color Host to 24-bit LCD Panel Application Copyright © 2009–2011, Texas Instruments Incorporated 15 SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com SN75LVDS83A to column driver LVDS timing 100 Controller (6-bpc, 18-bpp) Panel connector FPC Cable 100 to row driver 18-bpp LCD Display Y3M Y3P (See Note A) 4.8k 3.3V 100 CLKOUTM CLKOUTP VCC GND HSYNC VSYNC ENABLE RSVD CLK Y1M Y1P Rpullup Rpulldow VCC PLLVCC LVDSVCC B0(LSB) B1 B2 B3 B4 B5(MSB) 100 Y2M Y2P SHTDN G0(LSB) G1 G2 G3 G4 G5(MSB) Y0M Y0P Main board connector D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN GND R0(LSB) R1 R2 R3 R4 R5(MSB) CLKSEL 18-bpp GPU 3.3V C1* 3.3V C2* (See Note B) Main Board Note A. Leave output Y3 NC. Note B.Rpullup: install only to use rising edge triggered clocking. Rpulldown: install only to use falling edge triggered clocking. • C1: decoupling cap for the VDDIO supply; install at least 1 × 0.1μF and 1 × 0.01μF. • C2: decoupling cap for the VDD supply; install at least 1 × 0.1μF and 1 × 0.01μF. Figure 15. 18-Bit Color Host to 18-Bit Color LCD Panel Display Application 16 Copyright © 2009–2011, Texas Instruments Incorporated SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com 12-bpp GPU SN75LVDS83A (See Note B) B2or VCC B3 or GND B0 B1 B2 B3(MSB) Y1M Y1P 100 FPC Cable LVDS timing 100 Controller (6-bpc, 18-bpp) Panel connector Main board connector to column driver CLKOUTM CLKOUTP 100 to row driver 18-bpp LCD Display Y3M Y3P (See Note A) VCC GND HSYNC VSYNC ENABLE RSVD CLK 100 4.8k 3.3V Rpullup Rpulldown VCC PLLVCC LVDSVCC (See Note B) Y0M Y0P Y2M Y2P GND G2or VCC G3 or GND G0 G1 G2 G3(MSB) CLKSEL (See Note B) D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN SHTDN R2or VCC R3 or GND R0 R1 R2 R3(MSB) 3.3V C1* 3.3V C2* (See Note C) Main Board Note A. Leave output Y3 N.C. Note B. R3, G3, B3: this MSB of each color also connects to the 5th bit of each color for increased dynamic range of the entire color space at the expense of none-linear step sizes between each step. For linear steps with less dynamic range, connect D1, D8, and D18 to GND. R2, G2, B2: these outputs also connects to the LSB of each color for increased, dynamic range of the entire color space at the expense of none-linear step sizes between each step. For linear steps with less dynamic range, connect D0, D7, and D15 to VCC. Note C.Rpullup: install only to use rising edge triggered clocking. Rpulldown: install only to use falling edge triggered clocking. • C1: decoupling cap for the VDDIO supply; install at least 1 × 0.1μF and 1 × 0.01μF. • C2: decoupling cap for the VDD supply; install at least 1 × 0.1μF and 1 × 0.01μF. Figure 16. 12-Bit Color Host to 18-Bit Color LCD Panel Display Application Copyright © 2009–2011, Texas Instruments Incorporated 17 SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com 24-bpp GPU SN75LVDS83A R0 and R1: N.C. G7(MSB) (See Note B) B0 and B1: N.C. (See Note B) B2 B3 B4 B5 B6 100 to column driver LVDS timing 100 Controller (6-bpc, 18-bpp) Panel connector FPC Cable CLKOUTM CLKOUTP 100 to row driver 18-bpp LCD Display Y3M Y3P (See Note A) 4.8k 3.3V Y1M Y1P Y2M Y2P VCC GND B7(MSB) B0 -> N.C. B1 -> N.C. HSYNC VSYNC ENABLE RSVD CLK 100 Main board connector G2 G3 G4 G5 G6 Y0M Y0P Rpullup Rpulldown VCC PLLVCC LVDSVCC G0 and G1: N.C. (See Note B) GND R7(MSB) D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN CLKSEL R2 R3 R4 R5 R6 SHTDN (See Note B) 3.3V C1* 3.3V C2* (See Note C) Main Board Note A. Leave output Y3 NC. Note B. R0, R1, G0, G1, B0, B1: For improved image quality, the GPU should dither the 24-bit output pixel down to18-bit per pixel. NoteC.Rpullup: install only to use rising edge triggered clocking. Rpulldown: install only to use falling edge triggered clocking. • C1: decoupling cap for the VDDIO supply; install at least 1 × 0.1μF and 1 × 0.01μF. • C2: decoupling cap for the VDD supply; install at least 1 × 0.1μF and 1 × 0.01μF. Figure 17. 24-Bit Color Host to 18-Bit Color LCD Panel Display Application 18 Copyright © 2009–2011, Texas Instruments Incorporated SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com Typical Application Schematic Figure 18 represents the schematic drawing of the SN75LVDS83A evaluation module. J1 U1H GND1 GND2 GND3 GND4 GND5 GND6 GND7 PLLGND LVDSGND1 LVDSGND2 J3 CLKM CLKP Y0P Y0M Y1P Y1M Y2P Y2M VCC R4 4.7k R5 4.7k R6 4.7k R7 4.7k R8 4.7k R9 4.7k Y3P Y3M R10 4.7k JMP1 U1B D0 D1 D2 D3 D4 D6 D7 D0 D1 D2 D3 D4 D6 D7 D1 D2 G2 G1 J5 E1 E2 sma_surface J6 sma_surface C2 C1 J7 sma_surface SN65LVDS83AZQL J8 sma_surface J9 sma_surface 14 Header 7x2 J10 sma_surface VCC R11 4.7k R12 4.7k R13 4.7k R14 4.7k R15 4.7k R16 4.7k R17 4.7k sma_surface JMP2 U1C K6 J6 G5 G6 F6 E5 D5 J4 sma_surface H2 H1 1 2 SN65LVDS83AZQL D8 D9 D12 D13 D14 D15 D18 sma_surface U1A SN65LVDS83AZQL J2 K1 K2 J3 K3 J4 K5 J2 sma_surface C3 C5 D3 F5 G3 H3 J5 A1 B1 F2 D8 D9 D12 D13 D14 D15 D18 1 2 VCC VCC 14 SN65LVDS83AZQL R2 R1 4.7k Header 7x2 VCC R18 4.7k R19 4.7k R20 R21 4.7k 4.7k R22 4.7k R23 4.7k R24 4.7k D19 D20 D21 D22 D24 D25 D 26 C6 B6 B5 A6 A4 B4 A3 JMP6 U1G JMP3 U1D D19 D20 D21 D22 D24 D25 D26 SHTDN CLKSEL 1 2 B3 D4 SHTDN CLKSEL 1 2 3 4 Header 2x2 SN65LVDS83AZQL 14 U1J NC1 NC2 NC3 NC4 Header 7x2 SN65LVDS83AZQL VCC R25 4.7k R26 4.7k R27 4.7k R28 4.7k R29 4.7k R30 4.7k E3 E4 F3 F4 SN65LVDS83AZQL R31 4.7k JMP4 U1E D5 D10 D11 D16 D17 D23 D27 K4 H4 H6 E6 D6 A5 J1 D5 D10 D11 D16 D17 D23 D27 VCC 1 2 VCC U1I VCC PLLVCC LVDSVCC 14 VCC VCC Header 7x2 SN65LVDS83AZQL G4 B2 F1 H5 C4 SN65LVDS83AZQL VCC VCC C31 1uF C32 0.1uF C33 0.01uF VCC C34 1uF C35 0.1uF C36 0.01uF VCC C40 1uF C41 0.1uF C42 0.01uF C37 1uF C38 0.1uF C39 0.01uF PLACE UNDER LVDS83B (bottom pcb side) Figure 18. Schematic Example (SN75LVDS83A Evaluation Board) Copyright © 2009–2011, Texas Instruments Incorporated 19 SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com REVISION HISTORY Changes from Original (June 2009) to Revision A Page • Changed Description text From: Alternative device option: The SN75LVDS83A is an alternative... To: Alternative device option: The SN75LVDS83B is an alternative... ......................................................................................................... 2 • Changed Figure 13 - TYPICAL PRBS OUTPUT SIGNAL OVER ONE CLOCK PERIOD ................................................. 13 Changes from Revision A (June 2009) to Revision B • Changed the data sheet From Product Preview To Production. .......................................................................................... 1 Changes from Revision B (July 2009) to Revision C • 20 Page Deleted sentence in the Pin Functions table for entry D0 - D27 - "supports 1.8V to 3.3V input voltage selectable by VDD supply." ......................................................................................................................................................................... 5 Changes from Revision C (JAugust 2009) to Revision D • Page Page Changed Figure 14: From G7(LSB) To G7(MSB) .............................................................................................................. 15 Copyright © 2009–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 28-Mar-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) SN75LVDS83ADGG ACTIVE TSSOP DGG 56 35 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR SN75LVDS83ADGGR ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN75LVDS83ADGGR Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75LVDS83ADGGR TSSOP DGG 56 2000 367.0 367.0 45.0 Pack Materials-Page 2 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. 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