ISO7420-Q1 ISO7421A-Q1 www.ti.com SLLSE14A – MARCH 2012 – REVISED JUNE 2012 LOW-POWER DUAL DIGITAL ISOLATORS FEATURES 1 • • • • • • • • VCC1 1 INA 2 INB 3 GND1 4 Isolation ISO7420 D PACKAGE (TOP VIEW) Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to +125°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H3A – Device CDM ESD Classification Level C5 High Signaling Rate: 50 Mbps Low Power Consumption Low Propagation Delay – 9 ns (Typ) Low Skew – 300 ps (Typ) 4 kVpeak Maximum Isolation, 2.5 kVrms per UL 1577, IEC/VDE and CSA Approved, IEC 609501, IEC 61010-1 End Equipment Standards Approved. All Approvals Pending. 50 kV/μs Transient Immunity (Typ) Over 25-Year Isolation Integrity at Rated Voltage Operates From 3-V to 5.5-V Supply and Logic Levels 8 VCC2 7 OUTA 6 OUTB 5 GND2 ISO7421A D PACKAGE (TOP VIEW) VCC1 1 OUTA 2 INB 3 GND1 4 Isolation • • 8 VCC2 7 INA 6 OUTB 5 GND2 DESCRIPTION The ISO7420 and ISO7421A provide galvanic isolation up to 2.5 kVrms for 1 minute per UL. These digital isolators have two isolated channels with bidirectional channel configuration. Each isolation channel has a logic input and output buffer separated by a silicon dioxide (SiO2) insulation barrier. Used in conjunction with isolated power supplies, these devices prevent noise currents on a data bus or other circuit from entering the local ground and interfering with or damaging sensitive circuitry. The devices have TTL input thresholds and require two supply voltages from 3 V to 5.5 V, or any combination. All inputs are 5-V tolerant when supplied from a 3-V supply. ORDERING INFORMATION (1) PACKAGE (2) TA –40°C to 125°C (1) (2) SOIC – D Reel of 2500 ORDERABLE PART NUMBER TOP-SIDE MARKING ISO7420QDRQ1 PREVIEW ISO7421AQDRQ1 7421AQ For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated ISO7420-Q1 ISO7421A-Q1 SLLSE14A – MARCH 2012 – REVISED JUNE 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PIN FUNCTIONS PIN NAME NO. I/O ISO7420 ISO7421A INA 2 7 INB 3 GND1 4 GND2 DESCRIPTION I Input, channel A 3 I Input, channel B 4 – Ground connection for VCC1 5 5 – Ground connection for VCC2 OUTA 7 2 O Output, channel A OUTB 6 6 O Output, channel B VCC1 2 1 – Power supply, VCC1 VCC2 8 8 – Power supply, VCC2 Table 1. FUNCTION TABLE (1) INPUT SIDE VCC OUTPUT SIDE VCC PU PU PD (1) PU INPUT IN OUTPUT OUT H H L L Open H X H PU = Powered up (VCC ≥ 3 V), PD = Powered down (VCC ≤ 2.4 V), X = Irrelevant, H = High level, L = Low level ABSOLUTE MAXIMUM RATINGS (1) VCC Supply voltage (2), VCC1, VCC2 –0.5 V to 6 V VI Voltage at IN, OUT –0.5 V to 6 V IO Output current ±15 mA Human-body model (HBM) AEC-Q100 Classification Level H3A ESD Electrostatic discharge Charged-device model (CDM) AEC-Q100 Classification Level C5 4 kV All pins 1.5 kV Machine model (MM) 200 V TJ(Max) Maximum junction temperature (1) (2) 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values except differential I/O bus voltages are with respect to network ground terminal and are peak voltage values. RECOMMENDED OPERATING CONDITIONS MIN TYP MAX 3 5.5 UNIT VCC1, VCC2 Supply voltage IOH High-level output current IOL Low-level output current VIH High-level input voltage 2 VCC VIL Low-level input voltage 0 0.8 V TA Operating temperature –40 125 °C 2 Submit Documentation Feedback –4 V mA 4 mA V Copyright © 2012, Texas Instruments Incorporated ISO7420-Q1 ISO7421A-Q1 www.ti.com SLLSE14A – MARCH 2012 – REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS VCC1 = VCC2 = 5 V ±10%, TA = –40°C to 125°C PARAMETER VOH High-level output voltage VOL Low-level output voltage TEST CONDITIONS MIN TYP IOH = –4 mA, see Figure 1 VCC – 0.8 4.6 IOH = –20 μA, see Figure 1 VCC – 0.1 5 MAX V IOL = 4 mA, see Figure 1 0.2 0.4 IOL = 20 μA, see Figure 1 0 0.1 VI(HYS) Input threshold voltage hysteresis 400 IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, see Figure 3 V mV 10 IN from 0 V or VCC UNIT μA μA –10 25 1.2 pF 50 kV/μs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420x ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V 0.4 0.8 AC Input: CL = 15 pF 3.4 5 0.6 1 10 Mbps ICC2 4.5 6 1 1.5 6.2 8 1.7 2.5 9 12 DC Input: VI = VCC or 0 V 2.3 3.6 AC Input: CL = 15 pF 2.3 3.6 2.9 4.5 2.9 4.5 4.3 6 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 mA ISO7421x ICC1 DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 4.3 6 6 9.1 6 9.1 TYP MAX mA SWITCHING CHARACTERISTICS VCC1 = VCC2 = 5 V ±10%, TA = –40°C to 125°C PARAMETER tPLH, tPHL Propagation delay time PWD (1) Pulse duration distortion |tPHL – tPLH| tsk(pp) TEST CONDITIONS MIN 9 14 ns 0.3 3.7 ns Part-to-part skew time 4.9 ns tsk(o) Channel-to-channel output skew time 3.6 ns tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss tui Input pulse duration 7 1 / tui Signaling rate 0 (1) See Figure 1 UNIT See Figure 1 1 See Figure 2 ns 1 ns 6 μs ns 50 Mbps Also known as pulse skew Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 3 ISO7420-Q1 ISO7421A-Q1 SLLSE14A – MARCH 2012 – REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 = 5 V ±10%, VCC2 = 3.3 V ±10%, TA = –40°C to 125°C PARAMETER VOH High-level output voltage VOL Low-level output voltage TEST CONDITIONS MIN IOH = –4 mA, see Figure 1, 5-V side VCC – 0.8 IOH = –20 μA, see Figure 1 VCC – 0.1 TYP MAX V IOL = 4 mA, see Figure 1 0.4 IOL = 20 μA, see Figure 1 0.1 VI(HYS) Input threshold voltage hysteresis UNIT V 400 IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, see Figure 3 mV μA 10 IN from 0 V or VCC μA –10 25 1.2 pF 40 kV/μs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420x ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V 0.4 0.8 AC Input: CL = 15 pF 2.6 3.7 0.6 1 3.3 4.3 1 1.5 4.4 5.6 1.7 2.5 6.2 7.5 DC Input: VI = VCC or 0 V 2.3 3.6 AC Input: CL = 15 pF 1.8 2.8 2.9 4.5 2.2 3.2 4.3 6 2.8 4.1 6 9.1 3.8 5.8 TYP MAX 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 mA ISO7421x ICC1 DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 mA SWITCHING CHARACTERISTICS VCC1 = 5 V ±10%, VCC2 = 3.3 V ±10%, TA = –40°C to 125°C PARAMETER TEST CONDITIONS MIN tPLH, tPHL Propagation delay time PWD (1) Pulse duration distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss tui Input pulse duration 7 1 / tui Signaling rate 0 (1) 4 See Figure 1 See Figure 1 10 17 ns 0.5 5.6 ns 6.3 ns 4 ns 2 See Figure 2 UNIT ns 2 ns 6 μs ns 50 Mbps Also known as pulse skew Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated ISO7420-Q1 ISO7421A-Q1 www.ti.com SLLSE14A – MARCH 2012 – REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS VCC1 = 3.3 V ±10%, VCC2 = 5 V ±10%, TA = –40°C to 125°C PARAMETER VOH High-level output voltage VOL Low-level output voltage TEST CONDITIONS MIN IOH = –4 mA, see Figure 1, 3.3-V side VCC – 0.4 IOH = –20 μA, see Figure 1 VCC – 0.1 TYP MAX V IOL = 4 mA, see Figure 1 0.4 IOL = 20 μA, see Figure 1 0 VI(HYS) Input threshold voltage hysteresis 0.1 400 IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, see Figure 3 μA μA –10 25 V mV 10 IN from 0 V or VCC UNIT 1 pF 40 kV/μs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420x ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V 0.2 AC Input: CL = 15 pF 3.4 5 0.4 0.6 10 Mbps ICC2 4.5 6 0.6 0.9 6.2 8 1 1.3 9 12 DC Input: VI = VCC or 0 V 1.8 2.8 AC Input: CL = 15 pF 2.3 3.6 2.2 3.2 2.9 4.5 2.8 4.1 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 0.4 mA ISO7421x ICC1 DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 mA 4.3 6 3.8 5.8 6 9.1 TYP MAX 10 17 ns 0.5 4 ns 8.5 ns 4 ns SWITCHING CHARACTERISTICS VCC1 = 3.3 V ±10%, VCC2 = 5 V ±10%, TA = –40°C to 125°C PARAMETER TEST CONDITIONS MIN tPLH, tPHL Propagation delay time PWD (1) Pulse duration distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time tsk(o) Channel-to-channel output skew time tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss tui Input pulse duration 7 1 / tui Signaling rate 0 (1) See Figure 1 See Figure 1 2 See Figure 2 UNIT ns 2 ns 6 μs ns 50 Mbps Also known as pulse skew Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 5 ISO7420-Q1 ISO7421A-Q1 SLLSE14A – MARCH 2012 – REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS VCC1 = VCC2 = 3.3 V ±5%, TA = –40°C to 125°C PARAMETER VOH High-level output voltage VOL Low-level output voltage TEST CONDITIONS MIN TYP IOH = –4 mA, see Figure 1 VCC – 0.4 3 IOH = –20 μA, see Figure 1 VCC – 0.1 3.3 MAX V IOL = 4 mA, see Figure 1 0.2 0.4 IOL = 20 μA, see Figure 1 0 0.1 VI(HYS) Input threshold voltage hysteresis 400 IIH High-level input current IIL Low-level input current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) CMTI Common-mode transient immunity VI = VCC or 0 V, see Figure 3. μA μA –10 25 V mV 10 IN from 0 V or VCC UNIT 1 pF 40 kV/μs SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic ICC measurement) ISO7420x ICC1 DC to 1 Mbps ICC2 ICC1 DC Input: VI = VCC or 0 V 0.2 0.4 AC Input: CL = 15 pF 2.6 3.7 0.4 0.6 3.3 4.3 0.6 0.9 4.4 5.6 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 1 1.3 6.2 7.5 DC Input: VI = VCC or 0 V 1.8 2.8 AC Input: CL = 15 pF 1.8 2.8 2.2 3.2 2.2 3.2 2.8 4.1 2.8 4.1 3.8 5.8 3.8 5.8 TYP MAX 12 20 ns 1 5 ns 50 Mbps ICC2 mA ISO7421x ICC1 DC to 1 Mbps ICC2 ICC1 10 Mbps ICC2 Supply current for VCC1 and VCC2 ICC1 25 Mbps ICC2 ICC1 CL = 15 pF 50 Mbps ICC2 mA SWITCHING CHARACTERISTICS VCC1 = VCC2 = 3.3 V ± 5%, TA = –40°C to 125°C PARAMETER TEST CONDITIONS MIN tPLH, tPHL Propagation delay time PWD (1) Pulse duration distortion |tPHL – tPLH| tsk(pp) Part-to-part skew time 6.8 ns tsk(o) Channel-to-channel output skew time 5.5 ns tr Output signal rise time tf Output signal fall time tfs Fail-safe output delay time from input power loss tui Input pulse duration 7 1 / tui Signaling rate 0 (1) 6 See Figure 1 UNIT 2 See Figure 1 See Figure 2 ns 2 ns 6 μs ns 50 Mbps Also known as pulse skew Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated ISO7420-Q1 ISO7421A-Q1 www.ti.com SLLSE14A – MARCH 2012 – REVISED JUNE 2012 Isolation Barrier PARAMETER MEASUREMENT INFORMATION IN Input Generator (1) 50 W VI VCC1 VI OUT 1.4 V 1.4 V 0V VO CL tPLH (2) tPHL 90% 10% VCC/2 VO VCC/2 VOH VOL tr tf S0412-01 (1) The input pulse is supplied by a generator having the following characteristics: PRR ≤ 50 kHz, 50% duty cycle, tr ≤ 3 ns, tf ≤ 3 ns, ZO = 50 Ω. (2) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 1. Switching Characteristic Test Circuit and Voltage Waveforms VI VCC1 VCC1 Isolation Barrier 0 V IN or VCC1 VI 2.7 V 0V OUT tfs VO VOH CL 50% VO (1) Fail-Safe HIGH VOL S0413-01 (1) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 2. Fail-Safe Output Delay-Time Test Circuit and Voltage Waveforms S1 IN C = 0.1 mF ±1% Isolation Barrier VCC1 GND1 VCC2 C = 0.1 mF ±1% Pass-fail criteria – output must remain stable. OUT + VOH or VOL GND2 (1) – + VCM – S0414-01 (1) CL = 15 pF and includes instrumentation and fixture capacitance within ±20%. Figure 3. Common-Mode Transient Immunity Test Circuit Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 7 ISO7420-Q1 ISO7421A-Q1 SLLSE14A – MARCH 2012 – REVISED JUNE 2012 www.ti.com DEVICE INFORMATION PACKAGE CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT L(I01) Minimum air gap (clearance) Shortest terminal-to-terminal distance through air 4.8 mm L(I02) Minimum external tracking (creepage) Shortest terminal-to-terminal distance across the package surface 4.3 mm CTI Tracking resistance (comparative tracking index) DIN IEC 60112 / VDE 0303 Part 1 >175 V Minimum internal gap (internal clearance) Distance through the insulation 0.008 mm RIO Isolation resistance CIO Barrier capacitance, input to output Input to output, VIO = 500 V, all pins on each side of the barrier tied together creating a two-terminal device, TA < 100°C >1012 Input to output >1011 Ω 1 pF VI = 0.4 sin (4E6πt) Ω NOTE Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications. INSULATION CHARACTERISTICS (1) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIORM Maximum working insulation voltage VPR Input-to-output test voltage VIOTM Transient overvoltage VISO Isolation voltage per UL RS Insulation resistance t = 1 s (100% production), partial discharge 5 pC t = 60 s (qualification) t = 1 s (100% production) UNIT 560 V 1050 V 4000 V t = 60 s (qualification) 2500 t = 1 s (100% production) 3000 VIO = 500 V at TS >109 Pollution degree (1) SPECIFICATION Vrms Ω 2 Climatic Classification 40/125/21 Table 2. IEC 60664-1 RATINGS TABLE PARAMETER Basic isolation group Installation classification 8 Submit Documentation Feedback TEST CONDITIONS SPECIFICATION Material group III-a Rated mains voltage ≤ 150 Vrms I–IV Rated mains voltage ≤ 300 Vrms I–III Rated mains voltage ≤ 400 Vrms I–II Copyright © 2012, Texas Instruments Incorporated ISO7420-Q1 ISO7421A-Q1 www.ti.com SLLSE14A – MARCH 2012 – REVISED JUNE 2012 REGULATORY INFORMATION VDE CSA UL Certified according to IEC 60747-52 Approved under CSA Component Acceptance Notice Recognized under 1577 Component Recognition Program (1) File number: pending (40016131) File number: pending (1698195) File number: pending (E181974) (1) Production tested ≥ 3000 Vrms for 1 second in accordance with UL 1577. LIFE EXPECTANCY vs WORKING VOLTAGE Life Expectancy – Years 100 VIORM at 560 V 28 Years 10 0 120 250 500 750 880 1000 VIORM – Working Voltage – V G001 Figure 4. Life Expectancy vs Working Voltage IEC SAFETY LIMITING VALUES Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures. PARAMETER IS Safety input, output, or supply current TS Maximum case temperature TEST CONDITIONS MIN TYP MAX θJA = 212°C/W, VI = 5.5 V, TJ = 170°C, TA = 25°C 112 θJA = 212°C/W, VI = 3.6 V, TJ = 170°C, TA = 25°C 171 150 UNIT mA °C The safety-limiting constraint is the absolute-maximum junction temperature specified in the Absolute Maximum Ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Characteristics table is that of a device installed in the JESD51-3, Low-Effective-Thermal-Conductivity Test Board for Leaded Surface-Mount Packages and is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 9 ISO7420-Q1 ISO7421A-Q1 SLLSE14A – MARCH 2012 – REVISED JUNE 2012 www.ti.com PACKAGE THERMAL CHARACTERISTICS (over recommended operating conditions unless otherwise noted) PARAMETER TEST CONDITIONS Junction-to-air thermal resistance θJB Junction-to-board thermal resistance θJC Junction-to-case thermal resistance PD (1) 212 122 VCC1 = VCC2 = 5.5 V, TJ = 150°C, CL = 15 pF, Input a 150-Mbps 50% duty-cycle square wave Device power dissipation TYP High-K thermal resistance (1) Low-K thermal resistance θJA MIN (1) MAX UNIT °C/W 37 °C/W 69.1 °C/W 390 mW Tested in accordance with the low-K or high-K thermal metric definitions of EIA/JESD51-3 for leaded surface mount packages 200 Safety Limiting Current − mA 180 VCC1, VCC2 at 3.6 V 160 140 VCC1, VCC2 at 5.5 V 120 100 80 60 40 20 0 0 50 100 150 TC − Case Temperature − °C 200 G002 Figure 5. θJC Thermal Derating Curve per IEC 60747-5-2 VCC1 0.1mF OUTPUT INPUT GND1 VCC2 2 mm 2 mm max. max. ISO7421A from from VCC1 VCC2 8 1 OUTA INA 7 2 INB OUTB 6 3 5 4 0.1mF INPUT OUTPUT GND2 S0417-01 Figure 6. Typical ISO7421A Application Circuit 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated ISO7420-Q1 ISO7421A-Q1 www.ti.com SLLSE14A – MARCH 2012 – REVISED JUNE 2012 Input VCC1 VCC1 VCC1 Output VCC2 1 MW 500 W 8W IN OUT 13 W S0422-01 Figure 7. Device I/O Schematics Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 11 ISO7420-Q1 ISO7421A-Q1 SLLSE14A – MARCH 2012 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SIGNAL RATE (ALL CHANNELS) PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 14 CL = 15 pF TA = 25°C 18 16 tpd − Propagation Delay Time − ns ICC1, ICC2 − Supply Current − mA 20 14 VCC1, VCC2 at 5 V 12 10 8 6 VCC1, VCC2 at 3.3 V 4 2 0 0 20 40 60 80 2 −35 −15 5 25 45 65 85 105 125 G004 Figure 9. INPUT VOLTAGE SWITCHING THRESHOLD vs FREE-AIR TEMPERATURE FAIL-SAFE VOLTAGE THRESHOLD vs FREE-AIR TEMPERATURE 2.62 VIT+, 5 V Fail-Safe Voltage Threshold − V Input Voltage Switching Threshold − V 4 G003 VIT+, 3.3 V 1.3 1.2 1.1 VIT−, 5 V 1.0 VIT−, 3.3 V 0.9 −35 −15 5 25 45 65 85 TA − Free-Air Temperature − °C Figure 10. 12 VCC1, VCC2 at 5 V 6 Figure 8. 1.4 0.8 −55 8 TA − Free-Air Temperature − °C 1.6 1.5 VCC1, VCC2 at 3.3 V 10 0 −55 100 120 140 160 180 200 Signal Rate − Mbps 12 Submit Documentation Feedback 105 125 G005 2.61 FS+ 2.60 2.59 2.58 2.57 2.56 2.55 FS− 2.54 2.53 2.52 −55 −35 −15 5 25 45 65 85 TA − Free-Air Temperature − °C 105 125 G006 Figure 11. Copyright © 2012, Texas Instruments Incorporated ISO7420-Q1 ISO7421A-Q1 www.ti.com SLLSE14A – MARCH 2012 – REVISED JUNE 2012 TYPICAL CHARACTERISTICS (continued) HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 80 IOL − Low-Level Output Current − mA IOH − High-Level Output Current − mA 0 TA = 25°C −10 −20 −30 −40 VCC1, VCC2 at 3.3 V −50 −60 −70 VCC1, VCC2 at 5 V −80 −90 TA = 25°C 70 60 VCC1, VCC2 at 5 V 50 40 VCC1, VCC2 at 3.3 V 30 20 10 0 0 1 2 3 4 VOH − High-Level Output Voltage − V 5 6 G007 0 1 2 3 4 5 VOL − Low-Level Output Voltage − V 6 G008 Figure 12. Figure 13. Figure 14. Eye Diagram at 250 MBPS, 5-V VCC, Typical Figure 15. Eye Diagram at 200 MBPS, 5-V VCC, 125°C Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 13 ISO7420-Q1 ISO7421A-Q1 SLLSE14A – MARCH 2012 – REVISED JUNE 2012 www.ti.com REVISION HISTORY Changes from Original (March, 2012) to Revision A Page • Changed High Signaling Rate from 1 to 50 Mbps. ............................................................................................................... 1 • Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, 8.5 max value changed to 9.1. ..................................................................................................................................................................... 3 • Changed Signaling rate max value from 1 to 50. ................................................................................................................. 3 • Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, 8.5 max value changed to 9.1 and 5.5 changed to 5.8. ............................................................................................................................... 4 • Changed Signaling rate from 1 to 50 Mbps. ......................................................................................................................... 4 • Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, 5.5 max value changed to 5.8 and 8.5 changed to 9.1. ............................................................................................................................... 5 • Changed Signaling rate from 1 to 50 Mbps. ......................................................................................................................... 5 • Replaced Supply Current section with marked up table from commercial datasheet SLLSE45, 5.5 max value changed to 5.8. ..................................................................................................................................................................... 6 • Changed Signaling rate from 1 to 50 Mbps. ......................................................................................................................... 6 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 15-May-2012 PACKAGING INFORMATION Orderable Device ISO7421AQDRQ1 Status (1) ACTIVE Package Type Package Drawing SOIC D Pins Package Qty 8 2500 Eco Plan (2) Green (RoHS & no Sb/Br) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CU NIPDAU Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device ISO7421AQDRQ1 Package Package Pins Type Drawing SOIC D 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.4 B0 (mm) K0 (mm) P1 (mm) 5.2 2.1 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO7421AQDRQ1 SOIC D 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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