SP5054 2.6GHz 3-Wire BUS Controlled Synthesiser DS3048 - 3.4 May 1996 The SP5054 is a single-chip frequency synthesiser designed for satellite TV tuning systems. It is a programming variant of the SP5055, allowing the design of one tuner with either I2C bus or 3-wire bus format, depending on which device is inserted. The SP5054, when used with a satellite varactor tuner, forms a complete phase locked loop tuning system. The circuit consists of a divide-by-16 prescaler with its own preamplifier and a 14/15-bit programmable divider controlled by a serially-loaded data register. Four independently programmable open-collector outputs are included. The device has four modes of operation, selected by the Mode Select input; these modes are summarised in Table1. The comparison frequencies are obtained by the division of the output of a 4MHz crystal controlled on-chip oscillator. The phase comparator has a charge pump output with an output amplifier stage around which feedback may be applied. Only one external transistor is required for varactor line driving. FEATURES ■ Complete 2·6GHz Single Chip System ■ 62·5kHz, 100kHz and 125kHz Step Size ■ Low Power Consumption (325mW Typ.) ■ Programming Compatible with Toshiba TD6380, TD6381 and TD6382 * ■ Pin Compatible with SP5055 * ■ Low Radiation ■ Varactor Drive Amplifier Disable ■ Charge Pump Disable ■ Single Port 18/19 Bit Serial Data Entry ■ Four Controllable Outputs ■ ESD Protection † * See notes on pin compatibility † Normal ESD handling precautions should be observed APPLICATIONS ■ Satellite TV ■ High IF Cable Tuning Systems Fig. 1 Pin connections – top view ORDERING INFORMATION SP5054 KG DPAS (18-lead plastic package) SP5054S KG MPAS (16-lead miniature plastic package) SP5054 ELECTRICAL CHARACTERISTICS TAMB = 220°C to 180°C, VCC = 14·5V to 15·5V. Frequency standard = 4MHz. All pin connections refer to DP package. These Characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Value Characteristic Pin Units Min. Supply current Prescaler input voltage Prescaler input voltage 14 15,16 Prescaler input impedance Input capacitance 15,16 High level input voltage Low level input voltage High level input current Low level input current Low level input current High level input current Low level input current 4,5,10 4,5,10 4,5,10 5 4,10 3 3 Clock inout hysteresis Clock rate Data set up time, t2 Data hold time, t3 Enable set up time, t1 Enable hold time, t5 Clock-to-enable time, t4 5 5 4 4 10 10 10 Charge pump output current Charge pump output leakage current Drift due to leakage Charge pump drive output current Charge pump amplifier gain 1 1 18 Typ. Max. 65 80 400 400 50 100 VCC 0·7 1 5 2250 700 2700 0·4 0·5 300 600 300 600 300 6150 Ports and Lock Output Sink current Port leakage current Varactor drive amplifier disable Charge pump disable V MHz ns ns ns ns ns µA nA mV/s mA 2 2 ppm/°C ppm/V 6400 10 2 2 200 40 2400 6-9,11 6-9 10 10 4 2350 2350 10 NOTE 1. The maximum resistance quoted refers to all conditions, including start-up. 2 V V µA µA µA µA µA 65 5 1 Oscillator temperature stability Oscillator stability with supply voltage Recommended crystal series resistance Crystal oscillator drive level Crystal oscillator source impedance mA VCC = 5V mVrms 500MHz to 2·6GHz sinewave mVrms 120MHz and 500MHz, see Fig. 6 Ω pF 50 2 3 0 Conditions VIN = 5·5V, VCC = 5·5V VIN = 0V, VCC = 5·5V VIN = 0V, VCC = 5·5V VIN = 5·5V, VCC = 5·5V VIN = 0V, VCC = 5·5V See Fig. 4 See Fig. 4 See Fig. 4 See Fig. 4 See Fig. 4 V pin 1 = 2·0V V pin 1 = 2·0V At collector of external transistor V pin 18 = 0·7V I pin 18 = 100µA Ω Parallel resonant crystal (note 1) mV p-p Ω Nominal spread = 615% mA µA VOUT = 0·7V VOUT = 13·2V µA µA VIN < 0V VIN < 0V SP5054 ABSOLUTE MAXIMUM RATINGS All voltages are referred to VEE = 0V Value Pin Parameter Units SP5054 SP5054S Min. Max. 14 12 20·3 7 V 15,16 13,14 2·5 V p-p 6-9 6-9 6-9 6-9 20·3 20·3 14 6 V V Prescaler DC offset 15,16 13-14 20·3 VCC10·3 V Loop amplifier DC offset 1,18 1,16 20·3 VCC10·3 V 2 2 20·3 VCC10·3 V 4,5,10 4,5,10 20·3 VCC10·3 V 255 1150 °C 1150 °C DP18 thermal resistance, chip-to-ambient DP18 thermal resistance, chip-to-case 78 24 °C/W °C/W MP16 thermal resistance, chip-to-ambient MP16 thermal resistance, chip-to-case 111 41 °C/W °C/W Power consumption at 5·5V 484 mW Supply voltage RF input voltage Port voltage Crystal oscillator DC offset Data bus inputs Storage temperature Junction temperature Conditions Port in off state Port in on state With VCC applied Fig. 2 Typical input impedance 3 SP5054 Fig. 3 Block diagram of SP5054 Mode Mode Select input voltage Programmable divider bit length Reference divider ratio Frequency step size (kHz) * Maximum operating frequency (GHz) 3 0·925VCC to VCC 14 512 125 2·0479 2 0·675VCC to 0·825VCC 15 512 125 2·5 1 Open circuit 15 1024 62·5 2·0479 0 0V to 0·325 VCC 15 640 100 2·5 * Table 1 SP5054 modes of operation. * Frequencies stated apply when using a 4MHz crystal. FUNCTIONAL DESCRIPTION The SP5054 contains all the elements necessary, with the exception of reference crystal, loop filter and external high voltage transistor, to control a voltage controlled local oscillator, so forming a PLL frequency synthesised source. The system is controlled by a microprocessor via a standard Data, Clock and Enable three-wire data bus. The data load normally consists of a single word, which contains the frequency and port information, and is only transferred to the internal data shift register during an enable high period. The clock input is disabled during enable low periods. New data words are only accepted by the internal data buffers from the shift register on a negative transition of the Enable, so giving improved fine tune facility for digital AFC etc. The data sequence and timing follows the format shown in Fig. 4. The frequency is set by loading the programmable divider with the required 14/15 bit divisor word. The output of this divider, FPD, is fed to the phase comparator where it is compared in phase and frequency domain to the internally generated comparison frequency, FCOMP. FCOMP is obtained by dividing the output of an on-chip crystal controlled oscillator. The crystal frequency used is generally 4MHz, which gives an FCOMP of 3·90625/6·25/ 4 7·8125kHz and, when multiplied back up to the synthesised LO, gives a minimum step size of 62·5/100/125kHz, respectively. The programmable divider is preceded by an input RF preamplifier and high speed, low radiation prescaler. The preamplifier is arranged to be self oscillating, so giving excellent input sensitivity. The SP5054 contains an improved lock detect circuit which generates a flag when the loop has attained lock. ‘In lock’ is indicated by high impedance state. The SP5054 contains 4 general purpose open collector outputs, ports P1-P4, which are capable of sinking at least 10mA. These outputs are set by the remaining four bits within the normal data word. NOTES ON PIN COMPATIBILITY The SP5054 may be used in SP5055 applications which require 3-wire bus as opposed to I2 C bus data format. In SP5055 applications where the reference crystal is grounded to pin 3, a small modification is required to ground the crystal as shown in Fig. 5. Appropriate connections must also be made to the Mode Select input (see Table 1). In Mode 3, The SP5054 is programming compatible with the Toshiba TD6380, in Modes 0 and 2 with the TD6381 and in Mode 1 with the TD6382. SP5054 Fig. 4 Data format and timing 5 SP5054 Fig. 5 Typical application (fSTEP = 125kHz) Fig. 6 Typical input sensitivity 6 SP5054 Fig. 7 SP5054 input/output interface circuits 7 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. 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