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For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ Preliminary Information SP5848 SP5848 2.2/1.3GHz 3-Wire Bus Dual Low Phase Noise PLL Preliminary Information DS5076 ISSUE 1.6 Features • • • • • • • • Dual independent PLL frequency synthesisers in a single package, optimised for double conversion cable tuners, offering improved application 2.2GHz up-synthesiser optimised for low phase noise up to comparison frequencies of 4MHz 1.3GHz down-synthesiser optimised for low phase noise AND small step size Common reference oscillator and divider with independently selectable ratios for each synthesiser 10:1 programmable charge pump current ratio in up synthesiser 3-Wire bus programmable, each synthesiser indepently addressable Low power consumption, typ 100mW at 5V ESD protection, (Normal ESD handling procedures should be observed) Ordering Information SP5848/KG/QP1S SP5848/KG/QP1T Description The SP5848 is a dual PLL frequency synthesizer controlled by a 3-wire bus optimised for application in double conversion tuners. Each synthesiser loop within the SP5848 is independently addressable and contains an RF programmable divider, phase/frequency detector and charge pump/loop amplifier section; a common reference frequency oscillator and divider chain is provided, whose ratios for each loop are independently programmable. Both synthesisers are optimised for low phase noise performance and in addition synthesiser 2 is capable of operation with a low comparison frequency. Applications • October 1999 TV, VCR, and cable tuning systems PUMP 1 11 BIT COUNT RF1 INPUT DRIVE 1 16/17 4 BIT COUNT PORT P0 15 BIT LATCH 2 BIT LATCH 2 BIT LATCH PORT P1 DATA CLOCK DATA INTERFACE 5 BIT LATCH ENABLE 16 BIT LATCH 29 DIVIDE 1 BIT LATCH PUMP 2 12 BIT COUNT RF 2 INPUT 16/17 DRIVE 2 4 BIT COUNT Figure 1 - Block Diagram 1 SP5848 Preliminary Information PORT P1 PORT P0 CHARGE PUMP 2 CHARGE PUMP 1 DRIVE 2 DRIVE 1 Vee 2 Vee 1 RF2 INPUT RF1 INPUT RF2 INPUT RF1 INPUT Vcc2 Vcc1 CRYSTAL ENABLE CRYSTAL CAP DATA Vee CLOCK QP20 Figure 2 - Pin Connections Electrical Characteristics o o Tamb= -40 C to +80 C, Vcc = 4.5 to 5.5 V, These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Pin Value Typ Max 18 5.5 22 V mA 40 300 mVrms 240 32767 Min Supply voltage Supply current Synthesiser 1 (UP) RF1 input voltage RF1 input impedance RF1 division ratio Reference division 1 ratio Comparison frequency 1 Equivalent phase noise at phase detector 1 Charge pump 1 output current Charge pump 1 output leakage Charge pump 1 drive output current 2 7, 14 15,16 15,16 4.5 Units Conditions 80 -2200MHz See Figure 4 See Table 1 4 -148 MHz dBc/Hz nA SSB, within loop bandwidth, all comparison frequencies See Table 3 Vpin 19=2V Vpin19 = 2V mA Vpin 18 = 0.7V 19 ±3 19 18 0.5 ±10 Preliminary Information SP5848 Electrical Characteristics (continued) o o Tamb= -40 C to +80 C, Vcc = 4.5 to 5.5 V, These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Pin Min Synthesiser 2 (DOWN) RF2 input voltage RF2 input impedance RF2 division ratio Reference division 2 ratio Comparison frequency 2 5,6 5,6 Outputs ports P0 - P1 sink current leakage current Units Conditions Max 30 300 240 65535 mVrms 80 -1300MHz See Figure 5 See Table 2 16.25 Equivalent phase noise at phase detector 2 Charge pump 2 output current Charge pump 2 output leakage Charge pump 2 drive output curent Data, clock and enable Input high voltage Input low voltage Input current hysterysis Clock rate Bus timing Data set up Data hold Enable setup Enable hold Clock to enable Reference Oscillator Crystal frequency External reference input frequency External reference drive Value Typ 4000 -144 KHz nA Phase noise degrades above 250KHz SSB, within loop bandwidth, all comparison frequencie up to 250KHz See Table 4 Vpin 2=2V Vpin2 = 2V mA Vpin 3 = 0.7V V V µA Vpp KHz All input conditions dBc/Hz 2 ±3 2 3 ±10 0.5 12,11,13 3 0 -10 Vcc 0.7 10 0.8 11 500 300 600 300 600 300 ns ns ns ns ns 8, 9 8 2 2 16 20 MHz MHz 8 0.2 0.5 Vpp 10 mA µA 1, 20 2 See Figure 6 for application Sinewave coupled through 10nF blocking capacitor Sinewave coupled through 10nF blocking capacitor See note 1 Vport = 0.7V Vport = Vcc Note 1 Output ports high impedance on power up, with data, clock and enable at logic 0 3 SP5848 Preliminary Information Absolute maximum Ratings All voltages referred to Vee at 0V Characteristic Supply voltages RF1 input voltage RF2 input voltage All I/O ports DC offset Storage temperature Junction temperature Package thermal resistance chip to ambient chip to case Power consumption with all Vcc =5.5V ESD protection Min -0.3 -0.3 -55 Value Max 7 2.5 2.5 Vcc+0.3 +125 150 Units V Vp-p Vp-p V °C °C 100 30 121 °C/W °C/W mW 2 Conditions kV Differential Differential All ports off Mil std 883 latest revision methood 3015 class 1 Functional Description Programming Mode The SP5848 contains two PLL frequency synthesiser loops, each independently programmable from a 3-wire bus. The device is optimised for application in double conversion tuners where synthesiser 1 would form part of the upconverter and synthesiser 2 part of the down converter. Both loops are optimised for application in low phase noise loops and furtherly synthesiser 2 offers low comparison frequencies. A block diagram is contained in Figure 1. The SP5848 is designed to be programmed from a standard 3-wire bus consisting of clock, data and enable, where the serial clock and data lines can be shared with other devices and the enable line is a unique line for individual device selection. To simplify programming each synthesiser is independently addressed, with the required loop being selected by the LSB bit , which functions as the address, therefore to fully program the device two complete data transmissions must be sent. The device is programmed via a 3-wire bus where data is fed on serial data and clock lines and is gated by an enable line. Figure 3 indicates the format of the data. The sequence and timing of data load is described below in ‘programming mode’ description. Each synthesiser is independently addressable and is defined by the LSB bit within the data transmission. The data format for each transmission is contained in Figure 3. A common reference frequency source and reference divider is used to derive the comparison frequency for both PLL loops. The reference division ratio is programmable via the data bus as defined in Tables1 and 2. The charge pump current for each loop is also programmable via the data bus as defined in Tables 3 and 4 Two switching ports are provided to control switching functions within the tuner. These ports also access test signals within the PLL as defined in Figure 7. Ports power up in high impedance state. 4 Test modes as described in Figure 7, can be invoked by setting bit T0 in synthesiser 2 data word to a ‘1’ and sending control data for bits T1-T2. In normal operation where T0 is set to a ‘0’ bits T1 and T2 do not need to be transmitted Preliminary Information SP5848 CLOCK ENABLE DATA 222 221 220 219 218 217 216 215 21 20 P1 P0 CU1 CU0 RU2 RU1 RU0 MSB LSB ‘0’ Frequency data (15 bits) Synthesiser 1 control data CLOCK ENABLE DATA 224 223 T2 T1 222 T0 220 219 218 217 CD RD2 RD1 RD0 216 21 20 MSB LSB ‘1’ Frequency data (16 bits) Synthesiser 2 control data CU0 - CU1 RU0 - RU2 CD RD0 - RD2 T0 - T2 P0 - P1 : : : : : : Synthesiser 1 charge pump Synthesiser 1 reference division ration Synthesiser 2 charge pump Synthesiser 2 reference division ratio Test modes Switching ports P0 - P1 Figure 3 - Control data 5 SP5848 Preliminary Information j1 j0.5 j2 j0.2 j5 0.2 0 0.5 1 2 5 80MHz 1GHz 1·7GHz 2·2GHz 2j0.2 2j5 2j2 2j0.5 2j1 Figure 4 - Synthesiser 1 RF input impedance j1 j0.5 j2 j0.2 j5 0.2 0 0.5 1 2 5 80MHz 0·5GHz 0·9GHz 2j5 1·3GHz 2j0.2 2j2 2j0.5 2j1 Figure 5 - Synthesiser 2 RF input impedance 6 Preliminary Information RU2 RU1 RU0 Ratio 0 0 0 2 0 0 1 4 0 1 0 8 0 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 256 SP5848 Table 1 - Synthesiser 1 reference division ratio RU2 RU1 RU0 Ratio 0 0 0 4 0 0 1 8 0 1 0 16 0 1 1 32 1 0 0 64 1 0 1 128 1 1 0 256 1 1 1 512 Table 2 - Synthesiser 2 reference division ratio CU1 CU0 Current (typical in mA) 0 0 0.12 0 1 0.26 1 0 0.55 1 1 1.2 Table 3 - Synthesiser 1 charge pump current 7 SP5848 Preliminary Information CD Current (typical in mA) 0 0.05 1 0.2 Table 4 - Synthesiser 2 charge pump current Figure 6 - Crystal oscillator application T2 T1 T0 Functional Description X X 0 Normal operation 0 0 1 Both charge pumps in sink mode 0 1 1 Both charge pumps in source mode 1 0 1 Port P1 = Fcomp1, P0 = Fcomp2 and charge pumps disabled 1 1 1 Port P1 = (Fpd1)/2, P0 = (Fpd2)/2 X = dont care 8 Figure 7 - Test modes For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable. 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