Preliminary SPCA751A-P101 Description The SPCA751A is a single chip signal processor optimized for MPEG audio decoding and voice recording. It is developed to achieve a better performance/cost ratio for MPEG audio players. The SPCA751A is especially designed for standalone audio players, the system controller can easily carry out the MPEG audio decoding process by the use of a general serial IO/control interface for MPEG bit stream in/out and playback control. Decoded audio PCM data are output to external DAC through a programmable normal/I2S DAC interface, such that most of common audio DACs can be cooperated with SPCA751A to meet different customers' requirements. A high quality 10-bit 8KHz sampling rate ADC is embedded for voice recording. Based on the algorithm of SACM_S480 or SACM_S3200, voice is compressed to a low data rates of 4.8Kbps and 32Kbps respectively, while retaining a good resolution of the original speech/audio. The SPCA751A is designed for 3.3V applications, A built in PLL is able to synthesize the system clock from a 16.934MHz crystal oscillator source. The high performance SPCA751A signal processor can operate at 34MHz and dissipate low power, which makes the SPCA751A extremely suitable for portable systems. A common implementation utilizing the SPCA751A is presented below: LCD Key Scan PC parallel or USB port FM / AM Tuner Normal / I 2S SPCA751A DRAM ATAPI (CDROM/HD) Audio DAC (8KHz 10bit) System uP (SPCP751A) FLASH/Plug-in Cards 3.3V DSA / I 2C DC-DC Converter CDdsp interface CD Kit MPEG Audio Player System Block Diagram 1 Microphone AA battery x 1 Speaker Preliminary SPCA751A-P101 Features • Single chip MPEG audio decoder • Low power dissipation - Conforming to MPEG1/MPEG2 audio layer 2/3 - Extension to MPEG lower sampling rates • PLL embedded - Require only 16.934MHz crystal, resistors, and capacitors to supply the system clock • Digital sound control - Digital volume control - Stereo/Mono channel select - Digital sound equalizer • Built-in Digital Recording option - Embedded 10-bit 8 kHz audio ADC - SACM_S480 recording with 4.8 kbit/sec - SACM_S3200 recording with 32 kbit/sec • Internal auto-generate audio clock - Sampling frequency from 8 kHz up to 48 kHz • Device Parameter - Supply voltage : 3.0 ~ 3.6 volts - IO interface : 5 volts tolerance, TTL compatible - Package : 44-pin LQFP - Power consumption: less than 150 mW @ 3.6 volts • Programmable audio DAC interface - Support both normal and I2S audio DAC formats - Audio clock polarity programmable - Internal auto-generated oversampling clock for DAC Accept external audio clock for sampling rate control • Serial data IO and control interface - Easy for the host processor to command SPCA751A BLOCK DIAGRAM AIP AIN ATO VM OSCOUT OSCIN ADC MPEG Audio Decoder PLL Voice Encoder/Decoder Clock Synthesizer Host Interface PCM Buffer AUD_LRCK AUD_BCK AUD_DATA AUD_XCK TFS RFS SCLK DR DT FCEB1 FCEB2 2 Preliminary SPCA751A-P101 Function Description The SPCA751A is a single-chip CMOS microprocessor optimized for real-time MPEG audio decoding and speech/audio recording. SPCA751A decodes the encoded MPEG audio data according to the commands passed through the Serial Control/Data I/O Interface by the host processor, the host processor can also check the status of decoding process by the use of this interface. Refer to Programming Guide for command definitions In the digital recorder mode, speech/Audio is sampled at 8Khz by the on-chip ADC into 10-bit digital words, after encoding, the datum is compressed into a data rate of 4.8Kbps or 32Kbps. Decoded audio PCM data are output to external DAC through a programmable normal/I2S PCM interface, this interface is compliant to most of the common audio DACs. The embedded PLL is capable of providing the 27 MHz system clock derived from a 16.934MHz clock source ! Serial Control/Data I/O Interface The host controller uses this interface to transfer MPEG bit-stream with the SPCA751A and to command the SPCA751A during the recording/decoding process. This interface consists of seven pins: FCEB1 FCEB2 Host Controller SCLK RFS1 SPCA 751A TFS1 DR1 DT1 " Pin # 12 FCEB2 Frame Decoded Indicator generated by the SPCA751A Pin # 13 FCEB1 Data Request Flag generated by the SPCA751A Pin # 44 SCLK1 Bit Clock controlled by the host processor Pin # 1 DT1 Data from the SPCA751A to the host processor Pin # 2 TFS1 Transmit Frame Synchronization controlled by the host processor Pin # 3 DR1 Data from the host processor to the SPCA751A Pin # 4 RFS1 Receive Frame Synchronization controlled by the host processor FCEB1 - Data Request Flag The FCEB1 flag generated by the SPCA751A informs the status of the decoding/encoding process. When FCEB1 is high, it indicates that the SPCA751A is ready to receive data/command or to transfer data, the host processor is allowed to start the communication; When FCEB1 is low, the SPCA751A is busy processing internally and no I/O tasks could be taken, the commands sent by the host processor during low FCEB1 are not accepted by the SPCA751A and may cause the SPCA751A run into an unknown state. 3 Preliminary " SPCA751A-P101 FCEB2 - Frame Decoded Indicator Each time the SPCA751A has decoded one frame (512 bytes) of data, it changes the state of FCEB2 (either high to low or low to high) and progresses to the next frame. By counting the number of state-changes, the host processor is able to know the time elapsed in decoding. " Host Command The host commands consist of 8-bit command and 8-bit ID, totally 16-bit long. (Refer to the SPCA751A Programming Guide for command definitions) At the falling edges of SCLK1, the SPCA751A checks whether the RFS1 is high. Once it is high, the 16-bit long command is sampled at the following 16 consecutive falling edges of SCLK1 with MSB first. After the LSB is sent, the host processor should send at least one more cycle of SCLK1 to the SPCA751A. SCLK1 TSCLK RFS1 TFS TDS TDH TFH DR1 " b15 b14 b1 b0 Host processor writes 512 bytes to the SPCA751A At the falling edges of SCLK1, the SPCA751A checks whether the RFS1 is high. Once it is high, the 512-byte long data is sampled at the following 512x8 consecutive falling edges of SCLK1. RFS1 should remain high before the MSB of the last word. After the LSB of the last word is sent, the host processor should send at least three more cycles of SCLK1 to the SPCA751A. SCLK1 TSCLK RFS1 TDS TFS TFH TDH DR1 b15 b14 b0 255 words b0 b15 Last word Timing Requirements PARAMETER TFS TFH TDS TDH TSCLK MIN. MAX. UNIT RFS1 setup before SCLK1 falls low 2 ns RFS1 hold after SCLK1 falls low 2 ns DR1 setup before SCLK1 falls low 3 ns DR1 hold after SCLK1 falls low 3 ns SCLK1 period 16 * ns * The maximum period of SCLK1 depends on the sampling rate of the decoded data, too long a SCLK1 period makes the real-time decoding impossible. 4 Preliminary " SPCA751A-P101 Host processor reads 512 bytes from the SPCA751A To read data from the SPCA751A, the host processor first asserts the TFS1 at the falling edges of SCLK1, then the 512-byte long data is sampled out from the SPCA751A at the following 512x8 consecutive rising edges of SCLK1. The host processor is supposed to latch-in the data at the falling edges of SCLK1. TFS1 should remain high before the MSB of the last word. After the LSB of the last word is received, the host processor should send at least three more cycles of SCLK1 to the SPCA751A. SCLK1 TSCLK RFS1 TFS TFH TDH TD DR1 b15 b14 b0 255 words b0 b15 Last word Timing Requirements PARAMETER TFS TFH TSCLK MIN. MAX. UNIT TFS1 setup before SCLK1 falls low 2 ns TFS1 hold after SCLK1 falls low 2 ns SCLK1 period 16 ns Switching Characteristics PARAMETER TD TDH ! MIN. DT1 access MAX. 5 TSCLK / 2 DT1 hold after SCLK1 falls low UNIT ns ns PLL An independent analog power is applied through pin 41 VSSP and pin 42 VDDP to supply the power for the internal PLL. An oscillation circuit is built externally on pin 39 OSCIN and pin 40 OSCOUT. 10 M Ohm pin 40 OSCOUT pin 39 OSCIN 16.934MHz Crystal 12 pF 12 pF Oscillation Circuit 5 Preliminary ! SPCA751A-P101 PCM Interface The PCM Interface is used to output decoded audio data to external audio DAC. There are 4 signals, AUD_XCK, AUD_LRCK, AUD_BCK and AUD_DATA. The signal format of PCM Interface is programmable with register 0x3fDE. Register Name Register # Bits Description AUD_CONFIG 0x3FDE 14 (Value set at initialization) (0x2103) Audio out configuration (RW) bit 0 = I2S control bit 1 = AUD_XCK select bit 2 = AUD_DATA LSB / MSB sent first bit 3 = AUD_BCK active edge bit 4 = AUD_XCK IO select bit 5 = LRCK polarity bit 12 = CD-DA pass through mode (0 = I2S, 1 = normal) (0 = 256×Fs, 1 = 384×FS) (0 = MSB first, 1 = LSB first) (0 = falling, 1 = rising) (0 = output, 1 = input) (0 = LRCK low is right, 1 = LRCK low is left) (0 = disable, 1 = enable) Normal Mode: AUD_BCK AUD_LRCK AUD_DATA 0 15 14 1 0 15 14 1 0 15 14 BCK = 32 x Fs AUD_BCK AUD_LRCK AUD_DATA 0 15 14 1 0 15 14 1 0 15 BCK = 48 x Fs I2S Mode: AUD_BCK AUD_LRCK AUD_DATA 1 0 15 14 1 0 15 14 1 0 15 BCK = 32 x Fs AUD_BCK AUD_LRCK AUD_DATA 0 1514 0 1514 BCK = 48 x Fs PCM Interface waveform 6 0 1514 Preliminary ! SPCA751A-P101 ADC The SPCA751A has an audio-band sigma-delta analog-to-digital converter so as to meet the requirement of the digital recorder application. The circuit of converter consists of two main blocks: the analogto-digital converter (ADC) and internal reference and bias voltage. For the latter, it is 15-bit format with 10-bit resolution. The analog-to-digital conversion chain consists of a microphone amplifier (M.A.), a programmable gain amplifier (PGA), an analog oversampled modulator, and the decimation digital filter. The PGA has gain step from –12dB to 12dB (-12, -6, 0, 6, 12dB). The modulator is a sigma-delta feedback loop, which oversamples the signal at 1.024MHz and provides second-order noise shaping. It performs the conversion of the differential analog input signal to a pulse-density-modulated single-bit digital output. When a maximum positive differential input voltage is applied at the input of modulator, the resulting code at the output of the modulator is all ones. The decimation digital filter consists of a comb filter and a half-band filter. The comb filter is a third-order comb filter. Finally the encoder implements the half-band filter and data compression by software. ADC & DAC ELECTRICAL CHARACTERISTICS (TA = 25ºC, VDD = 3.3 V) PARAMETER ATO: CONDITION MIN. TYP. MAX. UNIT 0.25*VDD Vpp 12 dB MA gain = 0dB, Input Voltage PGA: PGA gain = 6dB Default: 6dB Gain Range -12 Step Size Step Variation 6 dB 0.5 dB Voltage Reference: Output Voltage 0.45VDD 0.5VDD 0.55VDD Vpp MIN. TYP. MAX. UNIT ADC PATH CHARACTERISTICS PARAMETER ADC: CONDITION FIN = 1kHz, Signal to noise ratio PGA gain = 12dB ATO is full swing Without data compression 7 60 dB Preliminary SPCA751A-P101 DIGITAL RECODER APPLICATION CIRCUIT A/D converter Analog reference voltage generator P.G.A. (-12,-6,0, 6,12dB) Microphone Amplifier ATO 390pF MICVCC AVDD1 AIN AIP 10 F Ω Ω AVSS1 Ω Controller IO port Ω VM Ω 10 F 0.1 F Ω 47 F MICGND 8 0.1 F M Microphone Ω 0.1 F Preliminary SPCA751A-P101 Pin Description PIN No. Mnemonic Type Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 DT1 TFS1 DR1 RFS1 RESET CLKSEL VDD VSS VDDO VSSO N.C. FCEB2 FCEB1 VDD VSS N.C. VDDO VSSO VDD VSS N.C. N.C. VDDO VSSO AUD_XCK AUD_DATA AUD_BCK AUD_LRCK VDD VSS VDDA VSSA AIP AIN ATO VM VDDO VSSO OSCIN OSCOUT VSSP VDDP CLKIN O I/O I I/O I I I I I I I I I/O O O O I I I I I I O O I I I O I I I 44 SCLK1 I/O O O I I I I I I Transmit Data of Serial Port Transmit Frame Synchronization of Serial Port Receive Data of Serial Port Receive Frame Synchronization of Serial Port System Reset (Active Low) System Clock Select (0: Internal PLL 1:External Oscillator) Digital Power Digital Ground Digital Power Digital Ground No Connection Frame Decoded Indicator Data Request Flag Digital Power Digital Ground No Connection Digital Power Digital Ground Digital Power Digital Ground No Connection No Connection Digital Power Digital Ground Oversampling Clock to external Audio DAC / from external source Serial Data Output to Stereo Audio DAC Bit Clock Output to Stereo Audio DAC Sample Rate Clock Output to Stereo Audio DAC Digital Power Digital Ground Analog Power for Audio ADC Analog Ground for Audio ADC Positive Input of the Audio ADC transmit input amplifier Negative Input of the Audio ADC transmit input amplifier Output of the Audio ADC transmit input amplifier 1/2 AVDD for the bias of the Audio ADC transmit input amplifier Digital Power Digital Ground 16.934MHz Oscillator Input 16.934MHz Oscillator Output Analog Ground for PLL Analog Power for PLL External System Clock (Connect to VSS if internal PLL is used (pin 82 CLKSEL == 0)) Bit Clock of Serial Port 9 Preliminary SPCA751A-P101 23 24 25 26 27 28 29 30 31 34 22 35 21 36 20 37 19 SPCA751A 38 39 18 17 LQFP 44 40 16 11 10 9 8 12 7 44 6 13 5 43 4 14 3 42 2 15 1 41 DT1 TFS1 DR1 RFS1 RESETB CLKSEL VDD VSS VDDO VSSO NC AIN ATO VM VDDO VSSO OSCIN OSCOUT VSSP VDDP CLKIN SCLK1 32 33 AIP VSSA VDDA VSS VDD AUD_LRCK AUD_BCK AUD_DATA AUD_XCK VSSO VDDO PIN Map 10 NC NC VSS VDD VSSO VDDO NC VSS VDD FCEB1 FCEB2 VDD 5K 0.1F Host Processor 12 pF RESET LQFP 44 12 pF 390pF 100K 0.1F 10F M Microphone 47F 0.1F 10F 2.2K 1K 0.1F 2.2K 2.2K 100K 20K DAC Application Circuit AUD_LRCK AUD_BCK AUD_DATA AUD_XCK AVDD AVSS VM ATO AIN AIP 10M 16.934MHz Crystal 10K CLKIN SPCA751A OSCOUT OSCIN SPCA751A 11 RFS1 DR1 TFS1 DT1 SCLK1 FCEB2 FCEB1 SPCA751A-P101 Preliminary Preliminary SPCA751A-P101 ABSOLUTE MAXIMUM RATINGS Rating Symbol Value Unit Supply Voltage VDD 0.0 ~ Input Voltage VIN - 0.3 ~ Operating Temperature TA 0 ~ 60 ºC -55 ~ 125 ºC Storage Temperature TSTG 3.6 V VDD + 0.3 V DC ELECTRICAL CHARACTERISTICS (TA = 25ºC, VDD = 3.3 V) PARAMETER CONDITION VDD Supply Voltage VIL Input Low Voltage VIH Input High Voltage VOH Output High Voltage IOH = -4mA VOL Output Low Voltage IOL = 4mA IDD Power Supply Current MIN. 3.0V TYP. 3.3V MAX. 3.6V 0.2VDD 0.8VDD 2.4V 30.0mA VDD 0.3V 0.6V 35.0mA 40.0mA Ordering Information " Package type : 44 pin LQFP Note: SUNPLUS TECHNOLOGY CO. LTD reserves the right to make changes at any time without notice in order to improve the design and performance to supply the best possible product 12 Preliminary SPCA751A-P101 Outline Dimensions D D1 D2 E E1 E2 e b c A2 L1 A1 A Symbol Min. Nom. Max. D D1 D2 E E1 E2 e b A A1 A2 c L1 0.22 0.05 1.35 0.09 - 12 10 8 12 10 8 0.80 0.30 1.40 1.0 0.38 1.60 0.15 1.45 0.20 - Unit : millimeter 13