S PMC802B SP 3 2-pin General Purpose 32 Microcontroller (OTP) AUG. 07, 2002 Version 1.0 SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus. SPMC802B Table of Contents PAGE 1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3 2. FEATURES.................................................................................................................................................................................................. 3 3. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 3.1. CPU ..................................................................................................................................................................................................... 4 3.2. MEMORY ............................................................................................................................................................................................... 4 3.3. OSCILLATOR .......................................................................................................................................................................................... 4 4. SIGNAL DESCRIPTIONS ........................................................................................................................................................................... 5 4.1. PIN DESCRIPTIONS (32 PIN) ................................................................................................................................................................. 5 4.2. PIN ASSIGNMENT .................................................................................................................................................................................. 5 5. FUNCTIONAL DESCRPITIONS.................................................................................................................................................................. 7 5.1. PORT A GROUP ..................................................................................................................................................................................... 7 5.2. PORT B GROUP ..................................................................................................................................................................................... 7 5.3. PORT C GROUP ..................................................................................................................................................................................... 8 5.4. PORT D GROUP ..................................................................................................................................................................................... 9 5.5. INTERRUPT ............................................................................................................................................................................................ 9 5.6. TIMER1 & REAL TIME INTERRUPT ......................................................................................................................................................... 10 5.7. TIMER2 & PWM .................................................................................................................................................................................. 10 5.8. COMPARATOR ...................................................................................................................................................................................... 10 5.9. WAIT & STOP MODE .......................................................................................................................................................................... 10 5.10. RESET ...............................................................................................................................................................................................11 5.11. RESET MANAGEMENT REGISTERS ......................................................................................................................................................11 6. ELECTRICAL CHARACTERISTICS......................................................................................................................................................... 12 6.1. ITEM DEFINITION .................................................................................................................................................................................. 12 6.2. ABSOLUTE MAXIMUM RATING ............................................................................................................................................................... 12 6.3. RECOMMENDED OPERATING CONDITIONS ............................................................................................................................................. 12 6.4. PIN ATTRIBUTE DESCRIPTION (VDD = 5.0V, TA = 0ºC~70ºC)............................................................................................................... 12 7. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 14 7.1. PACKAGE INFORMATION ....................................................................................................................................................................... 14 7.2. ORDERING INFORMATION ..................................................................................................................................................................... 25 8. DISCLAIMER............................................................................................................................................................................................. 26 9. REVISION HISTORY ................................................................................................................................................................................. 27 © Sunplus Technology Co., Ltd. Proprietary & Confidential 2 AUG. 07, 2002 Version: 1.0 SPMC802B 32-PIN GENERAL PURPOSE MICROCONTROLLER (OTP) 1. GENERAL DESCRIPTION The SPMC802B is an OTP version of SPMC02A with reliability enhancement. ! Three external interrupt groups, one is come from individual I/O It equips with an 8-bit Sunplus CPU core, 4.5K bytes of program ROM, and 128 bytes of RAM. Channel PB5 and group input PA3:0, one is come from SPMC802B also individual I/O Channel, PA7, and one is a group input, PC port. combines with four I/O ports, two timers with one PWM output, two ! External Reset input option on PB4. Comparator inputs, and a Watchdog Timer. ! An 8-bit Timer with Real Time Interrupt control. Three groups of interrupt are implemented for different kinds of applications. ! An 8-bit Re-loadable Timer with 8 stages prescalar. Major application fields are small home appliances or computer ! One 6-bit PWM waveform output. peripheral applications. ! Two voltage Comparator inputs with selectable internal or The details are described below. external voltage reference. An interrupt event control for the compare result. 2. FEATURES ! A watchdog timer for program control. ! Built-in 8-bit Sunplus CPU core with two index registers and up ! 4.5K bytes of ROM with 128 bytes of RAM. ! R-Oscillation or Crystal input options for system clock. to 6MHz clock operation. ! Stop or Wait Control setting for Power-Saving Mode. ! 28 general-purpose I/O channels that are belong to four I/O ports. ! Slow Transition Output Pins. Some of them are combined with the options to select Pull-Up/Down Resistors. 3. BLOCK DIAGRAM XO/R XI OSC. CKT 4.5K bytes PROM $600~$FFF & $1800~$1FFF 128 bytes RAM $80 ~ $FF VDD 8 - bit CPU VSS PA3-0 PA7 PC7-0 RESET(PB4) IRQ(PB5) PA6 PB3-1 PD3-0 © Sunplus Technology Co., Ltd. Proprietary & Confidential I/O PORT & External Interrupt I/O PORT & External RESET Pin I/O PORT & External IRQ Pin I/O PORT ADDRESS BUS DATA BUS TIMER 1 & RTI & Watch_Dog timer Interrupt Generator & RESET generator TIMER 2 & 6 bits PWM waveform generator /13 /1 /1 /1 /1 /8 /3 3 I/O PORT & External CLOCK Pin PB6 I/O PORT & PWM waveform output PB7 I/O PORT & 2 set Comparator circuit PA4,PA5 PB0 AUG. 07, 2002 Version: 1.0 SPMC802B 3.1. CPU 3.2. Memory The microprocessor of SPMC802B is a SUNPLUS high 3.2.1. Memory map performance processor equipped with Accumulator, Program SPMC802B Supports 4.5K bytes of EPROM with 512 bytes test Counter, X Register, Y Register, Stack Pointer and Processor ROM. Status Register (The same as 6502 instruction‘s structure). by writer for different applications. SPMC802B is a fully static CMOS design. test ROM, and options are located in $0400h ~ $0FFFh and The oscillation It also has the configurable options can be programmed frequency could be varied up to 6.0MHz depends on the $1800h ~ $1FFFh. application needs. $00FFh. The addresses for EPROM, The RAM area is located in $0080h ~ The functional control registers and I/O control registers are located in $0000h ~ $0013h. 3.1.1. Block diagram of Sunplus CPU REGISTER SECTION registers can be configured through indexed access addresses $003Eh and $003Fh. CONTROL SECTION RESET IRQ NMI the RAM area $00FFh ~ $0080h. INDEX REGISTER Y ABL A3 A4 A5 named Stack Limit Register (SLR) is used to limit the Stack area to PD prevent the override of the normal operating contents in the RAM. STACK POINT REGISTER S A6 This area is mirrored to A system control register RDY A1 A2 The buffers for stack pointer are started from $01FFh with downward direction. INTERRUPT LOGIC INDEX REGISTER X A0 A set of system control Once the Stack is over the limiter, CPU reset will be generated. A7 INSTRUCTION DECODE ALU ADDRESS BUS To prevent the illegal accesses on undefined addresses, there is a ACCUMULATOR A qualification block to limit the accesses. TIMING CONTROL PCL A8 generate the CPU reset to restart the program. PCH A9 PROCESSOR STATUS REGISTER P A10 A12 INPUT DATA LATCH IDLI ABH A11 A13 CLOCK GENERATOR CLK 0 IN 3.2.2. NMI, Reset, IRQ vectors R/W A14 A15 DATA BUS BUFFER INSTRUCTION REGISTER The address of NMI (not provided in this chip), RESET and IRQ D0 D1 D2 D3 D4 D5 D6 D7 LEGEND = 8BIT LINE The illegal accesses will = 1 BIT LINE are located from $1FFA to $1FFF. DATA BUS The interrupt vectors should be specified in the program to have proper operation. 3.3. Oscillator The SPMC802B supports AT-cut parallel resonant oscillated vendors‘ specifications or recommendations. Crystal /Resonator, or RC oscillator, or external clock sources by below configurable option (select one from those three types). applications: design of application circuit should follow SPMC802B XI The typical X’TAL/ROSC circuits for most the SPMC802B XO/R represents The diagram listed XI XO/R SPMC802B XI XO/R VDD 20 pf 20 pf (a) Crystal or Ceramic Resonator Connections © Sunplus Technology Co., Ltd. Proprietary & Confidential UNCONNECTED Rosc External Clock (b) RC Oscillator Connections 4 (c) External Clock Source Connections AUG. 07, 2002 Version: 1.0 SPMC802B 4. SIGNAL DESCRIPTIONS 4.1. PIN Descriptions (32 PIN) Mnemonic PIN No. Functional Description VDD 28 System Power Supply. VSS 27 System Ground. XO/R 4 Crystal In or Resistor In Input. An external resistive pull-up is used to connect with internal OSC circuitry for generating the internal clock and the related time base in R-Oscillation mode. It will be connected with external crystal for a crystal oscillation circuitry in crystal mode. XI 5 Crystal Output or External Clock Input. External clock input is used to connect with internal clock circuitry to generate the internal clock and the related time base in External clock mode. It will be connected with external crystal for a crystal oscillation circuitry in crystal mode. PA7:0 9, 10, 11, 12 General-purpose inputs/outputs. GPIO Port A7:0. 20, 21, 22, 23 addition, PA7 can be used as the external interrupt input. Comparator. 24 PB5 Using the internal setting can configure it. GPIO Port B5. (Vpp) In PA5:4 can be the compare inputs of PA3:0 can be the group input of external interrupt. General-purpose input/output. Using the internal setting can configure it. addition, PB5 can be used as the external Main IRQ input. In It is used as Programming Voltage input in Programming mode. PB1 29 GPIO Port B1. (SCK) General-purpose input/output. Using the internal setting can configure it. In addition, it is used as Serial Clock input in Programming mode. PB0 13 GPIO Port B0. (SDA) General-purpose input/output or the voltage reference input for the Comparator. Using the internal setting can configure it. In addition, it is used as Serial Data input/output in Programming mode. PB7:6,4:2 19, 14, 6, GPIO Port B7:6,4:2. 3, 30 for Timer 2. PC7:0 32, 1, 17, 16 Using the internal setting can configure it. 8, 7, 26, 25 In PB6 can be set as external event/clock input PB4 can be used as the Main nRESET input. GPIO Port C7:0. 31, 2, 18, 15 PD3:0 General-purpose inputs/output. addition, PB7 can be the PWM waveform output. General-purpose inputs/outputs. Using the internal setting can configure it. In addition, these pins can be used as the external interrupt inputs. GPIO Port D3:0. General-purpose inputs/outputs. Using the internal setting can configure it. 4.2. PIN Assignment 5 16 PC1 15 PC5 17 PB7 PB6 12 PC4 14 18 PA3 PC0 13 19 PA2 PB0 11 20 PA1 PA4 10 1 2 3 4 5 6 7 8 9 PC2 PB3 XO/R XI PB4 PA7 PA6 PA5 9 PA7 PC6 8 PD3 PC4 16 7 PD2 PC0 15 6 XI PB4 PB6 14 5 XO/R PB0 13 4 PA4 12 3 PB3 PA5 11 2 PC2 PA6 10 1 PC6 Proprietary & Confidential 21 PA0 SPMC802B SPMC802B © Sunplus Technology Co., Ltd. 22 PB5 23 VSS 24 VDD 25 PB1 26 PB2 28 PC7 17 PC5 18 PC1 19 PB7 20 PA3 21 PA2 22 PA1 23 PA0 24 PB5 25 PD0 26 PD1 27 VSS 28 VDD 29 PB1 30 PB2 31 PC3 32 PC7 27 PC3 4.2.2. 28 PIN package 4.2.1. 32 PIN package AUG. 07, 2002 Version: 1.0 © Sunplus Technology Co., Ltd. Proprietary & Confidential 2 3 4 5 6 7 8 9 XO/R XI PB4 PA7 PA6 PA5 PA4 PB0 SPMC802B 6 10 PA2 9 3 4 5 6 7 8 PB4 PA7 PA6 PA5 PA4 PB0 PA3 11 PA1 12 PA0 3 4 5 6 7 8 9 XO/R XI PB4 PA7 PA6 PA5 PA4 12 PA1 11 PA2 10 PA3 6 7 8 9 PA5 PA4 PB0 13 PA0 14 PB5 PA6 15 VSS 16 VDD 5 XI 17 PB1 PA7 3 XO/R 18 PB2 13 PC1 14 PB7 15 PA3 16 PA2 17 PA1 18 PA0 19 PB5 20 VSS 21 VDD 22 PB1 23 PB2 4 2 SPMC802B PB4 1 PB3 PC0 12 PB6 11 PB0 10 2 PB3 SPMC802B 13 PB5 14 VSS 15 VDD 2 SPMC802B XI 4.2.4. 20 PIN package 1 16 PB1 11 PB7 12 PA3 13 PA2 14 PA1 15 PA0 16 PB5 17 VSS 18 VDD 19 PB1 20 PB2 24 PC3 4.2.3. 24 PIN package XO/R PB6 10 1 PB3 1 PC2 SPMC802B 4.2.5. 18 PIN package 4.2.6. 16 PIN package AUG. 07, 2002 Version: 1.0 SPMC802B 5. FUNCTIONAL DESCRPITIONS SPMC802B is an OTP for SPMC02A emulating. blocks have two kinds of control input. configurable option. The functional I/O attribute. The first one is Setting the bit(s) to '1' will enforce the corresponding pad(s) to output mode. The other is programmable register. It is a write-only register. PA is used to store the data contents for output. Reading PA will Configurable options are used as permanent assignment. They get the stored data when corresponding bit of DPA is set as output are configured with the program code in the same time. Once mode, or will get the pad status if it is in input mode. the configurable options are written to SPMC802B, they are unchangeable as the program code. are described in detail later. The configurable options There is a built-in Pull-Up/Down resistor on each pad. Programmable registers are used to have pull-up resistors that is permanent in SPMC802B. PA5:4 can be configured with pull-up or pull-down resistors. These control the functional blocks by the program. The program can access the registers to achieve the desire functions. PA7:6 configurable pull-up/down resistors should be selected or enabled by configurable option first, and then can be controlled by users' There are two kinds of registers with different access methods. The first kind of registers uses direct access as normal. program through RPA. The second kind of registers uses indexed write access for specific The output mode on PA7:6 can be programmed as slow transition function. outputs. They are summarized as following. All of the function Programming the bit slowe in RPA to '1' will enforce the registers will be set to 0 (except rt1 and rt0 in TCS1), when a reset output high to low transition time to 250ns ± 20% with 500pf pad signal occurred. loading at 2.0MHz CPU frequency. The bits rt1 and rt0 will be set to 1 when a reset signal occurred. PA7 and PA3:0 are used as external interrupt inputs. 5.1. Port A Group details are described in section Interrupt. The I/O port A has 8 programmable I/Os that are controlled by voltage compare inputs for Comparator function. data register PA, direction control register DPA, and pull-up/down analog inputs to provide source voltage inputs. resistance control register RPA. are described in section Comparator. DPA is used to control the pad The more PA5:4 are used as They are The more details The corresponding pads are assigned for SPMC802B as following: (VDD = 5.0V) PIN Rp IN OUT Special Function 5K Up Always Schmitt-Trigger -/8mA IRQ1 interrupt input PA6 5K Up Always Schmitt-Trigger PA5 100K Up/Down@rpa5 8/8mA CMP1 compare input PA4 100K Up/Down@rpa4 8/8mA CMP0 compare input PA3 100K Up/Down@rpa3 8/8mA IRQ0 interrupt input PA2 100K Up/Down@rpa2 8/8mA IRQ0 interrupt input PA1 100K Up/Down@rpa1 8/8mA IRQ0 interrupt input PA0 100K Up/Down@rpa0 8/8mA IRQ0 interrupt input PA7 -/8mA 5.2. Port B Group The I/O port B has 8 programmable I/Os that are controlled by There is a built-in Pull-Up/Down resistor on each pad except PB5. data register PB, direction control register DPB, and pull-up/down PB7, PB6, PB3, and PB0 can be configured with pull-up or resistance control register RPB. pull-down resistors. I/O attribute. DPB is used to control the pad Setting the bit(s) to '1' will enforce the corresponding pad(s) to output mode. should be selected by configurable option first, and then can be It is a write-only register. PB is used to store the data contents for output. These configurable pull-up/down resistors controlled by users' program through RPB. Reading PB will the internal resistor. PB5 does not have For interrupt input on PB5, an external get the stored data when corresponding bit of DPB is set as output pull-up resistor is needed to maintain the interrupt function. mode, or will get the pad status if it is in input mode. PB2, and PB1 have pull-up resistors. PB4, They can be controlled by users' program through RPB. © Sunplus Technology Co., Ltd. Proprietary & Confidential 7 AUG. 07, 2002 Version: 1.0 SPMC802B In SPMC802B, the output mode on PB2 and PB1 can be an PB7 can be a PWM waveform output. open-drain pin with slow transition by program. To achieve the clock or event input for Timer2. PB5 is used as external interrupt slow transition function, programming the bit slowe in RPA to '1' input with falling-edge trigger. PB4 can be used as external will enforce the output high to low transition time to 250ns ± 20% active-low reset input by enabling the configurable option. with 50pf pad loading at 2.0MHz CPU frequency. can be reference voltage input for Comparator function. PB6 can be an external PB0 In case of using PB0 as external reference voltage input, the resistive pull-up/down should be disabled. The more details are described in related sections. The corresponding pads are assigned for SPMC802B as following: (VDD = 5.0V) PIN Rp IN OUT Special Function PB7 100K Up/Down@rpb7 8/8mA PWM waveform output PB6 100K Up/Down@rpb6 8/8mA External clock/event input PB5 No Pull-Up/Down Schmitt-Trigger -/8mA IRQ0 interrupt input PB4 100K Up@rpb4 Schmitt-Trigger 8/8mA External nRESET input PB3 100K Up/Down@rpb3 8/8mA PB2 100K Up@rpb2 -/20mA PB1 100K Up@rpb1 -/20mA PB0 100K Up/Down@rpb0 8/8mA Comparator Vref input 5.3. Port C Group The I/O port C has 8 programmable I/Os that are controlled by There is a built-in Pull-Up/Down resistor on each pad. data register PC, direction control register DPC, and pull-up/down pull-up/down resistors should be selected either pull-up or resistance control register RPC. pull-down by configurable option first, and then can be controlled I/O attribute. DPC is used to control the pad Setting the bit(s) to '1' will enforce the corresponding pad(s) to output mode. These by users' program through RPC. It is a write-only register. PC is used to store the data contents for output. Reading PC will PC7:0 are used as external interrupt inputs. get the stored data when corresponding bit of DPC is set as output The more details are described in section Interrupt. mode, or will get the pad status if it is in input mode. The corresponding pads are assigned for SPMC802B as following: (VDD = 5.0V) PIN Rp PC7 100K Up/Down@rpc7 8/8mA IRQ2 interrupt input PC6 100K Up/Down@rpc6 8/8mA IRQ2 interrupt input PC5 100K Up/Down@rpc5 8/8mA IRQ2 interrupt input PC4 100K Up/Down@rpc4 8/8mA IRQ2 interrupt input PC3 100K Up/Down@rpc3 8/8mA IRQ2 interrupt input PC2 100K Up/Down@rpc2 8/8mA IRQ2 interrupt input PC1 100K Up/Down@rpc1 8/8mA IRQ2 interrupt input PC0 100K Up/Down@rpc0 8/8mA IRQ2 interrupt input © Sunplus Technology Co., Ltd. Proprietary & Confidential IN OUT 8 Special Function AUG. 07, 2002 Version: 1.0 SPMC802B 5.4. Port D Group The I/O port D has 4 programmable I/Os that are controlled by get the stored data when corresponding bit of DPD is set as output data register PD, direction control register DPD, and pull-up/down mode, or will get the pad status if it is in input mode. resistance control register RPD. I/O attribute. DPD is used to control the pad Setting the bit(s) to '1' will enforce the corresponding pad(s) to output mode. There is a built-in Pull-Up resistor on each pad. It is a write-only register. PD is used to store the data contents for output. These pull-up resistors can be controlled by users' program through RPD. Reading PD will The corresponding pads are assigned for SPMC802B as following: (VDD = 5.0V) PIN Rp PD3 100K Up@rpd3 IN 8/8mA OUT Special Function PD2 100K Up@rpd2 8/8mA PD1 100K Up@rpd1 8/8mA PD0 100K Up@rpd0 8/8mA 5.5. Interrupt There are four kinds of interrupt, Software Interrupt, External event until the active level condition is removed. Interrupt, Timer Interrupt, and Comparator interrupt. support edge trigger mode only. Each of the IRQ1 and IRQ2 last three interrupts has individual status (occurred or not) and control (enable or not) registers, whereas Software Interrupt does The not. auto-clearing function. In general, once an corresponding flag bit will be set. interrupt event occurs, the external interrupt IRQ0 supports interrupt-flag-bit It is activated only when interrupt If the related interrupt control channels of IRQ1 is disabled. When the auto-clearing function is bit is set to enable interrupt, an interrupt request signal will be activated, the flag of IRQ0 will be cleared automatically as soon as generated and will be dealt with by CPU for service. The the interrupt vector is accessed. The user software in interrupt interrupt flag bits must be cleared in the interrupt service routine to service routine does no need to check the flag because that flag prevent program from deadlock in interrupt service routine. bit has been cleared by hardware. It is used to simplify the interrupt service routine only when the IRQ0 is the unique interrupt Software interrupt is generated by the instruction BRK. The BRK source of the system. If the Timer interrupts or Comparator is an executable instruction interrupt; it is executed regardless of interrupts are enabled with only IRQ0 being enabled as external the state of the I-bit in the Processor Status Register Flag (inside interrupt source, the external interrupt event due to IRQ0 might be CPU). lost in case two interrupt events occur in the same time. It jumps to interrupt routine when BRK occurred. As with To avoid any instruction, interrupts pending during the previous instruction the problem of IRQ0 loss, using IRQ1 or IRQ2 for external is served. interrupt channel, instead of using IRQ0, can solve it. However, no matter the auto-clearing function of interrupt flag is functional, External interrupts are coming from IRQ0, IRQ1, or IRQ2. These user software must clear the interrupt occurrence in the interrupt IRQ signals are combined with the configurable options and service routine. status/control registers to generate the interrupt events to CPU. For all IRQ channels, each channel has individual interrupt control There is a new configurable option, named irqac, to be added for or status bits. future supporting. Once an external interrupt is occurred, the flag will be set and stays at set unless user software clears the flag. This option can disable the auto-clearing The function of IRQ0 interrupt flag. interrupt request signal will be generated in case of the interrupt is body consistency will control it. enabled. The program tool to maintain the Channel IRQ0 has a configurable option used to set the trigger mode of the interrupt event. The trigger mode can be In SPMC802B, IRQ0 is come from either PB5 with falling-edge selected as either edge trigger mode or level trigger mode. trigger or group input PA3:0 with rising-edge trigger. When the interrupt channel is enabled with edge trigger mode, an configurable option is used to activate the group interrupt input on active transition edge on the external interrupt inputs will generate PA3:0. the interrupt. interrupt group input, PC7:0. If the channel is enabled with level trigger mode, IRQ1 is come from PA7. A IRQ2 is come from external the active level of the external interrupt inputs will set the interrupt © Sunplus Technology Co., Ltd. Proprietary & Confidential 9 AUG. 07, 2002 Version: 1.0 SPMC802B The Timer 1 interrupt and the Comparator interrupt will be The additional counting stages perform the Power On Reset (POR) described in detail in section Timer1 & Real Time Interrupt and cycle for clock settling down during power up, the Real Time section Comparator. Interrupt (RTI) function for timing applications, and watchdog Timer for function recovery. 5.6. Timer1 & Real Time Interrupt The POR and WDT functions are described in detail in section WDT & Reset. The clock input (XI/XO/R pins), fOSC, is internally divided by two to generate CPU clock, fCPU, for whole system. For Real Time Interrupt, there is a pre-scalar to perform the Timer 1 clock, fTM1, is come from CPU clock with the divisor either 1 or 4 setting by periodic timing events. configurable option. timing events will set the flag and will generate interrupt for service The timer clock is fed into an 8-bit free-run timer built as Timer 1 function. The if the interrupt is enabled. Timer 1 Count Register (TCR1) is used to read out the current counting value of Timer 1. The pre-scalar is defined below. Once TCR1 is overflow, it will set the corresponding flag and will generate interrupt for service if the interrupt input is enabled. RTI Rate rt1:0 Divisor fTM1=fCPU/1* 00 2048 01 4096 WDT Reset time (=RTI/8) fTM1=fCPU/4* Divisor fTM1=fCPU/1* fTM1=fCPU/4* 2.048ms 8.192ms 16384 16.384ms 66ms 4.096ms 16.384ms 32768 32.768ms 131ms 10 8192 8.192ms 32.768ms 65536 66ms 262ms 11 16384 16.384ms 65.536ms 131072 131ms 524ms Note1: In this example, the CPU clock is fCPU = 1.0MHz (fOSC = 2.0MHz). Note2: *The fTM1 is selected by configurable option fsel. 5.7. Timer2 & PWM 5.8. Comparator Timer 2 is a re-loadable 8-bit timer. It consists with an 8-bit SPMC802B is built with two channels of voltage Comparator. It prescale counter, a pre-load register, an 8-bit count-up counter, can compare the external voltage input coming from PA4 or PA5 and a control block. with the external voltage reference set up on PB0, or with the The base clock input for Timer 2 fTIN2 can be either from CPU clock fCPU, or from external clock through PB6. It internal voltage reference (1.24V). These two channels is fed into an 8-bit prescale counter to generate the Timer 2 clock, Comparator can be enabled with the setup of comparison criterion fTM2. and the reference source, and selectable interrupt input for event The prescalar for Timer 2 clock is set as 2 to the power of the value. An 8-bit counter with a Pre-load Register consist the main counter of Timer 2. service. Timer 2 Count Register (TCR2) is used The input operating range of the Comparator is 0.2V to (VDD-0.2)V. to set up the pre-load value in write mode and to read out the current counting value in read mode. Once the Timer 2 clock is enabled, main counter will count up. When Timer 2 rolls over 5.9. WAIT & STOP Mode There are two kinds of clock control mode supported by from $FF to pre-load data, it generates overflow signal and SPMC802B as WAIT mode and STOP mode. reloads the pre-load data into the counting stage and counts up again. The overflow signal will also generate interrupt for service The WAIT mode function will disable CPU clock but leave the if the interrupt function is enabled. timer clock active, if the bit wait is set as '1'. Once the system The PWM waveform generator consists with a 3-duty cycle PWM being entered the WAIT mode, the activated interrupt events will generator, a 64-duty cycle PWM generator, and a control block for recover the normal operation immediately from the next address of PWM waveform output to PB7. WAIT mode interrupt point. The general I/O function on PB7 will be disabled while the PWM output is enabled. To confirm the interrupt events can wake up the CPU, the corresponding interrupt enable bits must be There are two set before entering the WAIT mode. kinds of waveform output can be selected, fixed 3-duty cycle waveform output and programmable 64-duty cycle waveform output. The overflow signal of Timer 2, is the base clock of PWM generator. The STOP mode function will disable whole system clock, if the bit It will feed into the 3-duty cycle waveform generator stop is set as '1'. and the 64-duty cycle waveform generator. © Sunplus Technology Co., Ltd. Proprietary & Confidential Once the system being entered the STOP mode, only the activated external interrupt events (from I/Os) can 10 AUG. 07, 2002 Version: 1.0 SPMC802B recover the normal operation from the next address of STOP Stack Limit Register (SLR), System Guard Register (SGR), mode interrupt point with 1024 fTM1 clock cycle recovery time for System Control Register (SCR), and System Stop & Wait Register stable oscillation. (SNW). To confirm the external interrupt events can The read of these registers uses direct access. wake up the system, the corresponding interrupt enable bits must Reading the registers through page 0 addresses can get the be set before entering the STOP mode. contents directly. A specific write cycle, named indexed write cycle, is implemented to have higher reliability of content updates. There are two write paths. One is come from direct write mode The indexed addresses for these registers are same as the direct through address $0008, another is come from indexed write mode through indexed address $08. addresses used in read cycle. The purpose for the dual write paths is for backward compatibility. 5.11.1. Indexed write cycle The option incap is used to inhibit the STOP function coming from the direct write cycle of The procedure of indexed write cycle is formed with two SNW to improve the system reliability. consecutive write cycle of page 0. The indexed write for this register will be described in detail later. Only a write with address $003E, called write-index cycle, followed with a write with address $003F, called write-data cycle, can program the reset 5.10. Reset management registers. There are five kinds of reset resource for the system, Power On write cycles are allowed only for the code pre-fetches, means Reset (POR), External Reset (PB4), Low Voltage Reset (LVR), ROM area read cycles. Watchdog Timer Reset (WDT), and Illegal Address Reset (IAR). neither a ROM-read cycle nor a write-data cycle is executed after These reset sources can be concluded as external events and the write-index cycle, the indexed write cycle will be abnormal internal events. terminated without any data updates on these registers. The external events are come from the power line, or external trigger event. The intersections in between these two If a ROM-write cycle or an access cycle The internal events are come from the program exceptions or internal software reset event. To prevent abnormal termination of the indexed write cycle, programmers should handle the cycle much carefully. 5.11. Reset Management Registers The interrupts should be disabled to prevent unpredicted intersections. There are four registers implemented for reset event management, © Sunplus Technology Co., Ltd. Proprietary & Confidential 11 AUG. 07, 2002 Version: 1.0 SPMC802B 6. ELECTRICAL CHARACTERISTICS 6.1. Item Definition Symbol Definition Symbol Definition VIH Input High Voltage IOH Output High Current (Source) VIL Input Low Voltage IOL Output Low Current (Sink) VTH Input Threshold Voltage IZ Output Leakage Current (Source) SFV Frequency Stability RP Pull-Up/Down Resistance DFV Frequency Deviation 6.2. Absolute Maximum Rating Characteristics Symbol Min. Typ. Max. Unit Storage Temperature TSTR -40 - 125 ºC Operating Ambient Temperature TOPR 0 - 70 ºC Voltage Rating on Input VIN Voltage Rating on VDD Output Voltage -0.3 - VDD +0.3 V -0.3 - 7.0 V 0 - VDD V VOUT Condition Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions see AC/DC Electrical Characteristics. 6.3. Recommended Operating Conditions Symbol Min. Typ. Max. Unit Operating Supply Voltage Characteristics VDD 3.0 - 5.5 V Condition CPU Clock (Internal CPU clock) fCPU 200K - 6.0M Hz VDD = 5.0V Power Consumption IDD - 5.0 - mA fCPU = 6.0MHz @ VDD = 5.0V Power Down Current* IPD - - 10 µA VDD = 5.0V Power Up Initial Voltage VINIT - - 0.5 V Power On Reset Time tPOR 50 - - ms LVR Trigger Voltage VLVR - 2.2 - V VDD starts from VINIT Note: The power-down current is measured in SLEEP mode with all I/O pins in hi-impedance state and tied to VDD or VSS. 6.4. PIN Attribute Description (VDD = 5.0V, TA = 0ºC~70ºC) Mnemonic XI, XO PA7:6 Description Symbol Min. Typ. Max. Unit Condition Special Input Cell Pair for RC SFV - - ±5.0 % (f5.5V-f4.5V)/f5.0V * oscillation DFV - - ±10 % VDD = 5.0V RP - 27 - KΩ fCPU_5.0V = 6.0MHz Input with Schmitt Trigger VIH 2.0 - - V with Fixed Pull-Up R VIL - - 0.8 V 8mA Open-Drain Output IOL 8.0 - - mA VOL = 0.5V IP - 1.0 - mA VIN = VSS VIH 3.5 - - V PA5:0 Input with Pull-Up/Down PB7:6, 3, 0 option VIL - - 1.4 V PC7:0 8mA Output IOH 8.0 - - mA VOH = 2.4V IOL 8.0 - - mA VOL = 0.5V IP - 50 - µA VIN = VDD or VSS VIH 2.4 - - V PB5 Input with Schmitt Trigger © Sunplus Technology Co., Ltd. Proprietary & Confidential 12 AUG. 07, 2002 Version: 1.0 SPMC802B Mnemonic Description Symbol Min. Typ. Max. Unit VIL - - 0.8 V IOL 8.0 - - mA Input with Schmitt Trigger with VIH 2.0 - - V Pull-Up R VIL - - 0.8 V 8mA Output IOH 8.0 - - mA VOH = 2.4V 8mA Open-Drain Output PB4 PB2:1 PD3:0 VOL = 0.5V IOL 8.0 - - mA VOL = 0.5V RP 70 100 130 KΩ VIN = VSS = 0V Input with Pull-Up R VIH 3.5 - - V 20mA Open-Drain Output VIL - - 1.4 V IOL 20 - - mA VOL = 0.5V IP - 50 - µA VIN = VSS = 0V Input with Pull-Up R VIH 3.5 - - V 8mA Output VIL - - 1.4 V IOH 8.0 - - mA VOH = 2.4V IOL 8.0 - - mA VOL = 0.5V IP - 50 - µA VIN = VSS = 0V IZ - - 10 µA RP inactive VLVR 2.1 2.2 2.3 V Enable option All I/O Port Hi-Z Leakage LVR Threshold Voltage Compare Condition Operating Current ILVR - 20 - µA Input Hysteresis Voltage VHYS - 30 - mV Input Common Mode Voltage VICM 0.2 - VDD -0.2 V CMRR CMRR 50 - - dB tCV - - 400 ns tCON - - 10 µs ICMP - - 10 µA Response Time** Compare Mode Change to Output Valid*** Operating Current per Channel Note1: *The frequency defined in this item is based on the CPU frequency. It is one-half of the oscillation frequency. Note2: ** Response time measured with one comparator input at VDD/2, while the other input transitions from VSS to VDD. Note3: *** tCON measured with Compare mode enable to output valid, while the internal reference voltage is selected from disable to enable and same setup of comparator inputs as the item tCV. © Sunplus Technology Co., Ltd. Proprietary & Confidential 13 AUG. 07, 2002 Version: 1.0 SPMC802B 7. PACKAGE/PAD LOCATIONS 7.1. Package Information 7.1.1. PDIP 16 E1 D1 A2 c L1 e Body Size b Lead Size D1 E1 A2 L1 b 750 250 130 115 18 c e 10 100 All units are in mil. 1mil = 25.4µm © Sunplus Technology Co., Ltd. Proprietary & Confidential 14 D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-16-300 AUG. 07, 2002 Version: 1.0 SPMC802B 7.1.2. PDIP 18 E1 D1 A2 c L1 e b Body Size Lead Size D1 E1 A2 L1 b c e 900 250 130 115 18 10 100 All units are in mil. 1mil = 25.4µm © Sunplus Technology Co., Ltd. Proprietary & Confidential 15 D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-18-300 AUG. 07, 2002 Version: 1.0 SPMC802B 7.1.3. PDIP 20 E1 D1 A2 c L1 e Body Size Lead Size D1 E1 A2 L1 b c e 1020 250 130 115 18 10 100 All units are in mil. 1mil = 25.4µm © Sunplus Technology Co., Ltd. Proprietary & Confidential 16 b D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-20-300 AUG. 07, 2002 Version: 1.0 SPMC802B 7.1.4. PDIP 24 E1 D1 A2 c L1 e Body Size D1 E1 1245 250 A2 130 Lead Size L1 115 b 18 c 10 e 100 All units are in mil. 1mil = 25.4µm © Sunplus Technology Co., Ltd. Proprietary & Confidential 17 b D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-24-300 AUG. 07, 2002 Version: 1.0 SPMC802B 7.1.5. PDIP 28 (300mil) E1 D1 A2 c L1 e Body Size D1 1388 E1 290 Lead Size A2 130 L1 115 b 18 c 10 e 100 All units are in mil. 1mil = 25.4µm © Sunplus Technology Co., Ltd. Proprietary & Confidential 18 b D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-28-300 AUG. 07, 2002 Version: 1.0 SPMC802B 7.1.6. PDIP 28 (600mil) E1 D1 A2 c L1 e Body Size D1 1388 1450 E1 290 550 Lead Size A2 130 150 L1 115 100 b 18 c 10 e 100 All units are in mil. 1mil = 25.4µm © Sunplus Technology Co., Ltd. Proprietary & Confidential 19 b D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-28-300 PDIP-28-600 AUG. 07, 2002 Version: 1.0 SPMC802B 7.1.7. PDIP 32 (600mil) E1 A2 D1 c L1 e D1 1650 Body Size E1 550 A2 150 L1 100 Lead Size b c 18 10 e 100 All units are in mil. 1mil = 25.4µm © Sunplus Technology Co., Ltd. Proprietary & Confidential 20 b D1 E1 A2 L1 b c e Body Length Body Width Body Thickness Lead Length Lead Width Lead Thickness Lead Pitch PDIP-32-600 AUG. 07, 2002 Version: 1.0 SPMC802B 7.1.8. SOP 24 (300mil) E D X c y H 24 13 A2 A A1 pin 1 index L L1 θ detail X 1 12 e Symbol b Dimension in mm Dimension in inch Min. Typ. Max. Min. Typ. Max. A 2.362 2.515 2.642 0.093 0.099 0.104 A1 0.102 - 0.305 0.004 - 0.012 b - 0.406 - - 0.016 - c - 0.254 - - 0.010 - D 15.215 15.240 15.596 0.599 0.600 0.614 E 7.391 7.493 7.595 0.291 0.295 0.299 A2 e - 1.270 - - 0.050 - H 10.008 10.312 10.643 0.394 0.406 0.419 L1 0.406 0.889 1.270 0.016 0.035 0.050 y - - 0.102 - - 0.004 - 8 L θ © Sunplus Technology Co., Ltd. Proprietary & Confidential 0 0 - 8 21 0 0 0 0 AUG. 07, 2002 Version: 1.0 SPMC802B 7.1.9. SOP 28 (300mil) E D X c y H 28 15 A2 A A1 L pin 1 index L1 θ detail X 1 14 e b Symbol Dimension in mm Dimension in inch Min. Typ. Max. Min. Typ. Max. A 2.362 - 2.642 0.093 - 0.104 A1 0.102 - 0.305 0.004 - 0.012 b - 0.406 - - 0.016 - c - 0.254 - - 0.010 - D 17.704 - 18.110 0.697 - 0.713 E 7.391 - 7.595 0.291 - 0.299 e - 1.270 - - 0.050 - H 10.008 - 10.643 0.394 - 0.419 L1 0.406 - 1.270 0.016 - 0.050 y - - 0.102 - - 0.004 θ 0 A2 L © Sunplus Technology Co., Ltd. Proprietary & Confidential 0 8 22 0 0 0 8 0 AUG. 07, 2002 Version: 1.0 SPMC802B 7.1.10. SOP 28 (330mil) E D X c y H 28 15 A2 A A1 L pin 1 index L1 θ detail X 1 14 e b Symbol Dimension in mm Min. Dimension in inch Typ. Max. Min. Typ. Max. 0.112 A - - 2.845 - - A1 0.102 - - 0.004 - - A2 2.362 2.489 2.616 0.093 0.098 0.103 b 0.355 0.406 0.508 0.014 0.016 0.020 c 0.203 0.254 0.356 0.008 0.010 0.014 D - 18.110 18.618 - 0.713 0.733 E 8.280 8.407 8.534 0.326 0.331 0.336 e 1.118 1.270 1.422 0.044 0.050 0.056 H 11.506 11.811 12.116 0.453 0.465 0.477 L 1.499 0.914 1.905 0.028 0.036 0.044 L1 0.711 1.702 1.117 0.059 0.067 0.075 y - - 0.102 - - 0.004 θ 0 - 10 - 10 © Sunplus Technology Co., Ltd. Proprietary & Confidential 0 23 0 0 0 0 AUG. 07, 2002 Version: 1.0 SPMC802B 7.1.11. SOP 32 (445mil) E D X c y H 30 17 A2 A A1 L L1 θ detail X pin 1 index 16 1 e b Symbol Dimension in mm Min. Dimension in inch Typ. Max. Min. Typ. Max. 0.116 A - - 2.997 - - A1 0.102 - - 0.004 - - A2 2.565 2.692 2.819 0.101 0.106 0.111 b 0.356 0.406 0.508 0.014 0.016 0.020 c 0.152 0.203 0.305 0.006 0.008 0.012 D 20.142 20.447 20.752 0.793 0.805 0.817 E 11.176 11.303 11.430 0.440 0.445 0.450 e 1.118 1.270 1.422 0.044 0.050 0.056 H 13.868 14.122 14.376 0.546 0.556 0.566 L 0.584 0.787 0.991 0.023 0.031 0.039 L1 1.194 1.397 1.600 0.047 0.055 0.063 - 0.102 - - 0.004 - 10 - 10 y - θ 0 © Sunplus Technology Co., Ltd. Proprietary & Confidential 0 24 0 0 0 0 AUG. 07, 2002 Version: 1.0 SPMC802B 7.2. Ordering Information Product Number Chip form SPMC802B-PD03 Package form - PDIP 16 SPMC802B-PD04 Package form - PDIP 18 SPMC802B-PD05 Package form - PDIP 20 SPMC802B-PD06 Package form - PDIP 24 SPMC802B-PD08 Package form - PDIP 28 (300mil) SPMC802B-PD09 Package form - PDIP 28 (600mil) SPMC802B-PD11 Package form - PDIP 32 (600mil) SPMC802B-PS04 Package form - SOP 24 (300mil) SPMC802B-PS05 Package form - SOP 28 (300mil) SPMC802B-PS06 Package form - SOP 28 (330mil) SPMC802B-PS08 Package form - SOP 32 (445mil) © Sunplus Technology Co., Ltd. Proprietary & Confidential Package Type SPMC802B-C 25 AUG. 07, 2002 Version: 1.0 SPMC802B 8. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only. © Sunplus Technology Co., Ltd. Proprietary & Confidential 26 AUG. 07, 2002 Version: 1.0 SPMC802B 9. REVISION HISTORY Date Revision # AUG. 07, 2002 1.0 © Sunplus Technology Co., Ltd. Proprietary & Confidential Description Original Page 27 27 AUG. 07, 2002 Version: 1.0