SSM9960(G)H,J N-CHANNEL ENHANCEMENT-MODE POWER MOSFET Low gate-charge D Simple drive requirement Fast switching BV DSS 40V R DS(ON) 16mΩ 42A ID G S Description G D S The SSM9960H is in a TO-252 package, which is widely used for commercial and industrial surface mount applications, and is well suited for low voltage applications such as DC/DC converters. The through-hole version, the SSM9960J in TO-251, is available for low-footprint vertical G This device is available with Pb-free lead finish (second-level interconnect) as SSM9960GH or SSM9960GJ. D S TO-252 (H) TO-251 (J) Absolute Maximum Ratings Parameter Symbol Rating Units VDS Drain-Source Voltage 40 V VGS Gate-Source Voltage ± 20 V ID @ TA=25°C Continuous Drain Current, VGS @ 10V 42 A ID @ TA=100°C Continuous Drain Current, VGS @ 10V 26 A 195 A 1 IDM Pulsed Drain Current PD @ TA=25°C Total Power Dissipation 45 W Linear Derating Factor 0.36 W/°C TSTG Storage Temperature Range -55 to 150 °C TJ Operating Junction Temperature Range -55 to 150 °C Thermal Data Symbol Parameter Value Unit Rthj-c Thermal Resistance Junction-case Max. 2.8 °C/W Rthj-a Thermal Resistance Junction-ambient Max. 110 °C/W 11/16/2004 Rev.2.1 www.SiliconStandard.com 1 of 5 SSM9960(G)H,J Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. 40 - BVDSS Drain-Source Breakdown Voltage ∆ BV DSS/∆ Tj Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA - RDS(ON) Static Drain-Source On-Resistance VGS=10V, ID=20A - VGS=4.5V, ID=18A - V - V/°C - 16 mΩ - - 25 mΩ VDS=VGS, ID=250uA 1 - 3 V VDS=10V, ID=20A - 30 - S VDS=40V, VGS=0V - - 1 uA Drain-Source Leakage Current (Tj=150 C) VDS=32V ,VGS=0V - - 25 uA Gate-Source Leakage VGS= ± 20V - - ±100 nA ID=20A - 18 - nC VGS(th) Gate Threshold Voltage gfs Forward Transconductance o IDSS Drain-Source Leakage Current (Tj=25 C) o IGSS 2 VGS=0V, ID=250uA Max. Units 0.032 Qg Total Gate Charge Qgs Gate-Source Charge VDS=20V - 6 - nC Qgd Gate-Drain ("Miller") Charge VGS=4.5V - 12 - nC VDS=20V - 9 - ns 2 td(on) Turn-on Delay Time tr Rise Time ID=20A - 110 - ns td(off) Turn-off Delay Time RG=3.3Ω , VGS=10V - 23 - ns tf Fall Time RD=1Ω 10 - ns Ciss Input Capacitance VGS=0V - 1500 - pF Coss Output Capacitance VDS=25V - 250 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 180 - pF Min. Typ. IS=45A, VGS=0V - - 1.3 V ns nC - Source-Drain Diode Symbol Parameter 2 Test Conditions Max. Units VSD Forward On Voltage trr Reverse Recovery Time IS=20A, VGS=0V - 22 - Qrr Reverse Recovery Charge dI/dt = 100A/us - 27.4 - Notes: 1.Pulse width limited by safe operating area. 2.Pulse width <300us , duty cycle <2%. 11/16/2004 Rev.2.1 www.SiliconStandard.com 2 of 5 SSM9960(G)H,J 200 140 10.0V T C =150 o C 120 10V 8.0V 150 8.0V ID , Drain Current (A) ID , Drain Current (A) T C =25 o C 6.0V 100 50 100 80 6.0V 60 40 V G =4.0V V G =4.0V 20 0 0 0.0 1.5 3.0 4.5 0 1 Fig 1. Typical Output Characteristics 3 4 5 6 Fig 2. Typical Output Characteristics 1.80 60 I D =20A I D =20A T C =25°C Normalized RDS(ON) 1.60 40 RDS(ON) (mΩ ) 2 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) 20 V G =10V 1.40 1.20 1.00 0.80 0.60 0 0 4 8 12 -50 16 0 V GS , Gate-to-Source Voltage (V) 1000 2.5 100 2 T j =150 o C 100 150 Fig 4. Normalized On-Resistance vs. Junction Temperature VGS(th) (V) IS(A) Fig 3. On-Resistance vs. Gate Voltage 10 50 T j , Junction Temperature ( o C) o T j =25 C 1.5 1 1 0.5 0 -50 0.0 0.4 0.8 1.2 100 175 o T j , Junction Temperature ( C ) V SD (V) Fig 5. Forward Characteristic of Reverse Diode 11/16/2004 Rev.2.1 25 1.6 Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 5 SSM9960(G)H,J 12 I D =20A Ciss V DS =12V V DS =16V V DS =20V 10 8 1000 C (pF) VGS , Gate to Source Voltage (V) f=1.0MHz 10000 14 6 Coss Crss 100 4 2 10 0 0 10 20 30 1 40 8 15 22 29 V DS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 1000 100 ID (A) 10us 100us 10 1ms T c =25 o C Single Pulse 10ms 100ms 1 Normalized Thermal Response (Rthjc) 1 DUTY=0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 Single Pulse PDM t Duty factor = t/T Peak Tj = PDM x Rthjc + Tc T 0.001 0.1 1 10 100 0.0001 0.001 0.01 V DS , Drain-to-Source Voltage (V) Fig 9. Maximum Safe Operating Area 0.1 1 10 100 1000 t , Pulse Width (s) Fig 10. Effective Transient Thermal Impedance RD VDS TO THE D 0.5x RATED VDS G 0.5 x RATED VDS RG G S VGS + + S 10V VGS - 1~ 3 mA IG Fig 11. Switching Time Circuit 11/16/2004 Rev.2.1 OSCILLOSCOPE D TO THE OSCILLOSCOPE VDS ID Fig 12. Gate Charge Circuit www.SiliconStandard.com 4 of 5 SSM9960(G)H,J Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 11/16/2004 Rev.2.1 www.SiliconStandard.com 5 of 5