SSM9971GH,J N-CHANNEL ENHANCEMENT-MODE POWER MOSFET Low gate-charge D Simple drive requirement Fast switching BV DSS 60V R DS(ON) 36mΩ 25A ID G S Description G D S The SSM9971GH is in a TO-252 package, which is widely used for commercial and industrial surface mount applications, and is well suited for low voltage applications such as DC/DC converters. The through-hole version, the SSM9971GJ in TO-251, is available for low-footprint vertical mounting. These devices are manufactured with an advanced process, providing improved on-resistance and switching performance. G Pb-free lead finish (second-level interconnect) D S TO-252 (H) TO-251 (J) Absolute Maximum Ratings Symbol Parameter Rating Units VDS Drain-Source Voltage 60 V VGS Gate-Source Voltage ±20 V ID @ TA=25°C Continuous Drain Current, VGS @ 10V 25 A ID @ TA=100°C Continuous Drain Current, VGS @ 10V 16 A 1 IDM Pulsed Drain Current 80 A PD @ TA=25°C Total Power Dissipation 39 W Linear Derating Factor 0.31 W/°C TSTG Storage Temperature Range -55 to 150 °C TJ Operating Junction Temperature Range -55 to 150 °C Thermal Data Symbol Parameter Value Unit Rthj-c Thermal Resistance Junction-case Max. 3.2 °C/W Rthj-a Thermal Resistance Junction-ambient Max. 110 °C/W 2/16/2005 Rev.2.2 www.SiliconStandard.com 1 of 5 SSM9971GH,J Electrical Characteristics @ Tj=25oC (unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Units 60 - - V BVDSS Drain-Source Breakdown Voltage ∆ BV DSS/∆ Tj Breakdown Voltage Temperature Coefficient Reference to 25°C, ID=1mA - 0.05 - V/°C RDS(ON) Static Drain-Source On-Resistance2 VGS=10V, ID=18A - - 36 mΩ VGS=4.5V, ID=12A - - 50 mΩ VDS=VGS, ID=250uA 1 - 3 V VDS=10V, ID=18A - 17 - S VDS=60V, VGS=0V - - 1 uA Drain-Source Leakage Current (Tj=150 C) VDS=48V ,VGS=0V - - 25 uA Gate-Source Leakage VGS= ± 20V - - ±100 nA ID=18A - 18 30 nC VGS(th) Gate Threshold Voltage gfs Forward Transconductance o IDSS Drain-Source Leakage Current (Tj=25 C) o IGSS 2 VGS=0V, ID=250uA Qg Total Gate Charge Qgs Gate-Source Charge VDS=48V - 6 - nC Qgd Gate-Drain ("Miller") Charge VGS=4.5V - 11 - nC VDS=30V - 9 - ns 2 td(on) Turn-on Delay Time tr Rise Time ID=18A - 24 - ns td(off) Turn-off Delay Time RG=3.3Ω , VGS=10V - 26 - ns tf Fall Time RD=1.67Ω - 7 - ns Ciss Input Capacitance VGS=0V - 1700 2700 pF Coss Output Capacitance VDS=25V - 160 - pF Crss Reverse Transfer Capacitance f=1.0MHz - 110 - pF Min. Typ. Source-Drain Diode Symbol Parameter 2 Test Conditions Max. Units VSD Forward On Voltage IS=25A, VGS=0V - - 1.2 V trr Reverse Recovery Time IS=18A, VGS=0V, - 37 - ns Qrr Reverse Recovery Charge dI/dt=100A/µs - 38 - nC Notes: 1.Pulse width limited by safe operating area. 2.Pulse width <300us , duty cycle <2%. 2/16/2005 Rev.2.2 www.SiliconStandard.com 2 of 5 SSM9971GH,J 100 70 T C =25 o C 10V 7.0V 60 10V 7.0V 5.0V 50 5.0V 40 4.5V o T C =150 C 60 ID , Drain Current (A) ID , Drain Current (A) 80 4.5V 40 30 20 V G =3.0V 20 V G =3.0V 10 0 0 0 1 2 3 4 5 0 1 2 3 4 5 6 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics Fig 2. Typical Output Characteristics 40 2.5 I D =18A V G =10V I D = 18 A o T C =25 C Normalized R DS(ON) 2.0 RDS(ON) (mΩ ) 35 30 1.5 1.0 0.5 rr 0.0 25 3 5 7 9 -50 11 0 50 100 o V GS , Gate-to-Source Voltage (V) Qrr 150 T j , Junction Temperature ( C) Fig 3. On-Resistance vs. Gate Voltage Fig 4. Normalized On-Resistance vs. Junction Temperature 3 20 2.5 16 T j =25 o C T j =150 o C 2 IS(A) VGS(th) (V) 12 8 1.5 1 4 0.5 0 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -50 0 Fig 5. Forward Characteristic of Reverse Diode 2/16/2005 Rev.2.2 50 100 150 o V SD , Source-to-Drain Voltage (V) T j ,Junction Temperature ( C) Fig 6. Gate Threshold Voltage vs. Junction Temperature www.SiliconStandard.com 3 of 5 SSM9971GH,J f=1.0MHz 14 10000 I D =18A V DS =30V V DS =38V V DS =48V 10 Ciss 1000 8 C (pF) VGS , Gate to Source Voltage (V) 12 6 Coss Crss 100 4 2 0 10 0 10 20 30 40 1 5 9 13 17 21 25 29 V DS , Drain-to-Source Voltage (V) Q G , Total Gate Charge (nC) Fig 7. Gate Charge Characteristics Fig 8. Typical Capacitance Characteristics 100 1 100us Normalized Thermal Response (R thjc) Duty factor=0.5 1ms 10 ID (A) 10ms 100ms 1s DC 1 o T C =25 C Single Pulse 0.2 0.1 0.1 0.05 PDM t 0.02 T 0.01 Duty factor = t/T Peak Tj = PDM x Rthjc + TC Single Pulse rr 0.01 0.1 0.1 1 10 100 1000 0.00001 0.0001 0.001 0.01 0.1 Qrr 1 V DS , Drain-to-Source Voltage (V) t , Pulse Width (s) Fig 9. Maximum Safe Operating Area Fig 10. Effective Transient Thermal Impedance VG VDS 90% QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Fig 11. Switching Time Waveform 2/16/2005 Rev.2.2 Charge Q Fig 12. Gate Charge Waveform www.SiliconStandard.com 4 of 5 SSM9971GH,J Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 2/16/2005 Rev.2.2 www.SiliconStandard.com 5 of 5