1 Megabit (128K x 8) Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Data Sheet FEATURES: • Single Voltage Read and Write Operations – 5.0V-only for the 29EE010 – 3.0V-only for the 29LE010 – 2.7V-only for the 29VE010 • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption – Active Current: 20 mA (typical) for 5V and 10 mA (typical) for 3.0/2.7V – Standby Current: 10 µA (typical) • Fast Page-Write Operation – 128 Bytes per Page, 1024 Pages – Page-Write Cycle: 5 ms (typical) – Complete Memory Rewrite: 5 sec (typical) – Effective Byte-write Cycle Time: 39 µs (typical) • Fast Read Access Time – 5.0V-only operation: 90 and 120 ns – 3.0V-only operation: 150 and 200 ns – 2.7V-only operation: 200 and 250 ns • Latched Address and Data • Automatic Write Timing – Internal Vpp Generation • End of Write Detection – Toggle Bit – Data# Polling • Hardware and Software Data Protection • TTL I/O Compatibility • JEDEC Standard Byte-wide EEPROM Pinouts • Packages Available – 32-Pin TSOP (8x20 & 8x14 mm) – 32-Lead PLCC – 32 Pin Plastic DIP 1 2 3 4 5 6 7 PRODUCT DESCRIPTION The 29EE010/29LE010/29VE010 are 128K x 8 CMOS page mode EEPROMs manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split gate cell design and thick oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The 29EE010/ 29LE010/29VE010 write with a single power supply. Internal Erase/Program is transparent to the user. The 29EE010/29LE010/29VE010 conform to JEDEC standard pinouts for byte-wide memories. Featuring high performance page write, the 29EE010/ 29LE010/29VE010 provide a typical byte-write time of 39 µsec. The entire memory, i.e., 128K bytes, can be written page by page in as little as 5 seconds, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of a write cycle. To protect against inadvertent write, the 29EE010/29LE010/ 29VE010 have on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the 29EE010/ 29LE010/29VE010 are offered with a guaranteed pagewrite endurance of 104 or 103 cycles. Data retention is rated at greater than 100 years. The 29EE010/29LE010/29VE010 are suited for applications that require convenient and economical updating of program, configuration, or data memory. For all system applications, the 29EE010/29LE010/29VE010 significantly improve performance and reliability, while lowering power consumption, when compared with floppy disk or EPROM approaches. The 29EE010/29LE010/ 29VE010 improve flexibility while lowering the cost for program, data, and configuration storage applications. To meet high density, surface mount requirements, the 29EE010/29LE010/29VE010 are offered in 32-pin TSOP and 32-lead PLCC packages. A 600-mil, 32-pin PDIP package is also available. See Figures 1 and 2 for pinouts. Device Operation The SST page mode EEPROM offers in-circuit electrical write capability. The 29EE010/29LE010/29VE010 does not require separate erase and program operations. The internally timed write cycle executes both erase and program transparently to the user. The 29EE010/ 29LE010/29VE010 have industry standard optional Software Data Protection, which SST recommends always to be enabled. The 29EE010/29LE010/29VE010 are compatible with industry standard EEPROM pinouts and functionality. Read The Read operations of the 29EE010/29LE010/ 29VE010 are controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the © 1998 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 304-04 12/97 1 8 9 10 11 12 13 14 15 16 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the read cycle timing diagram for further details (Figure 3). leave the 29EE010/29LE010/29VE010 protected at the end of the page write. The page load cycle consists of loading 1 to 128 bytes of data into the page buffer. The internal write cycle consists of the TBLCO time-out and the write timer operation. During the Write operation, the only valid reads are Data# Polling and Toggle Bit. Write The Page Write to the SST29EE010/29LE010/29VE010 should always use the JEDEC Standard Software Data Protection (SDP) 3-byte command sequence. The 29EE010/29LE010/29VE010 contain the optional JEDEC approved Software Data Protection scheme. SST recommends that SDP always be enabled, thus, the description of the Write operations will be given using the SDP enabled format. The 3-byte SDP Enable and SDP Write commands are identical; therefore, any time a SDP Write command is issued, software data protection is automatically assured. The first time the 3-byte SDP command is given, the device becomes SDP enabled. Subsequent issuance of the same command bypasses the data protection for the page being written. At the end of the desired page write, the entire device remains protected. For additional descriptions, please see the application notes on “The Proper Use of JEDEC Standard Software Data Protection” and “Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories” in this data book. The Page-Write operation allows the loading of up to 128 bytes of data into the page buffer of the 29EE010/ 29LE010/29VE010 before the initiation of the internal write cycle. During the internal write cycle, all the data in the page buffer is written simultaneously into the memory array. Hence, the page-write feature of 29EE010/ 29LE010/29VE010 allow the entire memory to be written in as little as 5 seconds. During the internal write cycle, the host is free to perform additional tasks, such as to fetch data from other locations in the system to set up the write to the next page. In each Page-Write operation, all the bytes that are loaded into the page buffer must have the same page address, i.e. A7 through A16. Any byte not loaded with user data will be written to FF. See Figures 4 and 5 for the page-write cycle timing diagrams. If after the completion of the 3-byte SDP load sequence or the initial byte-load cycle, the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 100 µs, the 29EE010/29LE010/29VE010 will stay in the page load cycle. Additional bytes are then loaded consecutively. The page load cycle will be terminated if no additional byte is loaded into the page buffer within 200 µs (TBLCO) from the last byte-load cycle, i.e., no subsequent WE# or CE# high-to-low transition after the last rising edge of WE# or CE#. Data in the page buffer can be changed by a subsequent byte-load cycle. The page load period can continue indefinitely, as long as the host continues to load the device within the byteload cycle time of 100 µs. The page to be loaded is determined by the page address of the last byte loaded. The Write operation consists of three steps. Step 1 is the three byte load sequence for Software Data Protection. Step 2 is the byte-load cycle to a page buffer of the 29EE010/29LE010/29VE010. Steps 1 and 2 use the same timing for both operations. Step 3 is an internally controlled write cycle for writing the data loaded in the page buffer into the memory array for nonvolatile storage. During both the SDP 3-byte load sequence and the byte-load cycle, the addresses are latched by the falling edge of either CE# or WE#, whichever occurs last. The data is latched by the rising edge of either CE# or WE#, whichever occurs first. The internal write cycle is initiated by the TBLCO timer after the rising edge of WE# or CE#, whichever occurs first. The write cycle, once initiated, will continue to completion, typically within 5 ms. See Figures 4 and 5 for WE# and CE# controlled page write cycle timing diagrams and Figures 14 and 16 for flowcharts. Software Chip-Erase The 29EE010/29LE010/29VE010 provide a Chip-Erase operation, which allows the user to simultaneously clear the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Software Chip-Erase operation is initiated by using a specific six byte-load sequence. After the load sequence, the device enters into an internally timed cycle similar to the write cycle. During the erase operation, the only valid read is Toggle Bit. See Table 4 for the load sequence, Figure 9 for timing diagram, and Figure 18 for the flowchart. The Write operation has three functional cycles: the Software Data Protection load sequence, the page load cycle, and the internal write cycle. The Software Data Protection consists of a specific three byte load sequence that allows writing to the selected page and will © 1998 Silicon Storage Technology, Inc. 2 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Write Operation Status Detection The 29EE010/29LE010/29VE010 provide two software means to detect the completion of a write cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The end of write detection mode is enabled after the rising WE# or CE# whichever occurs first, which initiates the internal write cycle. Hardware Data Protection Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle. 1 VCC Power Up/Down Detection: The write operation is inhibited when VCC is less than 2.5V. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the write cycle, otherwise the rejection is valid. Software Data Protection (SDP) The 29EE010/29LE010/29VE010 provide the JEDEC approved optional software data protection scheme for all data alteration operations, i.e., Write and Chip erase. With this scheme, any write operation requires the inclusion of a series of three byte-load operations to precede the data loading operation. The three byte-load sequence is used to initiate the write cycle, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. The 29EE010/29LE010/29VE010 are shipped with the software data protection disabled. Data# Polling (DQ7) When the 29EE010/29LE010/29VE010 are in the internal write cycle, any attempt to read DQ7 of the last byte loaded during the byte-load cycle will receive the complement of the true data. Once the write cycle is completed, DQ7 will show true data. The device is then ready for the next operation. See Figure 6 for Data# Polling timing diagram and Figure 15 for a flowchart. The software protection scheme can be enabled by applying a three-byte sequence to the device, during a page-load cycle (Figures 4 and 5). The device will then be automatically set into the data protect mode. Any subsequent write operation will require the preceding three-byte sequence. See Table 4 for the specific software command codes and Figures 4 and 5 for the timing diagrams. To set the device into the unprotected mode, a six-byte sequence is required. See Table 4 for the specific codes and Figure 8 for the timing diagram. If a write is attempted while SDP is enabled the device will be in a non-accessible state for ~ 300 µs. SST recommends Software Data Protection always be enabled. See Figure 16 for flowcharts. Toggle Bit (DQ6) During the internal write cycle, any consecutive attempts to read DQ6 will produce alternating 0’s and 1’s, i.e. toggling between 0 and 1. When the write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 7 for Toggle Bit timing diagram and Figure 15 for a flowchart. The initial read of the Toggle Bit will typically be a “1”. The 29EE010/29LE010/29VE010 Software Data Protection is a global command, protecting (or unprotecting) all pages in the entire memory array once enabled (or disabled). Therefore using SDP for a single page write will enable SDP for the entire array. Single pages by themselves cannot be SDP enabled or disabled. Data Protection The 29EE010/29LE010/29VE010 provide both hardware and software features to protect nonvolatile data from inadvertent writes. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 © 1998 Silicon Storage Technology, Inc. 3 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Single power supply reprogrammable nonvolatile memories may be unintentionally altered. SST strongly recommends that Software Data Protection (SDP) always be enabled. The 29EE010/29LE010/29VE010 should be programmed using the SDP command sequence. SST recommends the SDP Disable Command Sequence not be issued to the device prior to writing. multiple manufacturers in the same socket. For details, see Table 3 for hardware operation or Table 4 for software operation, Figure 10 for the software ID entry and read timing diagram and Figure 17 for the ID entry command sequence flowchart. The manufacturer and device codes are the same for both operations. TABLE 1: PRODUCT IDENTIFICATION TABLE Byte Manufacturer’s Code 0000 H 29EE010 Device Code 0001 H 29LE010 Device Code 0001 H 29VE010 Device Code 0001 H Please refer to the following Application Notes located at the back of this databook for more information on using SDP: • Protecting Against Unintentional Writes When Using Single Power Supply Flash Memories • The Proper Use of JEDEC Standard Software Data Protection Data BF H 07 H 08 H 08 H 304 PGM T1.1 Product Identification Mode Exit Product Identification The product identification mode identifies the device as the 29EE010/29LE010/29VE010 and manufacturer as SST. This mode may be accessed by hardware or software operations. The hardware operation is typically used by a programmer to identify the correct algorithm for the 29EE010/29LE010/29VE010. Users may wish to use the software product identification operation to identify the part (i.e. using the device code) when using In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Software ID Exit (reset) operation, which returns the device to the read operation. The Reset operation may also be used to reset the device to the read mode after an inadvertent transient condition that apparently causes the device to behave abnormally, e.g. not read correctly. See Table 4 for software command codes, Figure 11 for timing waveform and Figure 17 for a flowchart. FUNCTIONAL BLOCK DIAGRAM OF SST 29EE010/29LE010/29VE010 1,048,576 Bit EEPROM Cell Array X-Decoder A16 - A0 Address buffer & Latches Y-Decoder and Page Latches CE# OE# WE# Control Logic I/O Buffers and Data Latches DQ7 - DQ0 304 MSW B1.0 © 1998 Silicon Storage Technology, Inc. 4 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 A11 A9 A8 A13 A14 NC WE# Vcc NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Standard Pinout Top View Die up 1 2 3 304 MSW F01.1 FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP PACKAGES 5 NC 1 32 Vcc A16 2 31 WE# A15 3 30 NC A12 4 5 29 28 A14 A7 A13 A7 5 29 A14 A6 A5 6 7 27 26 A8 A6 6 28 A13 A9 A5 7 27 A8 A4 A3 8 9 25 A11 Top View 24 A4 8 26 A9 OE# A10 A3 9 25 A11 A2 10 24 OE# 32-Pin PDIP A2 10 A1 11 22 CE# 23 A15 A12 4 NC WE# Vcc NC 1 32 31 30 A16 3 2 32-Lead PLCC Top View 6 A0 12 21 DQ7 A1 11 23 A10 DQ0 13 20 DQ6 A0 12 22 CE# DQ1 14 DQ5 DQ0 13 21 DQ7 DQ2 15 19 18 Vss 16 17 DQ3 14 15 16 DQ4 DQ1 DQ2 17 18 19 7 8 9 20 Vss DQ4 DQ6 DQ3 DQ5 304 MSW F02.1 FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN PLASTIC DIPS AND 32-LEAD PLCCS TABLE 2: PIN DESCRIPTION Symbol Pin Name A16-A7 Row Address Inputs A6-A0 DQ7-DQ0 Column Address Inputs Data Input/output CE# OE# WE# Vcc Chip Enable Output Enable Write Enable Power Supply Vss NC Ground No Connection Functions To provide memory addresses. Row addresses define a page for a write cycle. Column Addresses are toggled to load page data. To output data during read cycles and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE# or CE# is high. To activate the device when CE# is low. To gate the data output buffers. To control the write operations To provide 5-volt supply (± 10%) for the 29EE010, 3-volt supply (3.0-3.6V) for the 29LE010 and 2.7-volt supply (2.7-3.6V) for the 29VE010 Unconnected pins. 5 10 11 304 PGM T2.0 © 1998 Silicon Storage Technology, Inc. 4 304-04 12/97 12 13 14 15 16 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 TABLE 3: OPERATION MODES SELECTION Mode CE# OE# Read VIL VIL Page Write VIL VIH Standby VIH X Write Inhibit X VIL Write Inhibit X X Software Chip Erase VIL VIH Product Identification Hardware Mode VIL VIL Software Mode SDP Enable Mode SDP Disable Mode VIL VIL VIL VIH VIH VIH WE# VIH VIL X X VIH VIL DQ DOUT DIN High Z High Z/ DOUT High Z/ DOUT DIN Address AIN AIN X X X AIN, See Table 4 VIH Manufacturer Code (BF) Device Code (see notes) A16 - A1 = VIL, A9 = VH, A0 = VIL A16 - A1 = VIL, A9 = VH, A0= VIH See Table 4 See Table 4 See Table 4 VIL VIL VIL 304 PGM T3.0 TABLE 4: SOFTWARE COMMAND CODES Command Sequence 1st Bus Write Cycle Addr(1) Data 5555H AAH 2nd Bus Write Cycle Addr(1) Data 2AAAH 55H 3rd Bus Write Cycle Addr(1) Data 5555H A0H 4th Bus Write Cycle Addr(1) Data Addr(2) Data 5th Bus Write Cycle Addr(1) Data 6th Bus Write Cycle Addr(1) Data 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 20H 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H 5555H AAH 2AAAH 55H 5555H 90H 5555H AAH 2AAAH 55H 5555H F0H Alternate Software 5555H ID Entry(3) AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 60H Software Data Protect Enable & Page Write Software Data Protect Disable Software Chip Erase Software ID Entry Software ID Exit 304 PGM T4.1 Notes: (1) Address format A14-A0 (Hex), Addresses A15 and A16 are a “Don’t Care”. Page Write consists of loading up to 128 bytes (A6 - A0). (3) Alternate 6 byte software Product-ID Command Code (4) The software chip erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part. Notes for Software Product ID Command Code: 1. With A14 -A1 =0; SST Manufacturer Code = BFH, is read with A0 = 0, 29EE010 Device Code = 07H, is read with A0 = 1. 29LE010/29VE010 Device Code = 08H, is read with A0 = 1. 2. The device does not remain in Software Product ID Mode if powered down. (2) © 1998 Silicon Storage Technology, Inc. 6 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55°C to +125°C Storage Temperature ...................................................................................................................... -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VCC+ 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ......................................................... -1.0V to VCC+ 1.0V Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 14.0V Package Power Dissipation Capability (Ta = 25°C) ........................................................................................... 1.0W Through Hole Lead Soldering Temperature (10 Seconds) .............................................................................. 300°C Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C Output Short Circuit Current(1) ....................................................................................................................... 100 mA Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time. 29EE010 OPERATING RANGE Range Ambient Temp Commercial 0°C to +70°C Industrial -40°C to +85°C VCC 5V±10% 5V±10% 29LE010 OPERATING RANGE Range Ambient Temp Commercial 0°C to +70°C Industrial -40°C to +85°C VCC 3.0V to 3.6V 3.0V to 3.6V 29VE010 OPERATING RANGE Range Ambient Temp Commercial 0°C to +70°C Industrial -40°C to +85°C VCC 2.7V to 3.6V 2.7V to 3.6V 1 2 3 4 5 6 AC CONDITIONS OF TEST Input Rise/Fall Time ......... 10 ns Output Load ..................... 1 TTL Gate and CL = 100 pF 7 See Figures 12 and 13 8 9 10 11 12 13 14 15 16 © 1998 Silicon Storage Technology, Inc. 7 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 TABLE 5: 29EE010 DC OPERATING CHARACTERISTICS VCC = 5V±10% Limits Symbol Parameter Min Max Units ICC Power Supply Current Read 30 mA ISB1 ISB2 ILI ILO VIL VIH VOL VOH VH IH Write Standby VCC Current (TTL input) Standby VCC Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Supervoltage for A9 Supervoltage Current for A9 50 3 mA mA 50 µA 1 10 0.8 µA µA V V V V V µA 2.0 0.4 2.4 11.6 12.4 100 Test Conditions CE#=OE#=VIL,WE#=VIH , all I/Os open, Address input = VIL/VIH, at f=1/TRC Min., VCC=VCC Max CE#=WE#=VIL, OE#=VIH, VCC =VCC Max. CE#=OE#=WE#=VIH, VCC =VCC Max. CE#=OE#=WE#=VCC -0.3V. VCC = VCC Max. VIN =GND to VCC, VCC = VCC Max. VOUT =GND to VCC, VCC = VCC Max. VCC = VCC Max. VCC = VCC Max. IOL = 2.1 mA, VCC = VCC Min. IOH = -400µA, VCC = VCC Min. CE# = OE# =VIL, WE# = VIH CE# = OE# = VIL, WE# = VIH, A9 = VH Max. 304 PGM T5.0 TABLE 6: 29LE010/29VE010 DC OPERATING CHARACTERISTICS VCC = 3.0-3.6 FOR 29LE010, VCC = 2.7-3.6 FOR 29VE010 Limits Symbol Parameter Min Max Units Test Conditions Power Supply Current CE#=OE#=VIL,WE#=VIH , all I/Os open, ICC Read 12 mA Address input = VIL/VIH, at f=1/TRC Min., VCC=VCC Max Write 15 mA CE#=WE#=VIL, OE#=VIH, VCC =VCC Max. ISB1 Standby VCC Current 1 mA CE#=OE#=WE#=VIH, VCC =VCC Max. (TTL input) ISB2 Standby VCC Current 15 µA CE#=OE#=WE#=VCC -0.3V. (CMOS input) VCC = VCC Max. ILI Input Leakage Current 1 µA VIN =GND to VCC, VCC = VCC Max. ILO Output Leakage Current 10 µA VOUT =GND to VCC, VCC = VCC Max. VIL Input Low Voltage 0.8 V VCC = VCC Max. Input High Voltage 2.0 V VCC = VCC Max. VIH VOL Output Low Voltage 0.4 V IOL = 100 µA, VCC = VCC Min. VOH Output High Voltage 2.4 V IOH = -100 µA, VCC = VCC Min. VH Supervoltage for A9 11.6 12.4 V CE# = OE# =VIL, WE# = VIH IH Supervoltage Current 100 µA CE# = OE# = VIL, WE# = VIH, for A9 A9 = VH Max. 304 PGM T6.0 © 1998 Silicon Storage Technology, Inc. 8 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 TABLE 7: POWER-UP TIMINGS Symbol Parameter TPU-READ(1) Power-up to Read Operation (1) TPU-WRITE Power-up to Write Operation Maximum 100 5 Units µs ms 1 304 PGM T7.0 TABLE 8: CAPACITANCE (Ta = 25 °C, f=1 MHz, other pins open) Parameter Description Test Condition CI/O(1) I/O Pin Capacitance VI/O = 0V CIN(1) Input Capacitance VIN = 0V Maximum 12 pF 6 pF 2 3 304 PGM T8.0 Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 4 5 TABLE 9: RELIABILITY CHARACTERISTICS Symbol Parameter NEND TDR(1) VZAP_HBM(1) VZAP_MM(1) ILTH(1) Endurance Data Retention ESD Susceptibility Human Body Model ESD Susceptibility Machine Model Latch Up 6 Minimum Specification Units Test Method 10,000(2) 100 1000 Cycles Years Volts MIL-STD-883, Method 1033 JEDEC Standard A103 JEDEC Standard A114 200 Volts 100 mA JEDEC Standard A115 8 JEDEC Standard 78 304 PGM T9.1 Note: 7 9 (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (2)See Ordering Information for desired type. 10 11 12 13 14 15 16 © 1998 Silicon Storage Technology, Inc. 9 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 AC CHARACTERISTICS TABLE 10: 29EE010 READ CYCLE TIMING PARAMETERS 29EE010-90 Symbol Parameter Min Max 29EE010-120 Min Max Units TRC Read Cycle time TCE Chip Enable Access Time 90 120 ns TAA Address Access Time 90 120 ns TOE Output Enable Access Time TCLZ(1) CE# Low to Active Output 0 0 ns TOLZ(1) OE# Low to Active Output 0 0 ns 90 120 40 ns 50 ns (1) CE# High to High-Z Output 30 30 ns TOHZ(1) TOH(1) OE# High to High-Z Output 30 30 ns TCHZ Output Hold from Address Change 0 0 ns 304 PGM T10.1 TABLE 11: 29LE010 READ CYCLE TIMING PARAMETERS Symbol TRC TCE TAA TOE TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) 29LE010-150 Min Max 150 150 150 60 0 0 30 30 0 Parameter Read Cycle time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 29LE010-200 Min Max 200 200 200 100 0 0 50 50 0 Units ns ns ns ns ns ns ns ns ns 304 PGM T11.0 TABLE 12: 29VE010 READ CYCLE TIMING PARAMETERS Symbol TRC TCE TAA TOE TCLZ(1) TOLZ(1) TCHZ(1) TOHZ(1) TOH(1) 29VE010-200 Min Max 200 200 200 100 0 0 50 50 0 Parameter Read Cycle time Chip Enable Access Time Address Access Time Output Enable Access Time CE# Low to Active Output OE# Low to Active Output CE# High to High-Z Output OE# High to High-Z Output Output Hold from Address Change 29VE010-250 Min Max 250 250 250 120 0 0 50 50 0 Units ns ns ns ns ns ns ns ns ns 304 PGM T12.0 © 1998 Silicon Storage Technology, Inc. 10 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 TABLE 13: PAGE-WRITE CYCLE TIMING PARAMETERS Symbol TWC TAS TAH TCS TCH TOES TOEH TCP TWP TDS TDH TBLC(1) TBLCO(1) TIDA TSCE Parameter Write Cycle (erase and program) Address Setup Time Address Hold Time WE# and CE# Setup Time WE# and CE# Hold Time OE# High Setup Time OE# High Hold Time CE# Pulse Width WE# Pulse Width Data Setup Time Data Hold Time Byte Load Cycle Time Byte Load Cycle Time Software ID Access and Exit Time Software Chip Erase Min 0 50 0 0 0 0 70 70 35 0 0.05 200 29EE010 Max 10 100 10 20 29LE/VE010 Min Max 10 0 70 0 0 0 0 120 120 50 0 0.05 100 200 10 20 Units ms ns ns ns ns ns ns ns ns ns ns µs µs µs ms 1 2 3 4 5 6 7 304 PGM T13.1 Note: (1)This parameter is measured only for initial qualification and after the design or process change that could affect this parameter. 8 9 10 11 12 13 14 15 16 © 1998 Silicon Storage Technology, Inc. 11 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 304 AC F03.0 FIGURE 3: READ CYCLE TIMING DIAGRAM 304 AC F04.0 FIGURE 4: WE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM © 1998 Silicon Storage Technology, Inc. 12 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 1 2 3 4 5 6 304 AC F05.0 7 FIGURE 5: CE# CONTROLLED PAGE WRITE CYCLE TIMING DIAGRAM 8 9 10 11 12 13 14 15 304 AC F06.0 16 FIGURE 6: DATA# POLLING TIMING DIAGRAM © 1998 Silicon Storage Technology, Inc. 13 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 304 AC F07.0 FIGURE 7: TOGGLE BIT TIMING DIAGRAM 304 AC F08.0 FIGURE 8: SOFTWARE DATA PROTECT DISABLE TIMING DIAGRAM © 1998 Silicon Storage Technology, Inc. 14 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 1 2 3 4 5 6 304 AC F09.0 7 FIGURE 9: SOFTWARE CHIP ERASE TIMING DIAGRAM 8 9 10 11 DEVICE CODE 12 13 14 15 DEVICE CODE = 07 for 29EE010 = 08 for 29LE010/29VE010 304 AC F10.0 16 FIGURE 10: SOFTWARE ID ENTRY AND READ © 1998 Silicon Storage Technology, Inc. 15 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 304 AC F11.0 FIGURE 11: SOFTWARE ID EXIT AND RESET © 1998 Silicon Storage Technology, Inc. 16 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 2.4 2.0 INPUT 1 2.0 OUTPUT REFERENCE POINTS 2 0.8 0.8 0.4 304 MSW F12.0 3 AC test inputs are driven at VOH (2.4 VTTL) for a logic “1” and VOL (0.4 VTTL) for a logic “0”. Measurement reference points for inputs and outputs are VIH (2.0 VTTL) and VIL (0.8 VTTL). Inputs rise and fall times (10% ↔ 90%) are <10 ns. FIGURE 12: AC INPUT/OUTPUT REFERENCE WAVEFORMS 4 5 6 7 TEST LOAD EXAMPLE 8 VCC TO TESTER 9 RL HIGH 10 TO DUT 11 CL RL LOW 12 13 304 MSW F13.0 14 FIGURE 13: TEST LOAD EXAMPLE 15 16 © 1998 Silicon Storage Technology, Inc. 17 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Start Software Data Software Data ProtectWrite Write Protect Command Command See Figure 16 Set Page Address Set Byte Address = 0 Load Byte Data Increment Byte Address By 1 No Byte Address = 128 ? Yes Wait TBLCO Wait BLCO Wait endofof Wait for for end Write (TWC , Data , Write (TWC #Toggle Pollingbitbitoror Data # Polling Toggle bit bit operation) operation) Write Completed Figure 14: Write Algorithm 304 MSW F14.0 FIGURE 14: WRITE ALGORITHM © 1998 Silicon Storage Technology, Inc. 18 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Internal Timer Toggle Bit Data# Polling Page Write Initiated Page Write Initiated Page Write Initiated 1 2 3 4 Read DQ7 Read a byte from page Wait TWC (Data for last byte loaded) 5 6 Write Completed Read same byte No Is DQ7 = 7 true data? Yes No Does DQ6 match? 8 Write Completed 9 10 Yes Write Completed 11 12 304 MSW F15.0 FIGURE 15: WAIT OPTIONS 13 14 15 16 © 1998 Silicon Storage Technology, Inc. 19 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Software Data Protect Enable Command Sequence Software Data Protect Disable Command Sequence Write data: AA Address: 5555 Write data: AA Address: 5555 Write data: 55 Address: 2AAA Write data: 55 Address: 2AAA Write data: A0 Address: 5555 Write data: 80 Address: 5555 Load 0 to 128 Bytes of page data Optional Page Load Operation Write data: AA Address: 5555 Write data: 55 Address: 2AAA Wait TBLCO Write data: 20 Address: 5555 Wait TWC Wait TBLCO SDP Enabled Wait TWC SDP Disabled 304 MSW F16.0 FIGURE 16: SOFTWARE DATA PROTECTION FLOWCHARTS © 1998 Silicon Storage Technology, Inc. 20 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Software Product ID Entry Command Sequence 1 Software Product ID Exit & Reset Command Sequence 2 Write data: AA Address: 5555 Write data: AA Address: 5555 Write data: 55 Address: 2AAA Write data: 55 Address: 2AAA 3 4 5 Write data: 90 Address: 5555 6 Write data: F0 Address: 5555 7 Pause 10 µs 8 Pause 10 µs 9 Return to normal operation Read Software ID 10 11 304 MSW F17.0 12 FIGURE 17: SOFTWARE PRODUCT COMMAND FLOWCHARTS 13 14 15 16 © 1998 Silicon Storage Technology, Inc. 21 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Software Chip-Erase Command Sequence Write data: AA Address: 5555 Write data: 55 Address: 2AAA Write data: 80 Address: 5555 Write data: AA Address: 5555 Write data: 55 Address: 2AAA Write data: 10 Address: 5555 Wait TSCE Chip Erase to FFH 304 MSW F18.0 FIGURE 18: SOFTWARE CHIP ERASE COMMAND CODES © 1998 Silicon Storage Technology, Inc. 22 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 PRODUCT ORDERING INFORMATION Device SST29XE010 Speed - XXX Suffix1 - XX - Suffix2 1 XX 2 Package Modifier H = 32 leads Numeric = Die modifier 3 Package Type P = PDIP N = PLCC E = TSOP (die up) 8x20 mm W = TSOP (die up) 8x14 mm U = Unencapsulated die Operating Temperature C = Commercial = 0° to 70°C I = Industrial = -40° to 85°C Minimum Endurance 3 = 1000 cycles 4 = 10,000 cycles 4 5 6 7 8 9 Read Access Speed 250 = 250 ns 200 = 200 ns 150 = 150 ns 120 = 120 ns 90 = 90 ns 10 11 Voltage E = 5V-only L = 3V-only V = 2.7V-only 12 13 14 15 16 © 1998 Silicon Storage Technology, Inc. 23 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 29EE010 Valid combinations SST29EE010- 90-4C- EH SST29EE010- 90-4C- NH SST29EE010-120-4C- EH SST29EE010-120-4C- NH SST29EE010- 90-4C- PH SST29EE010-120-4C- PH SST29EE010- 90-4C- WH SST29EE010-120-4C- WH SST29EE010- 90-4I-EH SST29EE010-120-4I-EH SST29EE010- 90-4I-NH SST29EE010-120-4I-NH SST29EE010-120-4C-U2 29LE010 Valid combinations SST29LE010-150-4C- EH SST29LE010-150-4C- NH SST29LE010-200-4C- EH SST29LE010-200-4C- NH SST29LE010-150-4C- PH SST29LE010-200-4C- PH SST29LE010-150-4C- WH SST29LE010-200-4C- WH SST29LE010-150-4I-EH SST29LE010-150-4I-NH SST29LE010-200-4C-U2 29VE010 Valid combinations SST29VE010-200-4C- EH SST29VE010-200-4C- NH SST29VE010-250-4C- EH SST29VE010-250-4C- NH SST29VE010-200-4C- PH SST29VE010-250-4C- PH SST29VE010-200-4C-WH SST29VE010-250-4C-WH SST29VE010-200-4I-EH SST29VE010-200-4I-NH SST29VE010-250-4C-U2 Example:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Note: The software chip erase function is not supported by the industrial temperature part. Please contact SST, if you require this function for an industrial temperature part. © 1998 Silicon Storage Technology, Inc. 24 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 PACKAGING DIAGRAMS 1 2 3 4 5 6 32pn PDIP PH AC.2 7 Note: 1. Complies with JEDEC publication 95 MO-015 AP dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .010 inches. 32-LEAD PLASTIC DUAL-IN-LINE PACKAGE (PDIP) SST PACKAGE CODE: PH 8 9 10 11 12 13 14 32pn PLCC NH AC.2 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (min/max). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 16 32-LEAD PLASTIC LEAD CHIP CARRIER (PLCC) SST PACKAGE CODE: NH © 1998 Silicon Storage Technology, Inc. 25 15 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (±.05) mm. 32pn TSOP WH AC.3 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) SST PACKAGE CODE: WH Note: 1. Complies with JEDEC publication 95 MO-142 BD dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in metric (min/max). 3. Coplanarity: 0.1 (±.05) mm. 32pn TSOP EH AC.4 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) SST PACKAGE CODE: EH © 1998 Silicon Storage Technology, Inc. 26 304-04 12/97 1 Megabit Page Mode EEPROM SST29EE010, SST29LE010, SST29VE010 SST Area Offices U.S.A. - California U.S.A. - Florida U.S.A. - Florida U.S.A. - Massachusetts Japan - Yokohama Europe - UK Canada - Toronto Kaltron Components Inc. Canada - Ottawa Kaltron Components Inc. Canada - Montreal Kaltron Components Inc. Canada - B.C. Thorson Pacific, Inc. Puerto Rico MEC/Caribe (408) 523-7722 (813) 771-8819 (941) 505-8893 (978) 356-3845 (81) 45-471-1851 (44) 1784-490455 North American Sales Representatives Alabama Elcom, Inc. Arizona QuadRep, Inc. California Northern Premier Technical Sales Southern QuadRep, Inc., San Diego QuadRep, Inc., Irvine Colorado QuadRep, Inc. Florida MEC Corporation - Central/East Coast MEC Corporation - South/East Coast MEC Corporation - West Coast Georgia Elcom, Inc. Iowa Oasis Sales Corporation Idaho QuadRep, Inc. Illinois Oasis Sales Corporation - Northern Rush & West Associates - Southern Kansas Rush & West Associates Massachusetts S-J Associates Minnesota Cahill, Schmitz & Cahill Missouri Rush & West Associates North Carolina Elcom, Inc. - Charlotte Elcom, Inc. - Raleigh New Jersey S-J Associates New Mexico QuadRep, Inc. New York S-J Associates - NYC S-J Associates - Upstate Ohio Great Lakes - Columbus Great Lakes - Cleveland Oregon Thorson Pacific, Inc. Texas Tech. Mktg, Inc. - Carrollton Tech. Mktg, Inc. - Houston Tech. Mktg, Inc. - Austin Utah QuadRep, Inc. Virginia S-J Associates Washington Thorson Pacific, Inc. Wisconsin Oasis Sales Corporation (205) 830-4001 (905) 405-6276 1 (819) 457-1225 (514) 696-6589 2 (604) 294-3999 (787) 746-9897 International Sales Representatives & Distributors (602) 839-2102 Australia ACD Belgium Memec Brussels China Actron Technology Co., Ltd. Denmark Berendsen Components A/S Ireland Memec Ireland LTD Finland OXXO OY AB France RepDesign A2M Germany Endrich Bauelemente Vertriebs GMBH Metronik GmbH Hong Kong Actron Technology Co., Ltd. Serial System (HK) Ltd. Israel Elina Electronics Italy Carla Gavazzi Cefra SpA Japan Asahi Electronics Co., Ltd. Asahi Electronics Co., Ltd. Hakuto Co., Ltd. MICROTEK Inc. Ryoden Trading Co., Ltd. Silicon Technology Co., Ltd. Korea Bigshine Korea Co., Ltd. Netherlands Memec Benelux Singapore Serial System Ltd. South Africa KH Distributors Spain Tekelec Espana S.A. Sweden Pelcon Electronics AB Switzerland Leading Technology Taiwan, R.O.C. Award Software PCT Limited Tonsam Corporation United Kingdom Ambar Components, Ltd. (408) 736-2260 (619) 775-1188 (714) 727-4222 (303) 771-6886 (904) 427-7236 (954) 426-8944 (813) 393-5011 (770) 447-8200 (319) 377-8738 (208) 939-9626 (847) 640-1850 (314) 965-3322 (913) 764-2700 (978) 670-8899 (612) 646-7217 (314) 965-3322 (704) 543-1229 (919) 743-5200 (609) 866-1234 (505) 332-2417 (516) 536-4242 (716) 924-1720 (614) 885-6700 (216) 349-2700 (503) 293-9001 (972) 387-3601 (713) 783-4497 (512) 343-6976 (801) 521-4717 (703) 533-2233 (61) 3-762 7644 4 (32) 2778-9850 (86) 21-6482-8021 5 (45) 39-57-71-10 (353) 61 411842 (358) 9-5842 600 6 (33) 1 46 23 7990 (33) 1 46 23 7900 7 (49) 7452-60070 (49) 89-61108-0 8 (852) 2727-3978 (852) 2950-0820 (972) 3-649 8543 9 (39) 2-4801.2355 (81) 3-3350-5418 (81) 93-511-6471 (81) 3-3355-7615 (81) 3-5300-5525 (81) 3-5396-6206 (81) 3-3795-6461 10 11 (82) 2-832-8881 (31) 40-265-9399 12 (65) 286-1812 (27) 11 845-5011 13 (34) 13 20 41 60 (46) 8.795 98 70 14 (41) 277-21 7-446 (886) 22-555-0880 (886) 22-698-0098 (886) 22-651-0011 15 (44) 1844-261144 16 (425) 603-9393 (414) 782-6660 Revised 3-12-98 Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873 © 1998 Silicon Storage Technology, Inc. 3 27 304-04 12/97