SST SST38VF166-70-4C-EK

16 Megabit FlashBank Memory
SST38VF166
Data Sheet
SST38VF16616Mb (x16) FlashBank + 64Kb E2
FEATURES:
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Single 2.7-3.6V Read and Write Operations
Separate Memory Banks for Code or Data
– Simultaneous Read and Write Capability
Superior Reliability
– Endurance:
E2 bank - 500,000 Cycles (typical)
Flash bank - 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption
– Active Current, Read: 15 mA (typical)
– Active Current, Concurrent Read while Write:
40 mA (typical)
– Standby Current: 3 µA (typical)
– Auto Low Power Mode Current: 3 µA (typical)
Fast Write Operation
– Flash Bank-Erase + Program: 8 sec (typical)
– Flash Block-Erase + Program: 500 ms (typical)
– Flash Sector-Erase + Program: 30 ms (typical)
– E2 bank Word-Write: 9 ms (typical)
Fixed Erase, Program, Write Times
– Remain constant after cycling
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•
•
Read Access Time
– 70 ns
Latched Address and Data
End-of-Write Detection
– Toggle Bit
– Data# Polling
E2 Bank:
– Word-Write (Auto Erase before Program)
– Sector-Erase (32 Words) + Word-Program
(same as Flash bank)
Flash Bank: Two Small Erase Element Sizes
– 1 KWords per Sector or 32 KWords per Block
– Erase either element before Word-Program
CMOS I/O Compatibility
JEDEC Standard Command Set
Packages Available
– 48-Pin TSOP (12mm x 20mm)
Continuous Hardware and Software
Data Protection (SDP)
A One Time Programmable (OTP) E2 Sector
PRODUCT DESCRIPTION
The SST38VF166 consists of three memory banks, 2 each
512K x16 bits sector mode flash EEPROM plus a 4K x16
bits word alterable E2PROM manufactured with SST’s proprietary, high performance SuperFlash Technology. The
SST38VF166 erases and programs with a single power
supply. The internal Erase/Program in the E2 bank is transparent to the user. The device conforms to (proposed)
JEDEC standard pinouts for word-wide memories.
The SST38VF166 device is divided into three separate
memory banks, 2 each 512K x16 Flash banks and a 4K
x16 E2 bank. Each Flash bank is typically used for program
code storage and contains 512 sectors, each of 1 KWords
or 16 blocks, each of 32 KWords. The Flash banks may
also be used to store data. The E2 bank is typically used for
data or configuration storage and contains 128 sectors,
each of 32 words. Any bank may be used for executing
code while writing data to a different bank. Each memory
bank is controlled by separate Bank Enable (BE#) lines.
The SST38VF166 inherently uses less energy during
Erase, Program, and Write than alternative flash technologies. The total energy consumed is a function of the
applied voltage, current, and time of application. Since for
any given voltage range, the SuperFlash technology uses
©2001 Silicon Storage Technology, Inc.
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S71065
1
less current to program and has a shorter Erase time, the
total energy consumed during any Erase, Program, or
Write operation is less than alternative flash technologies.
The Auto Low Power mode automatically reduces the
active read current to approximately the same as standby;
thus, providing an average read current of approximately 1
mA/MHz of Read cycle time.
The SuperFlash technology provides fixed Erase, Program,
and Write times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated
as is necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
Device Operation
The SST38VF166 operates as two independent 8-Megabit
Word-Program, Sector-Erase flash EEPROMs with the
additional functionality of a 64 Kbit word-alterable
E2PROM. All banks are superimposed in the same memory address space. All three memory banks share common address lines, I/O lines, WE#, and OE#. Memory
bank selection is by bank enable. BE#1 selects the first
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
FlashBank is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Write Modes
Flash bank, BE#2 selects the second Flash bank, BE#3
selects the E2 bank. WE# is used with SDP to control the
Write or Erase and Program operation in each memory
bank.
The SST38VF166 device has separate Write modes for
the E2 bank and Flash banks. The conventional E2PROM
Word-Write with internally timed automatic Erase before
Program is the most convenient and easy method for the
user to alter data in the E2 bank with the Word-Write operation, the word being written is the only word that is altered.
Bank- or Sector-Erase plus Word-Program operations may
also be used for the E2 bank. For both banks of the Flash
array, the SST38VF166 offers Bank-, Block-, and SectorErase plus Word-Program operations.
The SST38VF166 provides the added functionality of
being able to simultaneously read from one memory bank
while writing, erasing, or programming to one other memory bank. Once the internally controlled Write, Erase, or
Program cycle in a memory bank has commenced, a different memory bank can be accessed for read. Also, once
WE# and the applicable BE# are high during the SDP load
sequence, a different bank may be accessed to read. If
multiple bank enables are asserted simultaneously, the outputs will tri-state and no new memory operations can be
initiated. Only one bank may be written, erased, or programmed at any given time. The device ID and Common
Flash Interface (CFI) functions cannot be accessed while
any bank is writing, erasing, or programming.
Write
All Write operations are initiated by first issuing the Software Data Protect (SDP) entry sequence for Bank-, Block-,
or Sector-Erase then Word-Program in the selected Flash
bank; or for Word-Write or for Sector-Erase and Word-Program in the E2 bank. Word-Write, Word-Program, and all
Erase commands have a fixed duration, that will not vary
over the life of the device, i.e., are independent of the number of Erase/Program cycles endured.
The Auto Low Power Mode automatically puts the device
in a near standby mode after data has been accessed with
a valid Read operation. This reduces the IDD active read
current from typically 15mA to typically 3µA. The Auto Low
Power mode reduces the typical IDD active read current to
the range of 1mA/MHz of Read cycle time. The device exits
the Auto Low Power Mode with any address transition or
control signal transition used to initiate another Read cycle,
with no access time penalty.
Either Flash bank may be read during the internally controlled E2 bank Write cycle, e.g., the Flash bank may be
accessed to fetch instructions or data when the E2 bank is
being written, erased, or programmed. Additionally, the
alternate Flash bank may be read while erasing or programming the other Flash or E2 bank. At any given time,
only one bank may be performing a Write operation, during
that time any other bank is available for read.
Flash Bank Read
The Read operation of the SST38VF166 Flash Bank is
controlled by BE#1 or BE#2 and OE#, a bank enable and
output enable both have to be low for the system to obtain
data from the outputs. BE#1 is used for Flash bank 1
selection. When BE#1 is high, the Flash bank 1 is deselected. BE#2 is used for Flash bank 2 selection. When
BE#2 is high, the Flash bank 2 is deselected. OE# is the
output control and is used to gate data from the output
pins. The data bus is in high impedance state when OE#
is high. Refer to the timing waveforms for further details
(Figure 2 or 3).
The Write Status command may be used to determine if
any bank is being written, at any given time. This may be
required if the system does not use a timer or does not
monitor toggle bit or data# polling when writing a specific
bank. In order to implement the Write Status command,
address 5XXXH in the E2 bank address space is reserved.
This address is outside the normal address space of the E2
bank; therefore, will not interfere with normal reading within
the E2 bank address space.
The device is always in the Software Data Protected mode
for all Write operations in both the Flash bank and E2 bank.
Write operations are controlled by toggling WE# or BE#.
The falling edge of WE# or BE#, whichever occurs last,
latches the address. The rising edge of WE# or BE#,
whichever occurs last, latches the data and initiates the
Erase, Program, or Write cycle.
E2 Bank Read
The Read operation of the E2 bank is controlled by BE#3
and OE#, both have to be low for the system to obtain data
from the outputs. BE#3 is used for E2 bank selection. When
BE#3 is high, the E2 bank is deselected. OE# is the output
control and is used to gate data from the output pins. The
data bus is in high impedance state when OE# is high.
Refer to the timing waveforms for further details (Figure 4).
The SDP Erase, Program, or Write commands are all BE#
specific. Whichever BE# is used for the first SDP bus cycle
(except for Read operation with WE# high), that BE# must
be used for all subsequent SDP bus cycles, for the command to be executed. If a different BE# is pulsed during a
©2001 Silicon Storage Technology, Inc.
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
The Write operation has two functional cycles: the Word
Load cycle and the internal Write cycle. The Word Load
cycle consists of loading 1 word of data into the word buffer
at the completion of the SDP sequence. The internal Write
cycle consists of the write timer operation, to erase and
program the selected address. Note, the word does NOT
have to be erased prior to writing. During the Write operation, the only valid reads are Data# Polling and Toggle Bit
from the E2 bank or normal read from either of the Flash
banks.
subsequent bus cycle, when WE# is low, in the SDP command sequence, the device will abort the attempted SDP
command and revert to the Read mode. Note, the SDP
command sequence may be suspended by taking WE#
high. A different BE# may then be pulsed to read from
either of the banks not involved with the SDP command
sequence.
For the purposes of simplification, the following descriptions will assume WE# is toggled to initiate an Erase, Program, or Write. Toggling the applicable BE# will accomplish
the same function. Note, there are separate timing diagrams to illustrate both WE# and BE# controlled Program
or Write commands.
E2 Bank Word-Program
The E2 bank Word-Program operation consists of issuing
the SDP Word-Program command, initiated by forcing
BE#3 and WE# low and OE# high. The Word-Program
command programs the desired addresses word-by-word.
The words to be programmed must be in the erased state,
prior to programming, unlike the Word-Write operation.
During the Word-Program cycle, the addresses are latched
by the falling edge of WE#. The data is latched by the rising
edge of WE#. See Figure 11 for WE# or 12 for BE#3 controlled Program cycle timing waveforms, Table 7 for the
command sequence and Figure 50 for a flowchart.
Flash Bank Word-Program
The Flash bank Word-Program operation consists of issuing the SDP Word-Program command, initiated by forcing
BE#1 or BE#2 and WE# low, and OE# high. The words to
be programmed must be in the erased state, prior to programming. The Word-Program command programs the
desired addresses word-by-word. During the Word-Program cycle, the addresses are latched by the falling edge of
WE#. The data is latched by the rising edge of WE#. See
Figure 5 or 7 for WE# or 6 and 8 for BE# controlled WordProgram cycle timing waveforms, Table 6 for the command
sequence, and Figure 49 for a flowchart.
During the E2 bank Erase or Program operation, the only
valid reads from the bank are Data# Polling and Toggle Bit.
Either Flash bank may be read.
During the Flash bank Erase or Program operation, the
only valid reads from that bank are Data# Polling and Toggle Bit. The other Flash bank or the E2 bank may be read.
The specified Bank- or Sector-Erase time is the only time
required to erase. There are no preprogramming or other
commands or cycles required either internally or externally
to erase the bank or sector.
The specified Bank-, Block-, or Sector-Erase time is the
only time required to erase. There are no preprogramming
or other commands or cycles required either internally or
externally to erase the bank, block, or sector.
Erase Operations
The Bank-Erase is initiated by a specific six-word load
sequence See Tables 6 and 7. A Bank-Erase will typically
be less than 70 ms.
E2 Bank Word-Write
The E2 bank Word-Write operation consists of issuing the
SDP command, initiated by forcing BE#3 and WE# low,
and OE# high; followed by the Word Load cycle to the
SST38VF166. The internally controlled Write cycle stores
the data loaded in the word buffer into the E2 bank. The
address selected is then erased and programmed, by internally controlled signals. During the Word Load cycle, the
address is latched by the falling edge of WE#. The data is
latched by the rising edge of WE#. The internal write cycle
is initiated on the rising edge of WE#. The Write cycle, once
initiated, will continue to completion, typically within 7 ms.
See Figure 9 for WE# or 10 for BE# controlled write cycle
timing waveforms, Table 7 for the command sequence, and
Figure 48 for a flowchart.
An alternative to the Bank-Erase in the Flash bank is the
Block-Erase or Sector-Erase. The Block-Erase will erase
an entire Block (32 KWords) in typically 15 ms. The SectorErase will erase an entire sector (1024 words) in typically
15 ms. The Sector-Erase provides a means to alter a single sector using the Sector-Erase and Word-Program
modes. The Sector-Erase is initiated by a specific six-word
load sequence, see Table 6.
The E2 bank may also use a Sector-Erase, instead of
Bank-Erase. An E2 bank sector consists of 32 words that
will typically erase in 7 ms. The Sector-Erase is initiated by
a specific six-word load sequence, see Table 7. Sector- or
Bank-Erase and Word-Program is an alternative to WordWrite as a means to alter the E2 bank.
©2001 Silicon Storage Technology, Inc.
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
The E2 Bank-Erase mode is initiated by issuing the specific
six-word loading sequence, as in the Software Data Protection operation. After the loading cycle, the device enters
into an internally timed cycle. See Table 7 for specific
codes, Figure 19 for the timing waveform, and Figure 44 for
a flowchart.
During any Sector-, Block-, or Bank-Erase within a bank,
any other bank may be read. During the Word-Write of the
E2 bank, either Flash bank may be read.
Flash Bank Bank-Erase
The SST38VF166 provides a Flash Bank-Erase mode,
which allows the user to clear the Flash bank to the “1”
state. This is useful when the entire Flash must be quickly
erased.
E2 Bank Sector-Erase
The SST38VF166 provides a Sector-Erase mode, which
allows the user to clear any sector in the E2 bank to the “1”
state. The software Sector-Erase mode is initiated by issuing the specific six-word loading sequence, as in the Software Data Protect operation. After the loading cycle, the
device enters into an internally timed. See Tables 6 and 7
for specific codes, Figure 20 for the timing waveform, and
Figure 46 for a flowchart. During the Erase operation, the
only valid reads are Data# Polling and Toggle Bit in the E2
bank or normal read from either of the Flash banks.
The software Flash Bank-Erase mode is initiated by issuing
the specific six-word loading sequence, as in the Software
Data Protection operation. After the loading cycle, the
device enters into an internally timed cycle. See Table 6 for
specific codes, Figure 13 or 16 for the timing waveform,
and Figure 44 for a flowchart.
Flash Bank Block-Erase
The SST38VF166 provides a Block-Erase mode, which
allows the user to clear any block in the Flash bank to the
“1” state.
Write Operation Status Detection
The SST38VF166 provides two software means to detect
the completion of a E2 bank or a Flash bank Program
cycle, in order to optimize the system Write cycle time. The
software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write Detection
mode is enabled after the rising edge of WE#, which initiates the internal Write, Erase, or Program cycle.
The software Block-Erase mode is initiated by issuing the
specific six-word loading sequence, as in the Software
Data Protect operation. After the loading cycle, the device
enters into an internally timed Erase cycle. See Table 6 for
specific codes, Figure 14 or 17 for the timing waveform,
and Figure 45 for a flowchart. During the Erase operation,
the only valid reads are Data# Polling and Toggle Bit from
the selected bank, other banks may perform normal read.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the Write cycle. If this occurs, the system will possibly get
an erroneous result, i.e. valid data may appear to conflict
with either DQ7 or DQ6. In order to prevent spurious device
rejection, if an erroneous result occurs, the software routine
should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the Write cycle, otherwise the rejection is valid.
Flash Bank Sector-Erase
The SST38VF166 provides a Sector-Erase mode, which
allows the user to clear any sector in the Flash bank to the
“1” state.
The software Sector-Erase mode is initiated by issuing the
specific six-word loading sequence, as in the Software
Data Protect operation. After the loading cycle, the device
enters into an internally timed Erase cycle. See Table 6 for
specific codes, Figure 15 or 18 for the timing waveform,
and Figure 47 for a flowchart. During the Erase operation,
the only valid reads are Data# Polling and Toggle Bit from
the selected bank, other banks may perform normal read.
Additionally, a Write Status read may be executed to determine if any bank has an Erase, Program, or Write operation in progress. A Write Status read may be used when,
for any reason, the system may have lost track of the status
of a Write, Erase, or Program operation in any bank.
Although normally, a Word-Write, Word-Program, SectorErase, or Block-Erase will be completed prior to recovery
from a system reset, if a Bank-Erase was initiated prior to
the reset, the system may need to verify the Bank-Erase is
no longer in progress. Note, a Bank-Erase will not be performed on the bank containing the boot code, so there will
E2 Bank Bank-Erase
The SST38VF166 provides a E2 Bank-Erase mode, which
allows the user to clear the E2 bank to the “1” state. This is
useful when the entire E2 bank must be quickly erased.
The E2 bank Bank-Erase command is disabled if the E2
bank OTP option is enabled.
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Toggle Bit (DQ6) - E2 Bank
be no issue when recovering from the system reset. See
Table 6 or 7 for the specific codes and Figure 40 for a timing
waveform.
During the E2 bank internal Write cycle, any consecutive
attempts to read DQ6 will produce alternating 0s and 1s,
i.e. toggling between 0 and 1. When the Write cycle is completed, the toggling will stop. The device is then ready for
the next operation. See Figure 26 for E2 bank Toggle Bit
timing waveforms and Figure 51 for a flowchart.
There is no provision to abort an Erase, Program, or Write
operation, once initiated. For the SST SuperFlash technology, the associated Erase, Program, and Write times are
so fast, relative to system reset times, there is no value in
aborting the operation. Note, reads can always occur from
any bank not performing an Erase, Program, or Write operation.
Data Protection
The SST38VF166 provides both hardware and software
features to protect nonvolatile data from inadvertent writes.
Should the system reset, while a Block- or Sector-Erase or
Word-Program is in progress in the bank where the boot
code is stored, the system must wait for the completion of
the operation before reading that bank. Since the maximum time the system would have to wait is 25 ms (for a
Block-Erase), the system ability to read the boot code
would not be affected.
Hardware Data Protection
Noise/Glitch Protection: A WE# pulse of less than 5 ns will
not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5 volts.
Data# Polling (DQ7) - Flash Bank
Write Inhibit Mode: Forcing OE# low, BE#1 and BE#2 high,
or WE# high will inhibit the Write operation to the Flash
bank. Forcing OE# low, BE#3 high, or WE# high will inhibit
the Write operation to the E2 bank. This prevents inadvertent writes during power-up or power-down.
When the SST38VF166 is in the internal Flash bank Program cycle, any attempt to read DQ7 of the last word
loaded during the Flash bank Word Load cycle will receive
the complement of the true data. Once the Write cycle is
completed, DQ7 will show true data. The device is then
ready for the next operation. See Figure 21 or 22 for the
Flash bank Data Polling timing waveforms and Figure 51
for a flowchart.
A One Time Programmable E2 Sector
The first sector of the E2 bank offers the option of OTP
(One Time Programmable) prevention of write for the first
sector, i.e., addresses A5 to A13 are “0” (0000H to 001FH).
Once the OTP software instruction is executed, no Write,
Erase, or Program operation can be performed on these 32
words. This is permanent and non-reversible. Additionally, if
the OTP prevention is enabled, the Bank-Erase for the E2
bank will not function. See Table 7 for specific codes and
Figure 39 for a timing waveform.
Data# Polling (DQ7) - E2 Bank
When the SST38VF166 is in the internal E2 bank Write
cycle, any attempt to read DQ7 of the last word loaded during the E2 bank Word Load cycle will receive the complement of the true data. Once the Write cycle is completed,
DQ7 will show true data. The device is then ready for the
next operation. See Figure 23 for E2 bank Data Polling timing waveforms and Figure 51 for a flowchart.
Software Data Protection (SDP)
The SST38VF166 provides the JEDEC approved Software
Data Protection scheme as a requirement for initiating a
Write, Erase, or Program operation. With this scheme, any
Write operation requires the inclusion of a series of three
word-load operations to precede the Word-Write or WordProgram operation. The three-word load sequence is used
to initiate the Write or Program cycle, providing optimal protection from inadvertent Write operations, e.g., during the
system power-up or power-down. The six-word sequence
is required to initiate any Bank-, Block-, or Sector-Erase
operation.
Toggle Bit (DQ6) - Flash Bank
During the Flash bank internal Write cycle, any consecutive
attempts to read DQ6 will produce alternating 0s and 1s,
i.e. toggling between 0 and 1. When the Write cycle is completed, the toggling will stop. The device is then ready for
the next operation. See Figure 24 or 25 for Flash bank Toggle Bit timing waveforms and Figure 51 for a flowchart.
©2001 Silicon Storage Technology, Inc.
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Product Identification
The requirements for JEDEC compliant SDP are in byte
format. The SST38VF166 is organized by word; therefore,
the contents of DQ8 to DQ15 are “Don’t Care” during any
SDP (3-word or 6-word) command sequence.
The product identification mode identifies the device manufacturer as SST and provides a code to identify each bank.
The manufacturer ID is the same for each bank; however,
each bank has a separate device ID. Each bank is individually accessed using the applicable BE# and a software
command. Users may wish to use the device ID operation
to identify the write algorithm requirements for each bank.
For details, see Table 6 or 7 for software operation and Figures 27, 28, or 29 for timing waveforms.
During the SDP load command sequence, the SDP load
cycle is suspended when WE# is high. This means a read
may occur to any other bank during the SDP load
sequence.
The SDP load sequence is bank specific, i.e., the same
BE# must be low for each bus cycle. If the command
sequence is aborted, e.g., a different BE# is brought low
(except for Read operation with WE# high), an incorrect
address is loaded, or incorrect data is loaded, the device
will return to the Read mode within TRC of execution of the
load error.
TABLE
Address
Data
0000H
00BFH
Flash Bank 1
0001H
2791H
Flash Bank 2
0001H
2792H
E2 Bank
0001H
2793H
Manufacturer’s ID
Device ID
Concurrent Read and Write Operations
The SST38VF166 provides the unique benefit of being
able to read any bank, while simultaneously writing, erasing, or programming one other bank. This allows data alteration code to be executed from one bank, while altering the
data in another bank. The following table lists all valid
states.
TABLE
2: PRODUCT IDENTIFICATION
T2.1 327
Device IDs are unique to each bank. Should a chip ID be
required, any of the bank IDs may be used as the chip ID.
While in the read software ID mode or CFI mode, no other
operation is allowed until after exiting these modes.
1: CONCURRENT READ/W RITE S TATE
Flash Bank 1
Flash Bank 2
E2 Bank
Read
No Operation
Write
Read
Write
No Operation
Write
Read
No Operation
No Operation
Read
Write
Write
No Operation
Read
No Operation
Write
Read
Product Identification Mode Exit
In order to return to the standard Read mode, the Product
Identification mode must be exited. Exit is accomplished by
issuing the Software ID exit command, which returns the
device to normal operation. This command may also be
used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the
device to behave abnormally, e.g., not read correctly. For
details, see Table 6 or 7 for software operation and Figures
30, 31, or 32 for timing waveforms.
T1.0 327
Note: For the purposes of this table, write means to Word-Write;
Block-, Sector-, or Chip-Erase; or Word-Program as applicable to the appropriate bank.
SST does not recommend that any two of the bank enable
signals BE#1, BE#2 or BE#3 be simultaneously asserted.
The device will ignore all SDP commands and toggling of
WE# when an Erase, Program, or Write operation is in
progress. Note, both Product Identification and the Common Flash Interface entry commands use SDP; therefore,
these commands will also be ignored while an Erase, Program, or Write operation is in progress.
©2001 Silicon Storage Technology, Inc.
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Common Flash Interface (CFI)
CFI Mode Exit
The SST38VF166 also contains the CFI information in
each bank, to describe the characteristics of that bank. See
Tables 8 through 16 for the CFI contents for each bank.
Both flash banks use the same information, as each bank
operates the same. The E2 bank contains the applicable
information for that bank.
In order to return to the standard Read mode, the CFI
mode must be exited. Exit is accomplished by issuing the
CFI exit command, which returns the device to normal
operation. This command may also be used to reset the
device to the Read mode after any inadvertent transient
condition that apparently causes the device to behave
abnormally, e.g., not read correctly. For details, see Table 6
or 7 for software operation and Figures 36, 37, or 38 for timing waveforms.
In order to obtain the CFI information, the CFI memory
space is accessed by using the CFI entry command. For
details, see Table 6 or 7 for software operation and Figures
33, 34, or 35 for timing waveforms.
CFI is specified for byte wide information. Since the
SST38VF166 is organized word wide, the first byte (2 nibbles) of each CFI word is always 00H.
FUNCTIONAL B LOCK DIAGRAM
Charge
Pump &
Vref.
Y - Decoder
4K x 16
E2 Bank
X - Decoder
Address Buffer
and Latches
512K x 16
Flash
Bank 1
512K x 16
Flash
Bank 2
A18 - A0
OE#
BE#1
BE#2
BE#3
WE#
I/O Buffers and
Data Latches
Control Logic
DQ15 - DQ0
327 ILL F02.1
©2001 Silicon Storage Technology, Inc.
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
BE#2
NC
BE#3
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard Pinout
Top View
Die Up
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
BE#1
A0
327 ILL F01b.5
FIGURE 1: P IN ASSIGNMENTS FOR 48-PIN TSOP (12MM X 20MM)
TABLE
3: PIN D ESCRIPTION
Symbol
Name
Functions
A18-A0
Flash Bank Addresses
To provide Flash Bank addresses
A11-A0
E2 Bank Addresses
To provide E2 Bank addresses
A18-A15
Flash Bank Block Addresses
To select a Flash Bank Block for erase
A18-A10
Flash Bank Sector Addresses To select a Flash Bank Sector for erase
A11-A5
E2 Bank Sector Addresses
DQ15-DQ 0 Data Input/output
To select an E2 Bank Sector for erase
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a Write cycle.
The outputs are in tri-state when OE# is high or BE#1, BE#2, and BE#3 are high.
OE#
Output Enable
To gate the data output buffers
WE#
Write Enable 1
To control the Write, Erase, or Program operations
To provide 2.7-3.6V power supply
VDD
Power Supply
VSS
Ground
NC
No Connect
Unconnected pins
T3.4 327
©2001 Silicon Storage Technology, Inc.
327-3 2/01
8
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TABLE
4: OPERATION MODES S ELECTION FOR FLASH B ANK
Array Operation Mode
BE#1
BE#2
BE#3
OE#
WE#
DQ
Address
Flash Bank 1
VIL
VIH
VIH
VIL
Flash Bank 2
VIH
VIL
VIH
VIL
VIH
DOUT
AIN
VIH
DOUT
AIN
Flash Bank 1
VIL
VIH
VIH
VIH
VIL
DIN
See Tables 6 and 7
Flash Bank 2
VIH
VIL
VIH
VIH
VIL
DIN
See Tables 6 and 7
Flash Bank 1
VIL
Flash Bank 2
VIH
VIH
VIH
VIH
VIL
DIN
See Tables 6 and 7
VIL
VIH
VIH
VIL
DIN
See Tables 6 and 7
Flash Bank 1
VIL
VIH
VIH
VIH
VIL
DIN
See Tables 6 and 7
Flash Bank 2
VIH
VIL
VIH
VIH
VIL
VIH
VIH
VIH
X
X
Flash Bank 1
VIH
X
X
VIL
Flash Bank 2
X
VIH
X
Flash Bank 1
VIL
VIH
Flash Bank 2
VIH
VIL
BE#1
BE#2
Read
Block-Erase
Sector-Erase
Program
Standby
DIN
See Tables 6 and 7
High Z
X
VIH
X
X
VIL
VIH
X
X
VIH
VIH
VIL
DIN
See Tables 6 and 7
VIH
VIH
VIL
DIN
See Tables 6 and 7
BE#3
OE#
WE#
DQ
Address
Write Inhibit
Flash Bank-Erase
Status Operation Mode
Write Status Read
VIH
VIH
VIL
VIL
VIH
DOUT1
Illegal State
VIL
VIL
VIL
X
X
High Z
X2
Illegal State
VIL
VIL
X
X
X
High Z
X2
Illegal State
VIL
X
VIL
X
X
High Z
X2
Illegal State
X
VIL
VIL
X
X
High Z
X2
Flash Bank 1
VIL
VIH
VIH
VIL
VIH
DOUT
See Tables 6 and 7
Flash Bank 2
VIH
VIL
VIH
VIL
VIH
DOUT
See Tables 6 and 7
Flash Bank 1
VIL
VIH
VIH
VIL
VIH
DOUT
See Tables 6 and 7
Flash Bank 2
VIH
VIL
VIH
VIL
VIH
DOUT
See Tables 6 and 7
5XXXXH
Product Identification
Common Flash Interface
T4.5 327
1. If Flash Bank 1 is writing, DQ1 is low. If Flash Bank 2 is writing, DQ2 is low. If E2 Bank is writing, DQ3 is low.
2. Entering an illegal state during an Erase, Program, or Write operation will not affect the operation, i.e., the erase, program, or write
will continue to normal completion.
©2001 Silicon Storage Technology, Inc.
327-3 2/01
9
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TABLE
5: OPERATION MODES S ELECTION FOR E2 BANK
Read Operation Mode
BE#1
BE#2
BE#3
OE#
WE#
DQ
Address
Bank
VIH
VIH
VIL
VIL
VIH
DOUT1
Write E2 Bank
VIH
VIH
VIL
VIH
VIL
DIN
See Tables 6 and 7
Read
E2
E2
VIH
VIH
VIL
VIH
VIL
DIN
See Tables 6 and 7
Program E2 Bank
VIH
VIH
VIL
VIH
VIL
DIN
See Tables 6 and 7
Standby
VIH
VIH
VIH
X
X
DIN
See Tables 6 and 7
X
X
VIH
VIL
VIH
High Z
X
Erase E2 Bank
VIH
VIH
VIL
VIH
VIL
DIN
See Tables 6 and 7
OTP Enable E2 Bank
VIH
VIH
VIL
VIH
VIL
DIN
See Tables 6 and 7
Sector-Erase
Bank
Write Inhibit E2 Bank
Status Operation Mode
BE#1
BE#2
BE#3
OE#
WE#
DQ
Address
Write Status Read
VIH
VIH
VIL
VIL
VIH
DOUT2
5XXXXH
Illegal State
VIL
VIL
VIL
X
X
High Z
X3
Illegal State
VIL
VIL
X
X
X
High Z
X3
Illegal State
VIL
X
VIL
X
X
High Z
X3
Illegal State
X
VIL
VIL
X
X
High Z
X3
VIH
VIH
VIL
VIL
VIH
DOUT
See Tables 6 and 7
VIH
VIH
VIL
VIL
VIH
DOUT
See Tables 6 and 7
Product Identification
E2 Bank
Common Flash Interface
E2 Bank
T5.6 327
1. A11-A0 are valid addresses; A15-A12 are “Don’t Care”; A 18-A16 cannot be 5H
2. If Flash Bank 1 is writing, DQ1 is low. If Flash Bank 2 is writing, DQ2 is low. If E2 Bank is writing, DQ3 is low.
3. Entering an illegal state during an Erase, Program, or Write operation will not affect the operation, i.e., the erase, program, or write
will continue to normal completion.
©2001 Silicon Storage Technology, Inc.
327-3 2/01
10
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TABLE
6: SOFTWARE C OMMAND SEQUENCE FOR FLASH BANKS
Command Code
1st Bus Cycle
2nd Bus Cycle
3rd Bus Cycle
4th Bus Cycle
5th Bus Cycle
6th Bus Cycle
Addr1
Addr1
Addr1
Data2
Addr1
Addr1
Data2
Addr1
Data2
Data2
Data2
Data2
Software ID Entry
5555H
AAH
2AAAH
55H
5555H
90H
3
Software ID Exit
5555H
AAH
2AAAH
55H
5555H
F0H
4
Flash Bank
Word-Program
5555H
AAH
2AAAH
55H
5555H
A0H
WA 5
Data
In
Flash Bank
Sector-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
SA6
30H
Flash Bank
Block-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
BA6
50H
Flash Bank
Bank-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
CFI Entry
5555H
AAH
2AAAH
55H
5555H
98H
7
CFI Exit
5555H
AAH
2AAAH
55H
5555H
F0H
4
T6.4 327
1. Command Code Address format A14-A0 (Hex), Addresses > A 14 are “Don’t Care” for Command sequences
2. Data format DQ7 -DQ0 (Hex), DQ15 - DQ8 are “Don’t Care”
3. With A14-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0
SST38VF166 Device ID = 2791H, 2792H, and 2793H is read with A0 = 1 for the applicable BE# active
4. The device does not remain in Software Product ID Mode or CFI Mode if powered down.
5. WA = Word address
6. SA = Sector address
BA = Block address
7. There is a separate CFI for each bank. See Tables 8 through 16
TABLE
7: SOFTWARE C OMMAND SEQUENCE FOR E2 B ANKS
Command Code
1st Bus Cycle
2nd Bus Cycle
3rd Bus Cycle
4th Bus Cycle
5th Bus Cycle
6th Bus Cycle
Addr1
Addr1
Addr1
Data2
Addr1
Addr1
Data2
Addr1
Data2
Data2
Data2
Data2
Software ID Entry
5555H
AAH
2AAAH
55H
5555H
90H
3
Software ID Exit
5555H
AAH
2AAAH
55H
5555H
F0H
4
E2
Bank
Word-Write
5555H
AAH
2AAAH
55H
5555H
A0H
WA 5
Data
In
E2 Bank
Word-Program
5555H
AAH
2AAAH
55H
5555H
A5H
WA 5
Data
In
E2 Bank
Sector-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
SA6
30H
E2 Bank
Bank-Erase
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
10H
E2 Bank
OTP Enable
5555H
AAH
2AAAH
55H
5555H
80H
5555H
AAH
2AAAH
55H
5555H
70H
CFI Entry
5555H
AAH
2AAAH
55H
5555H
98H
7
CFI Exit
5555H
AAH
2AAAH
55H
5555H
F0H
4
T7.4 327
1. Command Code Address format A14-A0 (Hex), Addresses > A 14 are “Don’t Care” for Command sequences
2. Data format DQ7 -DQ0 (Hex), DQ15 - DQ8 are “Don’t Care”
3. With A14-A1 = 0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0
SST38VF166 Device ID = 2791H, 2792H, and 2793H is read with A0 = 1 for the applicable BE# active
4. The device does not remain in Software Product ID Mode or CFI Mode if powered down.
5. WA = Word address
6. SA = Sector address
7. There is a separate CFI for each bank. See Tables 8 through 16
©2001 Silicon Storage Technology, Inc.
327-3 2/01
11
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TABLE
8: CFI QUERY IDENTIFICATION S TRING FOR FLASH B ANK 1
Address
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Data
0051H
0052H
0059H
0001H
0008H
0000H
0000H
0000H
0000H
0000H
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set (JEP-137)
Address for Primary Extended Table (00H = none exists)
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T8.2 327
TABLE
9: SYSTEM INTERFACE INFORMATION FOR FLASH BANK 1
Address
Data
1BH
0027H
Data
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
0036H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
0000H
VPP min. (00H = no V PP pin)
1EH
0000H
VPP max. (00H = no VPP pin)
1FH
0004H
Typical time out for Word-Program 2N µs
20H
0000H
Typical time out for min. size Page-Write 2N µs (00H = not supported)
21H
0004H
Typical time out for individual Sector-Erase 2N ms
22H
0006H
Typical time out for Bank-Erase 2N ms
23H
0001H
Maximum time out for Word-Program 2N times typical
24H
0000H
Maximum time out for Page-Write 2N times typical (00H = not supported)
25H
0001H
Maximum time out for individual Sector-Erase 2N times typical
26H
0001H
Maximum time out for Chip-Erase 2N times typical
T9.7 327
TABLE 10: DEVICE GEOMETRY INFORMATION FOR FLASH BANK 1
Address
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Data
0014H
0001H
0000H
0000H
0000H
0002H
00FFH
0001H
0008H
0000H
000FH
0000H
0000H
0001H
Data
Bank size = 2N Byte (14H > 220 = 1 MByte = 8 Mbits)
Flash Bank Device Interface description (Refer to CFI JESD-68) (x16 asynchronous)
Maximum number of bytes in Page-Write = 2N (00H = not supported)
Number of Erase Block Regions within device
Erase Block Region 1 Information (Sector)
(Refer to the CFI specification or JESD-68)
y = 511 + 1 = 512 sectors (01FFH = 511)
z = 2 KBytes/sector = 8 x 256 Bytes
Erase Block Region 2 Information (Block)
(Refer to the CFI specification or JESD-68)
y = 15 + 1 = 16 blocks
z = 64 KBytes/block = 256 x 256 Bytes (0100H = 64K)
T10.5 327
©2001 Silicon Storage Technology, Inc.
327-3 2/01
12
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TABLE 11: CFI QUERY IDENTIFICATION S TRING FOR FLASH B ANK 2
Address
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Data
0051H
0052H
0059H
0001H
0008H
0000H
0000H
0000H
0000H
0000H
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set (JEP-137)
Address for Primary Extended Table (00H = none exists)
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T11.2 327
TABLE 12: SYSTEM INTERFACE INFORMATION FOR FLASH BANK 2
Address
Data
1BH
0027H
Data
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1CH
0036H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
0000H
VPP min. (00H = no V PP pin)
1EH
0000H
VPP max. (00H = no VPP pin)
1FH
0004H
Typical time out for Word-Program 2N µs
20H
0000H
Typical time out for min. size Page-Write 2N µs (00H = not supported)
21H
0004H
Typical time out for individual Sector-Erase 2N ms
22H
0006H
Typical time out for Bank-Erase 2N ms
23H
0001H
Maximum time out for Word-Program 2N times typical
24H
0000H
Maximum time out for Page-Write 2N times typical (00H = not supported)
25H
0001H
Maximum time out for individual Sector-Erase 2N times typical
26H
0001H
Maximum time out for Chip-Erase 2N times typical
T12.8 327
TABLE 13: DEVICE GEOMETRY INFORMATION FOR FLASH BANK 2
Address
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
Data
0014H
0001H
0000H
0000H
0000H
0002H
00FFH
0001H
0008H
0000H
000FH
0000H
0000H
0001H
Data
Bank size = 2N Byte (14H > 220 = 1 MByte = 8 Mbits)
Flash Bank Device Interface description (Refer to CFI JESD-68) (x16 asynchronous)
Maximum number of bytes in Page-Write = 2N (00H = not supported)
Number of Erase Block Regions within device
Erase Block Region 1 Information (Sector)
(Refer to the CFI specification or JESD-68)
y = 511 + 1 = 512 sectors (01FFH = 511)
z = 2 KBytes/sector = 8 x 256 Bytes
Erase Block Region 2 Information (Block)
(Refer to the CFI specification or JESD-68)
y = 15 + 1 = 16 blocks
z = 64 KBytes/block = 256 x 256 Bytes (0100H = 64K)
T13.5 327
©2001 Silicon Storage Technology, Inc.
327-3 2/01
13
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TABLE 14: CFI QUERY IDENTIFICATION S TRING FOR E2 BANK
Address
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
Data
0051H
0052H
0059H
0001H
0009H
0000H
0000H
0000H
0000H
0000H
0000H
Data
Query Unique ASCII string “QRY”
Primary OEM command set (JEP-137)
Address for Primary Extended Table (00H = none exists)
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T14.1 327
TABLE 15: SYSTEM INTERFACE INFORMATION FOR E2 B ANK
Address
Data
1BH
0027H
1CH
0036H
Data
VDD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
0000H
VPP min. (00H = no V PP pin)
1EH
0000H
VPP max. (00H = no VPP pin)
1FH
0005H
Typical time out for Word-Program 2N µs
20H
0000H
Typical time out for min. size Page-Write 2N µs (00H = not supported)
21H
0003H
Typical time out for individual Sector-Erase 2N ms
22H
0006H
Typical time out for Bank-Erase 2N ms
23H
0001H
Maximum time out for Word-Program 2N times typical
24H
0000H
Maximum time out for Page-Write 2N times typical (00H = not supported)
25H
0001H
Maximum time out for individual Sector-Erase 2N times typical
26H
0001H
Maximum time out for Chip-Erase 2N times typical
T15.7 327
TABLE 16: DEVICE GEOMETRY INFORMATION FOR E2 B ANK
Address
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
Data
000DH
0001H
0000H
0001H
0000H
0001H
007FH
0000H
0001H
0000H
Data
Device size = 2N Byte (DH > 213 = 8 KBytes = 64 Kbits)
Flash Bank Device Interface description (Refer to CFI JESD-68) (x16 asynchronous)
Maximum number of bytes in Page-Write = 2N (00H = not supported)
Number of Erase Block Regions within device
Erase Block Region 1 Information (Sector)
(Refer to the CFI specification or JESD-68)
y = 127 + 1 = 128 sectors (007FH = 127)
z = 32 Bytes/sector = 1 x 256 Bytes
T16.4 327
©2001 Silicon Storage Technology, Inc.
327-3 2/01
14
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING R ANGE:
Range
Commercial
AC C ONDITIONS OF TEST
Ambient Temp
VDD
0°C to +70°C
2.7-3.6V
Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 42 and 43
TABLE 17: DC OPERATING C HARACTERISTICS VDD = 2.7-3.6V
Limits
Symbol
Parameter
IDD
Power Supply Current
Min
Max
Units
Test Conditions
Address input = VIL/VIH, at f=1/TRC Min
VDD=VDD Max
Read
35
mA
BE#1,BE#2, or BE#3=VIL, WE#=VIH,
all I/Os open
Write: Flash Bank
40
mA
BE#1/2=WE#=VIL, OE#=VIH
VDD=VDD Max or E2 Bank
BE#3=WE#=VIL, OE#=VIH
VDD=VDD Max
Read: Flash Bank plus
Write/Program/Erase:
E2 Bank or Flash Bank
75
mA
Address input = VIL/VIH, at f=1/TRC Min
WE#=VIH, VDD=VDD Max
BE#1,BE#2, or BE#3=VIL, OE#=WE#=VIH,
ISB
Standby VDD Current
(CMOS inputs)
50
µA
BE#1,BE#2, or BE#3=VIHC,
VDD = VDD Max
IALP
Auto Low Power Mode
(CMOS inputs)
50
µA
BE#1,BE#2, or BE#3=VILC, WE#= VIHC,
all I/Os open, Address input = VIHC/VIHC
and static VDD=V DD Max
ILI
Input Leakage Current
1
µA
VIN =GND to VDD, VDD = VDD Max
ILO
Output Leakage Current
VIL
Input Low Voltage
VILC
Input Low Voltage (CMOS)
VIH
Input High Voltage
0.7VDD
VIHC
Input High Voltage (CMOS)
VDD-0.2
VOL
Output Low Voltage
VOH
Output High Voltage
1
µA
VOUT =GND to VDD, VDD = VDD Max
0.3VDD
V
VDD = VDD Min
0.2
V
V
0.2
VDD-0.2
VDD = VDD Max
V
VDD = VDD Max
V
IOL = 100 µA, V DD = VDD Min
V
IOH = -100 µA, VDD = VDD Min
T17.1 327
©2001 Silicon Storage Technology, Inc.
327-3 2/01
15
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TABLE 18: RECOMMENDED SYSTEM POWER- UP TIMINGS
Symbol
Parameter
Minimum
Units
TPU-READ1
Power-up to Read Operation
100
µs
TPU-WRITE1
Power-up to Write Operation
100
µs
T18.1 327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 19: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
CI/O1
CIN1
Test Condition
Maximum
I/O Pin Capacitance
VI/O = 0V
12 pF
Input Capacitance
VIN = 0V
6 pF
T19.1 327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 20: RELIABILITY CHARACTERISTICS
Symbol
Parameter
NEND1
Minimum Specification
Units
Endurance - Flash Bank
Endurance - E2 Bank
TDR1
VZAP_HBM1
Test Method
10,000
100,000
Cycles/Sector
Cycles/Word
Data Retention
100
Years
JEDEC Standard A103
ESD Susceptibility
Human Body Model
2000
Volts
JEDEC Standard A114
VZAP_MM1
ESD Susceptibility
Machine Model
200
Volts
JEDEC Standard A115
ILTH1
Latch Up
100 + IDD
mA
JEDEC Standard A117
JEDEC Standard 78
T20.0 327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
327-3 2/01
16
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
AC CHARACTERISTICS
TABLE 21: READ C YCLE TIMING PARAMETERS
SST38VF166-70
Symbol
Parameter
TRC
Read Cycle Time
Min
Max
Units
TBE
Bank Enable Access Time
70
ns
TAA
Address Access Time
70
ns
TOE
Output Enable Access Time
30
ns
TCLZ1
CE# Low to Active Output
0
TOLZ1
TCHZ1
TOHZ1
TOH1
OE# Low to Active Output
0
70
ns
ns
ns
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
20
ns
20
ns
0
ns
T21.1 327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 22: W RITE, ERASE, P ROGRAM C YCLE TIMING PARAMETERS
Symbol
Parameter
TWC
Word-Write Cycle (Erase and Program)
Min
E2
Bank
Max
Units
12.5
ms
TBPE
Word-Program Time -
TBPF
Word-Program Time - Flash Bank
40
µs
20
µs
TSEF
Sector-Erase Time - Flash Bank
25
ms
TLEF
Block-Erase Time - Flash Bank
25
ms
TBEF
Bank-Erase Time - Flash Bank
100
ms
TSEE
Sector-Erase Time - E2 Bank
12.5
ms
TBEE
Bank-Erase Time - E2 Bank
100
ms
TAS
Address Setup Time
0
TAH
Address Hold Time
40
ns
TBES
BE# Setup Time
0
ns
TBEH
BE# Hold Time
0
ns
TOES
OE# High Setup Time
0
ns
TOEH
OE# High Hold Time
0
ns
TWP
Write Pulse Low Width
40
ns
TWPH
Write Pulse High Time
30
ns
TDS
Data Setup Time
40
ns
TDH
Data Hold Time
0
TVDDR1
VDD Rise Time
0.1
TDBR
Time to DATA# Polling Read
35
ns
TTBR
Time to Toggle Bit Read
35
ns
TIDA
Time to ID or CFI Read/Exit Cycle
TBS
Bank Enable Setup Time for Concurrent Operation
ns
ns
50
ms
150
ns
0
ns
T22.0 327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
327-3 2/01
17
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TIMING DIAGRAMS
Address and data format are in hexadecimal
TAA
TRC
ADDRESS A18-0
TBE
BE#1
TOE
OE#
VIH
TOHZ
TOLZ
BE#2, BE#3, WE#
DQ15-0
HIGH-Z
TCHZ
TOH
TCLZ
HIGH-Z
DATA VALID
DATA VALID
327 ILL F03a.2
FIGURE 2: FLASH BANK 1, READ C YCLE TIMING DIAGRAM
TAA
TRC
ADDRESS A18-0
TBE
BE#2
TOE
OE#
VIH
TOHZ
TOLZ
BE#1 , BE#3, WE#
DQ15-0
HIGH-Z
TOH
TCLZ
DATA VALID
TCHZ
HIGH-Z
DATA VALID
327 ILL F03b.2
FIGURE 3: FLASH BANK 2, READ C YCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
327-3 2/01
18
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TAA
TRC
ADDRESS A11-0
TBE
BE#3
TOE
OE#
TOHZ
TOLZ
VIH
BE#1 , BE#2, WE#
HIGH-Z
DQ15-0
TCHZ
TOH
TCLZ
DATA VALID
HIGH-Z
DATA VALID
327 ILL F03c.2
FIGURE 4: E 2 B ANK, R EAD C YCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
TBPF
5555
TAH
ADDRESS A18-0
2AAA
5555
ADDR
TDH
TWP
WE#
TAS
TDS
TWPH
BE#2, BE#3, OE#
TBEH
BE#1
TBES
DQ150
AA
SW0
55
SW1
A0
SW2
DATA
WORD
(ADDR/DATA)
327 ILL F04a1.3
FIGURE 5: FLASH BANK 1, WE# CONTROLLED WORD-PROGRAM CYCLE TIMING D IAGRAM
©2001 Silicon Storage Technology, Inc.
327-3 2/01
19
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
TBPF
5555
TAH
ADDRESS A18-0
2AAA
5555
ADDR
TDH
TWP
BE#1
TAS
TDS
TWPH
BE#2, BE#3, OE#
TWEH
WE#1
TWES
DQ150
AA
SW0
55
A0
SW1
SW2
DATA
WORD
(ADDR/DATA)
327 ILL F04a2.3
FIGURE 6: FLASH BANK 1, BE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
TBPF
5555
TAH
ADDRESS A18-0
2AAA
5555
ADDR
TDH
TWP
WE#
TAS
TDS
TWPH
BE#1, BE#3, OE#
TBEH
BE#2
TBES
DQ15-0
AA
SW0
55
SW1
A0
SW2
DATA
WORD
(ADDR/DATA)
327 ILL F04b1.3
FIGURE 7: FLASH BANK 2, WE# CONTROLLED WORD-PROGRAM CYCLE TIMING D IAGRAM
©2001 Silicon Storage Technology, Inc.
327-3 2/01
20
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
TBPF
5555
TAH
ADDRESS A18-0
2AAA
5555
ADDR
TDH
TWP
BE#2
TAS
TDS
TWPH
BE#1, BE#3, OE#
TWEH
WE#
TWES
DQ15-0
AA
SW0
55
SW1
A0
SW2
DATA
WORD
(ADDR/DATA)
327 ILL F04b2.3
FIGURE 8: FLASH BANK 2, BE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
TWC
5555
TAH
ADDRESS A14-0
2AAA
5555
ADDR
TDH
TWP
WE#
TAS
TDS
TWPH
BE#1, BE#2, OE#
TBEH
BE#3
TBES
DQ15-0
AA
SW0
55
SW1
A0
SW2
DATA
WORD
(ADDR/DATA)
327 ILL F04c1.3
FIGURE 9: E 2 B ANK, WE# CONTROLLED WORD-W RITE CYCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
327-3 2/01
21
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
TWC
5555
TAH
ADDRESS A14-0
2AAA
5555
ADDR
TDH
TWP
BE#3
TAS
TDS
TWPH
BE#1, BE#2, OE#
TWEH
WE#
TWES
DQ15-0
AA
SW0
55
A0
SW1
SW2
DATA
WORD
(ADDR/DATA)
327 ILL F04c2.3
FIGURE 10: E 2 B ANK, BE# C ONTROLLED WORD-W RITE C YCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
TBPE
5555
TAH
ADDRESS A14-0
2AAA
5555
ADDR
TDH
TWP
WE#
TAS
TDS
TWPH
BE#1, BE#2, OE#
TBEH
BE#3
TBES
DQ15-0
AA
SW0
55
SW1
A5
SW2
DATA
WORD
(ADDR/DATA)
327 ILL F04d1.3
FIGURE 11: E 2 B ANK, WE# CONTROLLED WORD-P ROGRAM CYCLE TIMING D IAGRAM
©2001 Silicon Storage Technology, Inc.
327-3 2/01
22
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
TBPE
5555
TAH
ADDRESS A14-0
2AAA
5555
ADDR
TDH
TWP
BE#3
TAS
TDS
TWPH
BE#1, BE#2, OE#
TWEH
WE#
TWES
DQ15-0
AA
SW0
55
A5
SW1
SW2
DATA
WORD
(ADDR/DATA)
326 ILL F04d 2.3
FIGURE 12: E 2 B ANK, BE# C ONTROLLED WORD-PROGRAM CYCLE TIMING D IAGRAM
TBEF
SIX-BYTE CODE FOR BANK-ERASE
ADDRESS A18-0
5555
2AAA
5555
5555
2AAA
5555
TAH
TAS
BE#1
BE#2, BE#3, OE#
TDS
TWPH
TWP
TDH
WE#
DQ15-0
AA
55
80
AA
55
10
SW0
SW1
SW2
SW3
SW4
SW5
327 ILL F05a1.2
FIGURE 13: FLASH BANK 1, BANK-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
327-3 2/01
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TLEF
SIX-BYTE CODE FOR BLOCK-ERASE
ADDRESS A18-0
5555
2AAA
5555
5555
2AAA
BAX
TAH
TAS
BE#1
BE#2, BE#3, OE#
TDS
TWPH
TWP
TDH
WE#
DQ15-0
AA
55
80
AA
55
SW0
SW1
SW2
SW3
SW4
50
SW5
327 ILL F05a2.3
FIGURE 14: FLASH BANK 1, BLOCK-ERASE TIMING DIAGRAM
TSEF
SIX-BYTE CODE FOR SECTOR-ERASE
ADDRESS A18-0
5555
2AAA
5555
5555
2AAA
SAX
TAH
TAS
BE#1
BE#2, BE#3, OE#
TDS
TWPH
TWP
TDH
WE#
DQ15-0
AA
55
80
AA
55
SW0
SW1
SW2
SW3
SW4
30
SW5
327 ILL F05a3.3
FIGURE 15: FLASH BANK 1, SECTOR-E RASE TIMING D IAGRAM
©2001 Silicon Storage Technology, Inc.
327-3 2/01
24
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TBEF
SIX-BYTE CODE FOR BANK-ERASE
ADDRESS A18-0
5555
2AAA
5555
5555
2AAA
5555
TAH
TAS
BE#2
BE#1, BE#3, OE#
TDS
TWPH
TWP
TDH
WE#
DQ15-0
AA
55
80
AA
55
SW0
SW1
SW2
SW3
SW4
10
SW5
327 ILL F05b1.2
FIGURE 16: FLASH BANK 2, BANK-ERASE TIMING DIAGRAM
TLEF
SIX-BYTE CODE FOR BLOCK-ERASE
ADDRESS A18-0
5555
2AAA
5555
5555
2AAA
BAX
TAH
TAS
BE#2
BE#1, BE#3, OE#
TDS
TWPH
TWP
TDH
WE#
DQ15-0
AA
55
SW0
SW1
80
AA
55
SW2
SW3
SW4
50
SW5
327 ILL F05b2.4
FIGURE 17: FLASH BANK 2, BLOCK-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
327-3 2/01
25
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TS EF
SIX-BYTE CODE FOR SECTOR-ERASE
ADDRESS A18-0
5555
2AAA
5555
5555
2AAA
SAX
TAH
TAS
BE#2
BE#1, BE#3, OE#
TDS
TWPH
TWP
TDH
WE#
DQ15-0
AA
55
80
AA
55
SW0
SW1
SW2
SW3
SW4
30
SW5
327 ILL F05b3.3
FIGURE 18: FLASH BANK 2, SECTOR-E RASE TIMING D IAGRAM
TBEE
SIX-BYTE CODE FOR BANK-ERASE
ADDRESS A14-0
5555
2AAA
5555
5555
2AAA
5555
TAH
TAS
BE#3
BE#1, BE#2, OE#
TDS
TWPH
TWP
TDH
WE#
DQ15-0
AA
55
SW0
SW1
80
AA
55
SW2
SW3
SW4
10
SW5
327 ILL F05c1.2
FIGURE 19: E 2 B ANK, B ANK-E RASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
327-3 2/01
26
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TSEE
SIX-BYTE CODE FOR SECTOR-ERASE
ADDRESS A14-0
5555
2AAA
5555
5555
2AAA
SAX
TAH
TAS
BE#3
BE#1, BE#2, OE#
TDS
TWPH
TWP
TDH
WE#
DQ15-0
AA
55
80
AA
55
SW0
SW1
SW2
SW3
SW4
30
SW5
327 ILL F05c2.3
FIGURE 20: E 2 B ANK, SECTOR-E RASE TIMING D IAGRAM
ADDRESS A18-0
BE#2, BE#3
TBE
BE#1
TOES
TOEH
OE#
TOE
WE#
DQ7
Data
Data#
Data#
Data
326 ILL F06a.3
FIGURE 21: FLASH BANK 1, DATA# POLLING TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
327-3 2/01
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
ADDRESS A18-0
BE#1, BE#3
TBE
BE#2
TOES
TOEH
OE#
TOE
WE#
DQ7
Data
Data#
Data#
Data
327 ILL F06b.3
FIGURE 22: FLASH BANK 2, DATA# POLLING TIMING DIAGRAM
ADDRESS A14-0
BE#1, BE#2
TBE
BE#3
TOES
TOEH
OE#
TOE
WE#
DQ7
Data
Data#
Data#
Data
327 ILL F06c.3
FIGURE 23: E 2 B ANK, D ATA# POLLING TIMING D IAGRAM
©2001 Silicon Storage Technology, Inc.
327-3 2/01
28
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
ADDRESS A18-0
BE#2, BE#3
TBE
BE#1
TOEH
TOES
TOE
OE#
WE#
DQ6
TWO READ CYCLES
WITH SAME OUTPUTS
327 ILL F07a.3
FIGURE 24: FLASH BANK 1, TOGGLE BIT TIMING DIAGRAM
ADDRESS A18-0
BE#1, BE#3
TBE
BE#2
TOEH
TOES
TOE
OE#
WE#
DQ6
TWO READ CYCLES
WITH SAME OUTPUTS
327 ILL F07b.3
FIGURE 25: FLASH BANK 2, TOGGLE BIT TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
327-3 2/01
29
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
ADDRESS A14 -0
BE#1, BE#2
TBE
BE#3
TOES
TOE
TOEH
OE#
WE#
DQ6
TWO READ CYCLES
WITH SAME OUTPUTS
326 ILL F07c.3
FIGURE 26: E 2 B ANK, TOGGLE BIT TIMING DIAGRAM
Three-Byte Sequence for
Software ID Entry
ADDRESS A14-0
5555
2AAA
5555
0000
0001
BE#1
BE#2, BE#3
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
AA
55
90
SW0
SW1
SW2
00BF
2791
327 ILL F08a.5
FIGURE 27: FLASH BANK 1, SOFTWARE ID ENTRY AND R EAD
©2001 Silicon Storage Technology, Inc.
327-3 2/01
30
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Three-Byte Sequence for
Software ID Entry
ADDRESS A14-0
5555
2AAA
5555
0000
0001
BE#2
BE#1, BE#3
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
AA
55
90
SW0
SW1
SW2
00BF
2792
327 ILL F08b.5
FIGURE 28: FLASH BANK 2, SOFTWARE ID ENTRY AND R EAD
Three-Byte Sequence for
Software ID Entry
ADDRESS A14-0
5555
2AAA
5555
0000
0001
BE#3
BE#2, BE#3
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
TAA
AA
55
90
SW0
SW1
SW2
00BF
2793
327 ILL F08c.5
FIGURE 29: E 2 B ANK, SOFTWARE ID ENTRY AND READ
©2001 Silicon Storage Technology, Inc.
327-3 2/01
31
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Three-Byte Sequence for
Software ID Exit
ADDRESS A14-0
5555
2AAA
DQ15-0
5555
AA
55
F0
TIDA
BE#1
BE#2, BE#3, OE#
TWP
WE#
T WPH
SW0
SW1
327 ILL F09a.3
SW2
FIGURE 30: FLASH BANK 1, SOFTWARE ID EXIT
Three-Byte Sequence for
Software ID Exit
ADDRESS A14-0
DQ15-0
5555
2AAA
AA
5555
55
F0
TIDA
BE#1
BE#1 , BE#3, OE#
TWP
WE#
T WPH
SW0
SW1
SW2
327 ILL F09b.4
FIGURE 31: FLASH BANK 2, SOFTWARE ID EXIT
©2001 Silicon Storage Technology, Inc.
327-3 2/01
32
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Three-Byte Sequence for
Software ID Exit
ADDRESS A14 -0
5555
DQ15-0
2AAA
AA
5555
55
F0
TIDA
BE#1
BE#1 , BE#3, OE#
TWP
WE#
T WPH
SW0
SW1
SW2
327 ILL F09c.4
FIGURE 32: E 2 B ANK, SOFTWARE ID EXIT
Three-Byte Sequence for
CFI Entry
ADDRESS A14-0
5555
2AAA
5555
0010
0011
BE#1
BE#2, BE#3
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
AA
55
SW0
SW1
TAA
0051
98
0052
SW2
327 ILL F10a.2
FIGURE 33: FLASH BANK 1, CFI ENTRY AND READ
©2001 Silicon Storage Technology, Inc.
327-3 2/01
33
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Three-Byte Sequence for
CFI Entry
ADDRESS A14-0
5555
2AAA
5555
0010
0011
BE#2
BE#1, BE#3
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
AA
55
SW0
SW1
TAA
0051
98
0052
SW2
327 ILL F10b.3
FIGURE 34: FLASH BANK 2, CFI ENTRY AND READ
Three-Byte Sequence for
CFI Entry
ADDRESS A14-0
5555
2AAA
5555
0010
0011
BE#3
BE#2, BE#3
OE#
TIDA
TWP
WE#
TWPH
DQ15-0
AA
55
SW0
SW1
TAA
0051
98
0052
SW2
327 ILL F10c.3
FIGURE 35: E 2 B ANK, CFI E NTRY AND READ
©2001 Silicon Storage Technology, Inc.
327-3 2/01
34
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Three-Byte Sequence for
CFI Exit
ADDRESS A14-0
5555
2AAA
DQ15-0
AA
5555
55
F0
TIDA
BE#1
BE#2, BE#3, OE#
TWP
WE#
T WPH
SW0
SW1
327 ILL F11a.2
SW2
FIGURE 36: FLASH BANK 1, CFI EXIT
Three-Byte Sequence for
CFI Exit
ADDRESS A14-0
DQ15-0
5555
2AAA
AA
5555
55
F0
TIDA
BE#1
BE#1 , BE#3, OE#
TWP
WE#
T WPH
SW0
SW1
SW2
327 ILL F11b.3
FIGURE 37: FLASH BANK 2, CFI EXIT
©2001 Silicon Storage Technology, Inc.
327-3 2/01
35
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Three-Byte Sequence for
CFI Exit
ADDRESS A14 -0
DQ15-0
5555
2AAA
AA
5555
55
F0
TIDA
BE#1
BE#1 , BE#3, OE#
TWP
WE#
T WPH
SW0
SW1
SW2
327 ILL F11c.3
FIGURE 38: E 2 B ANK, CFI E XIT
TBPE
SIX-BYTE CODE FOR OTP ENABLE
ADDRESS A14 -0
5555
2AAA
5555
5555
2AAA
5555
TAH
TAS
BE#3
BE#1, BE#2, OE#
TDS
TWPH
TWP
TDH
WE#
DQ15-0
AA
55
80
AA
55
SW0
SW1
SW2
SW3
SW4
70
SW5
327 ILL F12.2
FIGURE 39: E 2 B ANK, OTP E NABLE
©2001 Silicon Storage Technology, Inc.
327-3 2/01
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
TRC
ADDRESS A18-0
5XXXX
TAA
TBE
BE#3
TOE
OE#
TOLZ
VIH
BE#1, BE#2, WE#
DQ15-0
TOH
TCLZ
HIGH-Z
DATA VALID
327 ILL F13.3
FIGURE 40: W RITE OPERATION STATUS R EAD
ADDRESS A18-0
BE#i
TBS
BE#i
WE#
OE#
DQ15-0
327 ILL F25.1
Note: i = 1, 2, 3
FIGURE 41: TIMING DIAGRAM TO A LTERNATE BETWEEN E ACH MEMORY B ANK
©2001 Silicon Storage Technology, Inc.
327-3 2/01
37
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
327 ILL F14.3
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <10 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 42: AC INPUT/OUTPUT R EFERENCE WAVEFORMS
TO TESTER
TO DUT
CL
327 ILL F15.3
FIGURE 43: A TEST LOAD E XAMPLE
©2001 Silicon Storage Technology, Inc.
327-3 2/01
38
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Memory Bank
Bank-Erase
Start
Software Data Protect
Bank-Erase
Command
Wait for End-of-Erase
(TBEE, TBEF, Data #
Polling, or Toggle Bit)
Bank-Erase Complete
327 ILL F16.3
FIGURE 44: B ANK-E RASE FLOWCHART
©2001 Silicon Storage Technology, Inc.
327-3 2/01
39
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Flash Bank
Block-Erase
Start
Software Data Protect
Block-Erase
Flash Bank Command
Set Block Address
Wait for End-of-Erase
(TLEF, Data #
Polling, or Toggle Bit)
Flash Bank
Block-Erase Complete
327 ILL F17.5
FIGURE 45: FLASH BANK BLOCK-E RASE FLOWCHART
©2001 Silicon Storage Technology, Inc.
327-3 2/01
40
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
E2 Bank
Sector-Erase
Start
Software Data Protect
Sector-Erase
Flash Bank Command
Set Sector Address
Wait for End-of-Erase
(TSEE, Data #
Polling, or Toggle Bit)
E2 Bank
Sector-Erase Complete
327 ILL F18.5
FIGURE 46: E 2 B ANK SECTOR-E RASE FLOWCHART
©2001 Silicon Storage Technology, Inc.
327-3 2/01
41
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Flash Bank
Sector-Erase
Start
Software Data Protect
Sector-Erase
Flash Bank Command
Set Sector Address
Wait for End-of-Erase
(TSEF, Data #
Polling, or Toggle Bit)
Flash Bank
Sector-Erase Complete
327 ILL F19.5
FIGURE 47: FLASH BANK SECTOR-ERASE FLOWCHART
©2001 Silicon Storage Technology, Inc.
327-3 2/01
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
E2 Bank
Word-Write
Start
Software Data Protect
Write
E2 Bank Command
Set Word Address
Load Word Data
Wait for End-of-Write
(TWC, Polling,
or Toggle Bit)
E2 Bank Word-Write
Complete
327 ILL F20.4
FIGURE 48: E 2 B ANK WORD-W RITE FLOWCHART
©2001 Silicon Storage Technology, Inc.
327-3 2/01
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Flash Bank
Word-Program
Start
Software Data Protect
Program
Flash Bank Command
Set Word Address
Load Word Data
Wait for End of Program
(TBPF, Data # Polling,
or Toggle Bit)
Flash Bank Word-Program
Complete
327 ILL F21.3
FIGURE 49: FLASH BANK WORD-P ROGRAM FLOWCHART
©2001 Silicon Storage Technology, Inc.
327-3 2/01
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
E2 Bank
Word-Program
Start
Software Data Protect
Program
E2 Bank Command
Set Word Address
Load Word Data
Wait for End of Program
(TBPE, Data # Polling,
or Toggle Bit)
E2 Bank Word-Program
Complete
327 ILL F22.3
FIGURE 50: E 2 B ANK WORD-PROGRAM FLOWCHART
©2001 Silicon Storage Technology, Inc.
327-3 2/01
45
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Internal
Timer
Toggle Bit
Data# Polling
Erase, Program,
or Write Operation
Initiated
Erase, Program,
or Write Operation
Initiated
Erase, Program,
or Write Operation
Initiated
Wait TWC, TBPE, TBPF,
TSEF, TLEF, TBEF,
TSEE or TBEE
Read a word from a bank,
block, sector, or word
selected
Read DQ7 of the last
address set (or any address
within selected bank,
block, sector for erase)
Erase, Program, or
Write Completed
Read the same
word again
No
Is DQ7 same
as bit loaded?
Yes
No
Is DQ6 the same?
Erase, Program, or
Write Completed
Erase, Program, or
Write Completed
327 ILL F23.1
FIGURE 51: E ND-OF-W RITE, ERASE, OR PROGRAM WAIT OPTIONS FLOWCHART
©2001 Silicon Storage Technology, Inc.
327-3 2/01
46
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Concurrent
Operation
Load SDP
Command
Sequence
Flash
Program/Erase or
E2 Write Initiated
Wait for
End-of-Write
Indication
Read
Another Bank
End
Wait
Flash Operation
Completed
End Concurrent
Operation
327 ILL F24.1
FIGURE 52: C ONCURRENT OPERATION FLOWCHART
©2001 Silicon Storage Technology, Inc.
327-3 2/01
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Device
Speed
SST38VF166
-
XXX
Suffix1
-
XX
Suffix2
-
XX
Package Modifier
K = 48 balls
Package Type
E = TSOP (12mm x 20mm)
Temperature Range
C = Commercial = 0°C to +70°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Voltage
V = 2.7-3.6V
SST38VF166 Valid combinations
SST38VF166-70-4C-EK
Example:
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to
confirm availability of valid combinations and to determine availability of new combinations.
©2001 Silicon Storage Technology, Inc.
327-3 2/01
48
S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
PACKAGING DIAGRAMS
1.05
0.95
Pin # 1 Identifier
.50
BSC
.270
.170
12.20
11.80
0.15
0.05
18.50
18.30
0.70
0.50
Note:
20.20
19.80
1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
48.TSOP-EK-ILL.5
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
48-P IN THIN SMALL OUTLINE PACKAGE (TSOP) 12 MM X 20MM
SST PACKAGE C ODE: EK
©2001 Silicon Storage Technology, Inc.
327-3 2/01
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S71065
16 Megabit FlashBank Memory
SST38VF166
Data Sheet
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com
©2001 Silicon Storage Technology, Inc.
327-3 2/01
50
S71065