Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C SST32HF324C32Mb Flash + 4Mb SRAM (x16) MCP ComboMemories Preliminary Specifications FEATURES: • ComboMemory organized as: – 2M x16 Flash + 256K x16 SRAM • Single 2.7-3.3V Read and Write Operations • Concurrent Operation – Read from or Write to SRAM while Erase/Program Flash • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 15 mA (typical) for Flash or SRAM Read – Standby Current: 12 µA (typical) • Flexible Erase Capability – Uniform 2 KWord sectors – Uniform 32 KWord size blocks • Erase-Suspend/Erase-Resume Capabilities • Security-ID Feature – User: 128 bits • Fast Read Access Times: – Flash: 70 ns – SRAM: 70 ns • Latched Address and Data for Flash • Flash Fast Erase and Word-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 40 ms (typical) – Word-Program Time: 7 µs (typical) • Flash Automatic Erase and Program Timing – Internal VPP Generation • Flash End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard Command Set • Package Available – 48-ball LBGA (10mm x 12mm x 1.4mm) • All non-Pb (lead-free) devices are RoHS compliant PRODUCT DESCRIPTION The SST32HF324C ComboMemory devices integrate a CMOS flash memory bank with a CMOS SRAM memory bank in a Multi-Chip Package (MCP), manufactured with SST’s proprietary, high-performance SuperFlash technology. Featuring high performance Word-Program, the flash memory bank provides a maximum Word-Program time of 7 µsec. To protect against inadvertent flash write, the SST32HF324C devices contain on-chip hardware and software data protection schemes. The SST32HF324C devices offer a guaranteed endurance of 10,000 cycles. Data retention is rated at greater than 100 years. The SST32HF324C devices consist of two independent memory banks with respective bank enable signals. The Flash and SRAM memory banks are superimposed in the same memory address space. Both memory banks share common address lines, data lines, WE# and OE#. The memory bank selection is done by memory bank enable signals. The SRAM bank enable signal, BES# selects the SRAM bank. The flash memory bank enable signal, BEF# selects the flash memory bank. The WE# signal has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The SDP command sequence protects the data stored in the flash memory bank from accidental alteration. ©2005 Silicon Storage Technology, Inc. S71267-02-000 9/05 1 The SST32HF324C provide the added functionality of being able to simultaneously read from or write to the SRAM bank while erasing or programming in the flash memory bank. The SRAM memory bank can be read or written while the flash memory bank performs SectorErase, Bank-Erase, or Word-Program concurrently. All flash memory Erase and Program operations will automatically latch the input address and data signals and complete the operation in background without further input stimulus requirement. Once the internally controlled Erase or Program cycle in the flash bank has commenced, the SRAM bank can be accessed for Read or Write. The SST32HF324C devices are suited for applications that use both flash memory and SRAM memory to store code or data. For systems requiring low power and small form factor, the SST32HF324C devices significantly improve performance and reliability while lowering power consumption when compared with multiple chip solutions. The SST32HF324C inherently use less energy during Erase and Program operations than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since, for any given voltage range, SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF+ and ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications Flash Word-Program Operation SuperFlash technology provides fixed Erase and Program times independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. The ComboMemory uses BES# and BEF# to control operation of either the SRAM or the flash memory bank. When BES# is low, the SRAM Bank is activated for Read and Write operation. When BEF# is low the flash bank is activated for Read, Program or Erase operation. BES# and BEF# cannot be at low level at the same time. If BES# and BEF# are both asserted to low level bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by SRAM Bank and flash bank which minimizes power consumption and loading. The device goes into standby when both bank enables are high. The flash memory bank of the SST32HF324C devices is programmed on a word-by-word basis. Before Program operations, the memory must be erased first. The Program operation consists of three steps. The first step is the threebyte load sequence for Software Data Protection. The second step is to load word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either BEF# or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# or WE#, whichever occurs last. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF#, whichever occurs first. The Program operation, once initiated, will be completed, within 10 µs. See Figures 6 and 7 for WE# and BEF# controlled Program operation timing diagrams and Figure 18 for flowcharts. During the Program operation, the only valid flash Read operations are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any SDP commands loaded during the internal Program operation will be ignored. Concurrent Read/Write Operation Flash Sector-/Block-Erase Operation The SST32HF324C provide the unique benefit of being able to read from or write to SRAM, while simultaneously erasing or programming the flash. This allows data alteration code to be executed from SRAM, while altering the data in flash. See Figure 22 for a flowchart. The following table lists all valid states. The Flash Sector/Block-Erase operation allows the system to erase the device on a sector-by-sector (or block-byblock) basis. The SST32HF324C offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 2 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The address lines AMS-A11 are used to determine the sector address. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The address lines AMS-A15 are used to determine the block address. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase operation can be determined using either Data# Polling or Toggle Bit methods. See Figures 11 and 12 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. Device Operation CONCURRENT READ/WRITE STATE TABLE Flash Program/Erase Program/Erase SRAM Read Write The device will ignore all SDP commands when an Erase or Program operation is in progress. Note that Product Identification commands use SDP; therefore, these commands will also be ignored while an Erase or Program operation is in progress. Flash Read Operation The Read operation of the SST32HF324C devices is controlled by BEF# and OE#. Both have to be low, with WE# high, for the system to obtain data from the outputs. BEF# is used for flash memory bank selection. When BEF# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to Figure 5 for further details. ©2005 Silicon Storage Technology, Inc. S71267-02-000 2 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications Erase-Suspend/-Resume Commands Write Operation Status Detection The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing data to be read from any memory location, or program data into any sector/block that is not suspended for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not suspended from an Erase operation. Reading at address location within erase-suspended sectors/blocks will output DQ2 toggling and DQ6 at “1”. While in Erase-Suspend mode, a Word-Program operation is allowed except for the sector or block selected for Erase-Suspend. The SST32HF324C provide two software means to detect the completion of a write (Program or Erase) cycle, in order to optimize the system Write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue Erase Resume command. The operation is executed by issuing one byte command sequence with Erase Resume command (30H) at any address in the last Byte sequence. Flash Data# Polling (DQ7) Flash Chip-Erase Operation When the SST32HF324C flash memory banks are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge of the fourth WE# (or BEF#) pulse for Program operation. For Sector- or Block-Erase, the Data# Polling is valid after the rising edge of the sixth WE# (or BEF#) pulse. See Figure 8 for Data# Polling timing diagram and Figure 19 for a flowchart. The SST32HF324C provide a Chip-Erase operation, which allows the user to erase the entire memory array to the “1” state. This is useful when the entire device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF#, whichever occurs first. During the Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 5 for the command sequence, Figure 9 for timing diagram, and Figure 21 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. ©2005 Silicon Storage Technology, Inc. S71267-02-000 3 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications Toggle Bits (DQ6 and DQ2) Flash Software Data Protection (SDP) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. For Sector-, Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the rising edge of sixth WE# (or BEF#) pulse. DQ6 will be set to “1” if a Read operation is attempted on an Erase-Suspended Sector/Block. If Program operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ6 will toggle. The SST32HF324C provide the JEDEC approved software data protection scheme for all flash memory bank data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three byte-load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. The SST32HF324C devices are shipped with the software data protection permanently enabled. See Table 5 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode, within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. An additional Toggle Bit is available on DQ2, which can be used in conjunction with DQ6 to check whether a particular sector is being actively erased or erase-suspended. Table 1 shows detailed status bits information. The Toggle Bit (DQ2) is valid after the rising edge of the last WE# (or BEF#) pulse of Write operation. See Figure 9 for Toggle Bit timing diagram and Figure 19 for a flowchart. SRAM Read The SRAM Read operation of the SST32HF324C is controlled by OE# and BES#, both have to be low with WE# high for the system to obtain data from the outputs. BES# is used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 2, for further details. TABLE 1: WRITE OPERATION STATUS Status DQ7 DQ6 DQ2 Normal Standard Operation Program DQ7# Toggle No Toggle Standard Erase 0 Toggle Toggle Read from Erase-Suspended Sector/Block 1 1 Toggle EraseSuspend Mode SRAM Write Read from Non- Erase-Suspended Sector/Block Data Data Program DQ7# Toggle The SRAM Write operation of the SST32HF324C is controlled by WE# and BES#; both have to be low for the system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of either BES# or WE#, whichever occurs first. The Write time is measured from the last falling edge of BES# or WE# to the first rising edge of BES# or WE#. Refer to the Write cycle timing diagrams, Figures 3 and 4, for further details. Data N/A T1.0 1267 Note: DQ7 and DQ2 require a valid address when reading status information. Flash Memory Data Protection The SST32HF324C flash memory bank provides both hardware and software features to protect nonvolatile data from inadvertent writes. Product Identification The Product Identification mode identifies the devices as the SST32HF324C and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers, cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Flash Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# pulse of less than 5 ns will not initiate a Write cycle. VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. Write Inhibit Mode: Forcing OE# low, BEF# high, or WE# high will inhibit the flash Write operation. This prevents inadvertent writes during power-up or power-down. ©2005 Silicon Storage Technology, Inc. S71267-02-000 4 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications Security ID Tables 4 and 5 for software operation, Figure 13 for the software ID entry and read timing diagram and Figure 20 for the ID entry command sequence flowchart. The SST32HF324C device offers one 128-bit Security ID space. This space is left un-programmed for the customer to program as desired. TABLE 2: PRODUCT IDENTIFICATION Manufacturer’s ID Address Data 0000H BFH 0001H 235BH To program the Security ID, the user must use the Security ID Word-Program command. To detect end-of-write for the SEC ID, read the toggle bits. Do not use Data# Polling. Once this is complete, the Sec ID should be locked using the User Sec ID Program Lock-Out. This disables any future corruption of this space. Note that regardless of whether or not the Sec ID is locked, the Sec ID segment cannot be erased. Device ID SST32HF324C T2.0 1267 Product Identification Mode Exit/Reset In order to return to the standard read mode, the Software Product Identification mode must be exited. Exiting is accomplished by issuing the Exit ID command sequence, which returns the device to the Read operation. Please note that the software reset command is ignored during an internal Program or Erase operation. This command may also be used to reset the device to Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g. not read correctly. See Table 5 for software command codes, Figure 14 for timing waveform and Figure 20 for a flowchart. The Secure ID space can be queried by executing a threebyte command sequence with Enter Sec ID command (88H) at address 5555H in the last byte sequence. To exit this mode, the Exit Sec ID command should be executed. Refer to Table 5 for more details. Design Considerations SST recommends a high frequency 0.1 µF ceramic capacitor to be placed as close as possible between VDD and VSS, e.g., less than 1 cm away from the VDD pin of the device. Additionally, a low frequency 4.7 µF electrolytic capacitor from VDD to VSS should be placed within 1 cm of the VDD pin. FUNCTIONAL BLOCK DIAGRAM Address Buffers AMS(1)-A0 UBS# LBS# BES# BEF# OE# WE# SRAM Control Logic Address Buffers & Latches I/O Buffers SuperFlash Memory ©2005 Silicon Storage Technology, Inc. DQ15 - DQ8 DQ7 - DQ0 1267 B1.0 S71267-02-000 5 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications TOP VIEW (balls facing down) SST32HF324C 6 5 4 BES# VSS DQ1 A1 A2 A4 A19 A9 A10 DQ5 DQ2 A0 A3 A7 A20 A14 OE# DQ7 DQ4 DQ0 A6 A18 NC A15 3 A5 A11 A8 DQ3 DQ12 A12 LBS# A13 A17 UBS# BEF# DQ10 VDDF DQ6 DQ15 DQ8 1 WE# VDDS A16 VSS DQ9 DQ11 DQ13 DQ14 A B C D E F G H 1267 48-lbga P2.1 2 FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL LBGA (10MM X 12MM) TABLE 3: PIN DESCRIPTION Symbol Pin Name Functions AMS1-A0 Address Inputs To provide flash addresses: A20-A0 SRAM addresses: A17-A0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# or BES# and BEF# are high. DQ15-DQ0 BES# SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low. BEF# Flash Memory Bank Enable To activate the flash memory bank when BEF# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDDF Power Supply (Flash) 2.7-3.3V Power Supply to flash only. VDDS Power Supply (SRAM) 2.7-3.3V Power Supply to SRAM only VSS UBS# LBS# NC Ground Upper Byte Control (SRAM) To enable DQ15-DQ8 Lower Byte Control (SRAM) To enable DQ7-DQ0 No Connection Unconnected Pins T3.0 1267 1. AMS=Most significant address ©2005 Silicon Storage Technology, Inc. S71267-02-000 6 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications TABLE 4: OPERATION MODES SELECTION Mode BES#1 BEF#1 OE# WE# UBS# LBS# DQ15 to DQ8 DQ7 to DQ0 Address VIL VIL X2 X X X X X X Read VIH VIL VIL VIH X X DOUT DOUT AIN Program VIH VIL VIH VIL X X DIN DIN AIN X VIL VIH VIL X X X X Sector or Block address, XXH for Chip-Erase VIL VIH VIL VIH VIL VIL DOUT DOUT AIN VIL VIH VIL VIH VIL VIH DOUT High Z AIN VIL VIH VIL VIH VIH VIL High Z DOUT AIN VIL VIH X VIL VIL VIL DIN DIN AIN VIL VIH X VIL VIL VIH DIN High Z AIN Not Allowed Flash Erase SRAM Read Write Standby Flash Write Inhibit Output Disable VIL VIH X VIL VIH VIL High Z DIN AIN VIHC VIHC X X X X High Z High Z X X X VIL X X X High Z / DOUT High Z / DOUT X X X X VIH X X High Z / DOUT High Z / DOUT X X VIH X X X X High Z / DOUT High Z / DOUT X VIH VIL VIH VIH X X High Z High Z X VIL VIH X X VIH VIH High Z High Z X VIL VIH VIH VIH X X High Z High Z X VIH VIL VIL VIH X X Product Identification Software Mode Manufacturer’s ID (00BFH) Device ID3 A19-A1=VIL, A0=VIH (See Table 4) T4.0 1267 1. Do not apply BES#=VIL and BEF#=VIL at the same time 2. X can be VIL or VIH, but no other value. SST Manufacturer’s ID = 00BFH, is read with A0=0, 3. With AMS-A1 = 0; SST32HF324C Device ID = 235BH, is read with A0=1 ©2005 Silicon Storage Technology, Inc. S71267-02-000 7 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications TABLE 5: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle Addr1 Data2 2nd Bus Write Cycle Addr1 Data2 3rd Bus Write Cycle Addr1 4th Bus Write Cycle Data2 Addr1 Data2 Data AAH Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3 Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data2 Addr1 Data2 2AAAH 55H SAX4 30H 4 Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H Erase-Suspend XXXXH B0H Erase-Resume XXXXH 30H ID5 5555H AAH 2AAAH 55H 5555H 88H User Security ID Word-Program 5555H AAH 2AAAH 55H 5555H A5H WA6 Data User Security ID Program Lock-Out 5555H AAH 2AAAH 55H 5555H 85H XXH6 0000H Software ID Entry7,8 5555H AAH 2AAAH 55H 5555H 90H 5555H AAH 2AAAH 55H 5555H F0H XXH F0H Query Sec Software ID /Sec ID Exit Exit9 Software ID Exit9 /Sec ID Exit 50H 10H T5.1 1267 1. Address format A14-A0 (Hex). Addresses A15-A20 can be VIL or VIH, but no other value, for Command sequence for SST32HF324C. 2. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence 3. WA = Program Word address 4. SAX for Sector-Erase; uses AMS-A11 address lines BAX, for Block-Erase; uses AMS-A15 address lines AMS = Most significant address AMS = A20 for SST32HF324C. 5. With A20-A5 = 0; Sec ID is read with A4-A0, User ID is read with A4 = 1 (Address range = 000010H to 000017H). Lock Status is read with A7-A0 = 0000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0. 6. Valid Word-Addresses for Sec ID are from 000010H-000017H. 7. The device does not remain in Software Product ID Mode if powered down. 8. With AMS-A1 =0; SST Manufacturer ID = 00BFH, is read with A0 = 0, SST32HF324C Device ID = 235BH, is read with A0 = 1, AMS = Most significant address AMS = A20 for SST32HF324C. 9. Both Software ID Exit operations are equivalent ©2005 Silicon Storage Technology, Inc. S71267-02-000 8 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD1+0.3V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD1+1.0V Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds Output Short Circuit Current3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. VDD = VDDF and VDDS 2. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information. 3. Outputs shorted for no more than one second. No more than one output shorted at a time. OPERATING RANGE Range Commercial Extended Ambient Temp VDD 0°C to +70°C 2.7-3.3V -20°C to +85°C 2.7-3.3V AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF See Figures 16 and 17 ©2005 Silicon Storage Technology, Inc. S71267-02-000 9 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications TABLE 6: DC OPERATING CHARACTERISTICS (VDD = VDDF AND VDDS = 2.7-3.3V) Limits Symbol Parameter IDD Active VDD Current Min Max Units Address input = VILT/VIHT, at f=5 MHz, VDD=VDD Max, all DQs open Test Conditions Read OE#=VIL, WE#=VIH Flash 18 mA BEF#=VIL, BES#=VIH SRAM 30 mA BEF#=VIH, BES#=VIL 40 mA Concurrent Operation Write1 BEF#=VIH, BES#=VIL WE#=VIL Flash 35 mA BEF#=VIL, BES#=VIH, OE#=VIH SRAM 30 mA BEF#=VIH, BES#=VIL ISB Standby VDD Current 30 µA VDD = VDD Max, BEF#=BES#=VIHC ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VILC Input Low Voltage (CMOS) 0.3 V VDD=VDD Max VIH Input High Voltage 0.7 VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 VOLF Flash Output Low Voltage VOHF Flash Output High Voltage VOLS SRAM Output Low Voltage VOHS SRAM Output High Voltage 0.2 VDD-0.2 0.4 2.2 V VDD=VDD Max V IOL=100 µA, VDD=VDD Min V IOH=-100 µA, VDD=VDD Min V IOL =1 mA, VDD=VDD Min V IOH =-500 µA, VDD=VDD Min T6.0 1267 1. IDD active while Erase or Program is in progress. TABLE 7: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 µs Power-up to Program/Erase Operation 100 µs TPU-WRITE 1 T7.0 1267 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 12 pF CIN 1 T8.0 1267 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 9: FLASH RELIABILITY CHARACTERISTICS Symbol NEND 1 Parameter Minimum Specification Units Endurance 10,000 Cycles JEDEC Standard A117 100 Years JEDEC Standard A103 100 + IDD mA TDR1 Data Retention ILTH1 Latch Up Test Method JEDEC Standard 78 T9.0 1267 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2005 Silicon Storage Technology, Inc. S71267-02-000 10 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications AC CHARACTERISTICS TABLE 10: SRAM READ CYCLE TIMING PARAMETERS Symbol Parameter Min 70 Max Units TRCS Read Cycle Time TAAS Address Access Time 70 ns TBES Bank Enable Access Time 70 ns TOES Output Enable Access Time 35 ns TBYES UBS#, LBS# Access Time 70 ns TBLZS1 BES# to Active Output 0 ns TOLZS1 Output Enable to Active Output 0 ns TBYLZS1 UBS#, LBS# to Active Output 0 ns TBHZS 1 BES# to High-Z Output TOHZS1 TBYHZS Output Disable to High-Z Output 1 TOHS 0 UBS#, LBS# to High-Z Output Output Hold from Address Change ns 25 ns 25 ns 35 ns 10 ns T10.0 1267 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 11: SRAM WRITE CYCLE TIMING PARAMETERS Symbol Parameter Min TWCS Write Cycle Time 70 Max Units TBWS Bank Enable to End-of-Write 60 ns TAWS Address Valid to End-of-Write 60 ns TASTS Address Set-up Time 0 ns TWPS Write Pulse Width 60 ns TWRS Write Recovery Time 0 ns TBYWS UBS#, LBS# to End-of-Write 60 ns TODWS Output Disable from WE# Low TOEWS Output Enable from WE# High 0 ns TDSS Data Set-up Time 30 ns TDHS Data Hold from Write Time 0 ns 30 ns ns T11.0 1267 ©2005 Silicon Storage Technology, Inc. S71267-02-000 11 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications TABLE 12: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V Symbol Parameter Min TRC Read Cycle Time 70 Max Units TCE Chip Enable Access Time 70 ns TAA Address Access Time 70 ns TOE Output Enable Access Time TCLZ1 BEF# Low to Active Output 0 TOLZ1 OE# Low to Active Output 0 TCHZ1 BEF# High to High-Z Output TOHZ1 OE# High to High-Z Output TOH1 Output Hold from Address Change ns 35 ns ns ns 20 ns 20 ns 0 ns T12.0 1267 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 13: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter Min Max Units 10 µs TBP Word-Program Time TAS Address Setup Time 0 TAH Address Hold Time 30 ns TCS WE# and BEF# Setup Time 0 ns TCH WE# and BEF# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP BEF# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns TCPH1 BEF# Pulse Width High 30 ns TDS Data Setup Time 30 ns Data Hold Time 0 TDH 1 ns ns TIDA1 Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase 50 ms T13.0 1267 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2005 Silicon Storage Technology, Inc. S71267-02-000 12 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications TRCS ADDRESSES AMSS-0 TOHS TAAS TBES BES# TBLZS TBHZS TOES OE# TOLZS TOHZS TBYES UBS#, LBS# TBYLZS TBYHZS DQ15-0 DATA VALID 1267 F02.0 Note: AMSS = Most Significant SRAM Address AMSS = A17 for SST32HF324C FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM TWCS ADDRESSES AMSS3-0 TASTS TWRS TWPS WE# TAWS TBWS BES# TBYWS UBS#, LBS# TOEWS TODWS TDSS DQ15-8, DQ7-0 NOTE 2 TDHS VALID DATA IN NOTE 2 1267 F03.0 Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. If BES# goes Low coincident with or after WE# goes Low, the output will remain at high impedance. If BES# goes High coincident with or before WE# goes High, the output will remain at high impedance. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A17 for SST32HF324C FIGURE 3: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1 ©2005 Silicon Storage Technology, Inc. S71267-02-000 13 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications TWCS ADDRESSES AMSS3-0 TWRS TWPS WE# TBWS BES# TAWS TASTS TBYWS UBS#, LBS# TDSS VALID DATA IN NOTE 2 DQ15-8, DQ7-0 TDHS NOTE 2 1267 F04.0 Note: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. 3. AMSS = Most Significant SRAM Address AMSS = A17 for SST32HF324C FIGURE 4: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1 TAA TRC ADDRESS AMS-0 TCE BEF# TOE OE# VIH TOHZ TOLZ WE# DQ15-0 HIGH-Z TOH TCLZ DATA VALID TCHZ HIGH-Z DATA VALID 1267 F05.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C FIGURE 5: FLASH READ CYCLE TIMING DIAGRAM ©2005 Silicon Storage Technology, Inc. S71267-02-000 14 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 ADDR TDH TWP WE# TAS TDS TWPH OE# TCH BEF# TCS DQ15-0 XXAA XX55 XXA0 SW0 SW1 SW2 DATA WORD (ADDR/DATA) 1267 F06.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C X can be VIL or VIH, but no other value FIGURE 6: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM INTERNAL PROGRAM OPERATION STARTS TBP 5555 TAH ADDRESS AMS-0 2AAA 5555 ADDR TDH TCP BEF# TAS TDS TCPH OE# TCH WE# TCS DQ15-0 XXAA XX55 XXA0 DATA SW0 SW1 SW2 WORD (ADDR/DATA) 1267 F07.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C X can be VIL or VIH, but no other value FIGURE 7: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM ©2005 Silicon Storage Technology, Inc. S71267-02-000 15 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications ADDRESSES AMSF-0 TCE BEF# TOES TOEH OE# TOE WE# DQ7 Data Data# Data# Data 1267 F08.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C FIGURE 8: FLASH DATA# POLLING TIMING DIAGRAM ADDRESSES AMSF-0 TCE BEF# TOEH TOE TOES OE# WE# DQ6 and DQ2 TWO READ CYCLES WITH SAME OUTPUTS 1267 F09.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C FIGURE 9: FLASH TOGGLE BIT TIMING DIAGRAM ©2005 Silicon Storage Technology, Inc. S71267-02-000 16 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555 BEF# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 SW0 SW1 SW2 SW3 SW4 SW5 1267 F10.0 Note: This device also supports BEF# controlled Chip-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13) AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C X can be VIL or VIH, but no other value. FIGURE 10: WE# CONTROLLED FLASH CHIP-ERASE TIMING DIAGRAM TBE SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA BAX BEF# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 SW0 SW1 SW2 SW3 SW4 SW5 1267 F11.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C This device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13.) BAX = Block Address X can be VIL or VIH, but no other value. FIGURE 11: WE# CONTROLLED FLASH BLOCK-ERASE TIMING DIAGRAM ©2005 Silicon Storage Technology, Inc. S71267-02-000 17 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications TSE SIX-BYTE CODE FOR SECTOR-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA SAX BEF# OE# TWP WE# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 SW0 SW1 SW2 SW3 SW4 SW5 1267 F12.0 Note: AMSF = Most Significant Flash Address AMSF = A20 for SST32HF324C This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchangeable as long as minimum timings are met. (See Table 13.) SAX = Sector Address X can be VIL or VIH, but no other value. FIGURE 12: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM ©2005 Silicon Storage Technology, Inc. S71267-02-000 18 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications THREE-WORD SEQUENCE FOR SOFTWARE ID ENTRY 5555 ADDRESS A14-0 2AAA 5555 0000 0001 BEF# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX90 00BF SW0 SW1 SW2 MFG ID DEVICE ID 1267 F13.0 Note: X can be VIL or VIH, but no other value. Device ID - See Table 2 on page 5 FIGURE 13: SOFTWARE ID ENTRY AND READ THREE-WORD SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 ADDRESS A14-0 DQ15-0 XXAA 2AAA 5555 XX55 XXF0 TIDA BEF# OE# TWP WE# TWHP 1267 F14.0 SW0 SW1 SW2 Note: X can be VIL or VIH, but no other value. FIGURE 14: SOFTWARE ID EXIT AND RESET ©2005 Silicon Storage Technology, Inc. S71267-02-000 19 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY 5555 ADDRESS A20-0 2AAA 5555 BEF# OE# TIDA TWP WE# TWPH DQ15-0 TAA XXAA XX55 XX88 SW0 SW1 SW2 1267 F22.0 Note: X can be VIL or VIH, but no other value. FIGURE 15: SEC ID ENTRY ©2005 Silicon Storage Technology, Inc. S71267-02-000 20 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1267 F15.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5VDD) and VOT (0.5VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 16: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 1267 F16.0 FIGURE 17: A TEST LOAD EXAMPLE ©2005 Silicon Storage Technology, Inc. S71267-02-000 21 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications Start Write data: XXAAH Address: 5555H Write data: XX55H Address: 2AAAH Write data: XXA0H Address: 5555H Write Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1267 F17.0 Note: X can be VIL or VIH, but no other value FIGURE 18: WORD-PROGRAM ALGORITHM ©2005 Silicon Storage Technology, Inc. S71267-02-000 22 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Read word Read DQ7 Wait TBP, TSCE, or TBE Read same word Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1267 F18.0 FIGURE 19: WAIT OPTIONS ©2005 Silicon Storage Technology, Inc. S71267-02-000 23 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications Software Product ID Entry Command Sequence Sec ID Query Entry Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXF0H Address: XXH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Wait TIDA Load data: XX90H Address: 5555H Load data: XX88H Address: 5555H Load data: XXF0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Wait TIDA Read Software ID Read Sec ID Return to normal operation Software Product ID/Sec ID Exit Command Sequence 1267 F19.1 X can be VIL or VIH, but no other value FIGURE 20: SOFTWARE PRODUCT COMMAND FLOWCHARTS ©2005 Silicon Storage Technology, Inc. S71267-02-000 24 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX10H Address: 5555H Load data: XX30H Address: SAX Load data: XX50H Address: BAX Wait TSCE Wait TSE Wait TBE Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 1267 F20.0 Note: X can be VIL or VIH, but no other value. FIGURE 21: ERASE COMMAND SEQUENCE ©2005 Silicon Storage Technology, Inc. S71267-02-000 25 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications Concurrent Operation Load SDP Command Sequence Flash Program/Erase Initiated Wait for End of Write Indication Read or Write SRAM End Wait Flash Operation Completed End Concurrent Operation 1267 F21.0 FIGURE 22: CONCURRENT OPERATION FLOWCHART ©2005 Silicon Storage Technology, Inc. S71267-02-000 26 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications PRODUCT ORDERING INFORMATION Device Speed SST32HFxxxC - XXX Suffix1 - XX Suffix2 - XXXX Package Attribute E1 = non-Pb Package Modifier K = 48 leads or balls Package Type LB = LBGA (10mm x 12mm x 1.4mm) Temperature Range C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 70 = 70 ns Density 324 = 32 Mbit Flash + 4 Mbit SRAM Voltage H = 2.7-3.3V Product Series 32 = MPF + SRAM ComboMemory 1. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”. Valid combinations for SST32HF324C SST32HF324C-70-4C-LBK SST32HF324C-70-4C-LBKE SST32HF324C-70-4E-LBK SST32HF324C-70-4E-LBKE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2005 Silicon Storage Technology, Inc. S71267-02-000 27 9/05 Multi-Purpose Flash Plus + SRAM ComboMemory SST32HF324C Preliminary Specifications PACKAGING DIAGRAMS TOP VIEW BOTTOM VIEW 12.00 ± 0.20 7.0 1.0 6 6 5 5 5.0 4 4 10.00 ± 0.20 3 3 2 2 1 1 1.0 0.50 ± 0.05 (48X) A B C D E F G H H G F E D C B A A1 CORNER A1 CORNER SIDE VIEW 1.4 Max 0.12 SEATING PLANE 1mm 0.40 ± 0.05 Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.4 mm (± 0.05 mm) 48-lbga-LBK-10x12-500mic-2 48-BALL LOW-PROFILE BALL GRID ARRAY (LBGA) 10MM X 12MM SST PACKAGE CODE: LBK TABLE 14: REVISION HISTORY Number Description Date 00 • Initial Release 01 • • Removed all 16 Mbit devices and related MPNs Added RoHS compliance information on page 1 and in the “Product Ordering Information” on page 27 Added the solder reflow temperature to the “Absolute Maximum Stress Ratings” on page 9. May 2005 Added User Security ID feature Sep 2005 • 02 • Jul 2004 Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2005 Silicon Storage Technology, Inc. S71267-02-000 28 9/05