512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit (x8) Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 SST39LF/VF512 / 010 / 020 / 0403.0 & 2.7V 512Kb / 1Mb / 2Mb / 4Mb (x8) MPF memories Data Sheet FEATURES: • Organized as 64K x8 / 128K x8 / 256K x8 / 512K x8 • Single Voltage Read and Write Operations – 3.0-3.6V for SST39LF512/010/020/040 – 2.7-3.6V for SST39VF512/010/020/040 • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption (typical values at 14 MHz) – Active Current: 5 mA (typical) – Standby Current: 1 µA (typical) • Sector-Erase Capability – Uniform 4 KByte sectors • Fast Read Access Time: – 45 ns for SST39LF512/010/020/040 – 55 ns for SST39LF020/040 – 70 ns for SST39VF512/010/020/040 • Latched Address and Data • Fast Erase and Byte-Program: – Sector-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Byte-Program Time: 14 µs (typical) – Chip Rewrite Time: 1 second (typical) for SST39LF/VF512 2 seconds (typical) for SST39LF/VF010 4 seconds (typical) for SST39LF/VF020 8 seconds (typical) for SST39LF/VF040 • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard – Flash EEPROM Pinouts and command sets • Packages Available – 32-lead PLCC – 32-lead TSOP (8mm x 14mm) – 48-ball TFBGA (6mm x 8mm) – 34-ball WFBGA (4mm x 6mm) for 1M and 2M • All devices are RoHS compliant PRODUCT DESCRIPTION The SST39LF512, SST39LF010, SST39LF020, SST39LF040 and SST39VF512, SST39VF010, SST39VF020, SST39VF040 are 64K x8, 128K x8, 256K x8 and 5124K x8 CMOS Multi-Purpose Flash (MPF) manufactured with SST’s proprietary, high performance CMOS SuperFlash technology. The split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. The SST39LF512/010/020/040 devices write (Program or Erase) with a 3.0-3.6V power supply. The SST39VF512/010/020/040 devices write with a 2.7-3.6V power supply. The devices conform to JEDEC standard pinouts for x8 memories. Featuring high performance Byte-Program, the SST39LF512/010/020/040 and SST39VF512/010/020/ 040 devices provide a maximum Byte-Program time of 20 µsec. These devices use Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent write, they have on-chip hardware and Software Data Protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, they are offered with a guaranteed typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices are suited for applications that require convenient and economical updating of program, configu©2010 Silicon Storage Technology, Inc. S71150-14-000 01/10 1 ration, or data memory. For all system applications, they significantly improves performance and reliability, while lowering power consumption. They inherently use less energy during Erase and Program than alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to program and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash technologies. These devices also improve flexibility while lowering the cost for program, data, and configuration storage applications. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase and Program times increase with accumulated Erase/Program cycles. To meet surface mount requirements, the SST39LF512/ 010/020/040 and SST39VF512/010/020/040 devices are offered in 32-lead PLCC and 32-lead TSOP packages. The SST39LF/VF010 and SST39LF/VF020 are also offered in a 48-ball TFBGA package. See Figures 2, 3, 4, and 5 for pin assignments. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Device Operation edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. The End-of-Erase can be determined using either Data# Polling or Toggle Bit methods. See Figure 11 for timing waveforms. Any commands written during the Sector-Erase operation will be ignored. Commands are used to initiate the memory operation functions of the device. Commands are written to the device using standard microprocessor write sequences. A command is written by asserting WE# low while keeping CE# low. The address bus is latched on the falling edge of WE# or CE#, whichever occurs last. The data bus is latched on the rising edge of WE# or CE#, whichever occurs first. Chip-Erase Operation The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices provide a Chip-Erase operation, which allows the user to erase the entire memory array to the ‘1’s state. This is useful when the entire device must be quickly erased. Read The Read operation of the SST39LF512/010/020/040 and SST39VF512/010/020/040 device is controlled by CE# and OE#, both have to be low for the system to obtain data from the outputs. CE# is used for device selection. When CE# is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either CE# or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 6). The Chip-Erase operation is initiated by executing a sixbyte Software Data Protection command sequence with Chip-Erase command (10H) with address 5555H in the last byte sequence. The internal Erase operation begins with the rising edge of the sixth WE# or CE#, whichever occurs first. During the internal Erase operation, the only valid read is Toggle Bit or Data# Polling. See Table 4 for the command sequence, Figure 12 for timing diagram, and Figure 20 for the flowchart. Any commands written during the ChipErase operation will be ignored. Byte-Program Operation The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 are programmed on a byte-by-byte basis. Before programming, the sector where the byte exists must be fully erased. The Program operation is accomplished in three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load byte address and byte data. During the Byte-Program operation, the addresses are latched on the falling edge of either CE# or WE#, whichever occurs last. The data is latched on the rising edge of either CE# or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or CE#, whichever occurs first. The Program operation, once initiated, will be completed, within 20 µs. See Figures 7 and 8 for WE# and CE# controlled Program operation timing diagrams and Figure 17 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands written during the internal Program operation will be ignored. Write Operation Status Detection The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 devices provide two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system write cycle time. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE# which initiates the internal Program or Erase operation. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Sector-Erase Operation The Sector-Erase operation allows the system to erase the device on a sector-by-sector basis. The sector architecture is based on uniform sector size of 4 KByte. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The sector address is latched on the falling edge of the sixth WE# pulse, while the command (30H) is latched on the rising ©2010 Silicon Storage Technology, Inc. S71150-14-000 2 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Data# Polling (DQ7) Software Data Protection (SDP) When the SST39LF512/010/020/040 and SST39VF512/ 010/020/040 are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt to read DQ7 will produce a “0”. Once the internal Erase operation is completed, DQ7 will produce a “1”. The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 9 for Data# Polling timing diagram and Figure 18 for a flowchart. The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 provide the JEDEC approved Software Data Protection scheme for all data alteration operation, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte load sequence. These devices are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to read mode, within TRC. Product Identification The Product Identification mode identifies the devices as the SST39LF/VF512, SST39LF/VF010, SST39LF/VF020 and SST39LF/VF040 and manufacturer as SST. This mode may be accessed by software operations. Users may use the Software Product Identification operation to identify the part (i.e., using the device ID) when using multiple manufacturers in the same socket. For details, see Table 4 for software operation, Figure 13 for the Software ID Entry and Read timing diagram, and Figure 19 for the Software ID entry command sequence flowchart. Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating ‘0’s and ‘1’s, i.e., toggling between 0 and 1. When the internal Program or Erase operation is completed, the toggling will stop. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector- or ChipErase, the Toggle Bit is valid after the rising edge of sixth WE# (or CE#) pulse. See Figure 10 for Toggle Bit timing diagram and Figure 18 for a flowchart. TABLE 1: Product Identification Address Data 0000H BFH SST39LF/VF512 0001H D4H SST39LF/VF010 0001H D5H SST39LF/VF020 0001H D6H SST39LF/VF040 0001H D7H Manufacturer’s ID Data Protection Device ID The SST39LF512/010/020/040 and SST39VF512/010/ 020/040 provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection T1.1 1150 Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a Write cycle. Product Identification Mode Exit/Reset VDD Power Up/Down Detection: The Write operation is inhibited when VDD is less than 1.5V. In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 14 for timing waveform, and Figure 19 for a flowchart. Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. ©2010 Silicon Storage Technology, Inc. S71150-14-000 3 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet SuperFlash Memory X-Decoder Memory Address Address Buffers & Latches Y-Decoder CE# I/O Buffers and Data Latches Control Logic OE# WE# DQ7 - DQ0 1150 B1.1 A17 WE# NC NC A17 WE# WE# WE# VDD A18 VDD VDD A16 VDD NC NC 4 3 2 1 32 31 30 29 NC A16 NC A16 A12 A15 A15 A15 A12 A12 A15 SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512 A12 SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 FIGURE 1: Functional Block Diagram SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 A7 A7 5 A14 A14 A14 A14 A6 A6 A6 A6 6 28 A13 A13 A13 A13 A5 A5 A5 A5 7 27 A8 A8 A8 A8 A4 A4 A4 A4 8 26 A9 A9 A9 A9 A3 A3 A3 A3 9 25 A11 A11 A11 A11 A2 A2 A2 A2 10 24 OE# OE# OE# OE# A1 A1 A1 A1 11 23 A10 A10 A10 A10 A0 A0 A0 A0 12 22 CE# CE# CE# CE# DQ0 DQ0 DQ0 DQ0 13 21 14 15 16 17 18 19 20 DQ7 DQ7 DQ7 DQ7 DQ5 1150 32-plcc NH P4.3 DQ6 DQ6 DQ6 DQ5 DQ5 DQ5 DQ4 DQ4 DQ4 DQ4 VSS DQ3 DQ3 VSS VSS DQ3 VSS DQ3 DQ2 DQ2 DQ2 DQ2 DQ1 DQ1 DQ1 DQ1 32-lead PLCC Top View DQ6 A7 SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512 A7 FIGURE 2: Pin Assignments for 32-lead PLCC ©2010 Silicon Storage Technology, Inc. S71150-14-000 4 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet SST39LF/VF040 SST39LF/VF020 SST39LF/VF010 SST39LF/VF512 A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 A17 WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC A16 A15 A12 A7 A6 A5 A4 A11 A9 A8 A13 A14 NC WE# VDD NC NC A15 A12 A7 A6 A5 A4 SST39LF/VF512 SST39LF/VF010 SST39LF/VF020 SST39LF/VF040 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard Pinout Top View Die Up OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 OE# A10 CE# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1150 32-tsop WH P1.0 FIGURE 3: Pin Assignments for 32-lead TSOP (8mm x 14mm) TOP VIEW (balls facing down) SST39LF/VF010 SST39LF/VF020 A14 A13 A15 A16 NC NC 6 NC VSS 5 2 1 WE# NC NC NC DQ5 NC VDD DQ4 NC NC NC NC DQ2 DQ3 VDD NC A7 NC A6 A5 DQ0 NC NC DQ1 A3 A4 A2 A1 A0 CE# OE# VSS A D E B C F G NC VSS A9 A8 A11 A12 NC A10 DQ6 DQ7 1150 48-tfbga B3K P2.0 A9 A8 A11 A12 NC A10 DQ6 DQ7 4 3 A14 A13 A15 A16 A17 NC 5 4 WE# NC NC NC DQ5 NC VDD DQ4 3 NC NC NC NC DQ2 DQ3 VDD NC 2 1 H A7 NC A6 A5 DQ0 NC A3 A4 A2 A1 A0 CE# OE# VSS A D E B C F NC DQ1 G 1150 48-tfbga B3K P3.0 6 TOP VIEW (balls facing down) H TOP VIEW (balls facing down) SST39LF/VF040 6 A14 A13 A15 A16 A17 NC NC VSS A9 A8 A11 A12 NC A10 DQ6 DQ7 4 3 2 1 WE# NC NC NC DQ5 NC VDD DQ4 NC NC NC NC DQ2 DQ3 VDD NC A7 A18 A6 A5 DQ0 NC A3 A4 A2 A1 A0 CE# OE# VSS A D E B C F NC DQ1 G 1150 48-tfbga B3K P4.0 5 H FIGURE 4: Pin Assignment for 48-ball TFBGA (6mm x 8mm) for 1 Mbit, 2 Mbit, and 4 Mbit ©2010 Silicon Storage Technology, Inc. S71150-14-000 5 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet TOP VIEW (balls facing down) 6 A2 A8 A9 A14 A13 A11 NC1 OE# A10 CE# 5 A1 A17 A0 VDD WE# DQ3 DQ4 CE# A16 A18 DQ2 VSS A12 A15 A7 A6 A5 A4 NC2 A3 A2 A1 B C D E F G H DQ7 DQ5 DQ6 4 VSS 2 DQ0 DQ1 A0 1 A 1150 34-wfbga MM P5.0 3 J Note: For SST39LF020, ball B3 is "No Connect" For SST39LF010, balls B3 and A5 are "No Connect" FIGURE 5: Pin Assignment for 34-ball WFBGA (4mm x 6mm) for 1 Mbit and 2 Mbit TABLE 2: Pin Description Symbol Pin Name Functions AMS1-A0 Address Inputs To provide memory addresses. During Sector-Erase AMS-A12 address lines will select the sector. During Block-Erase AMS-A16 address lines will select the block. DQ7-DQ0 Data Input/output To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a Write cycle. The outputs are in tri-state when OE# or CE# is high. CE# Chip Enable To activate the device when CE# is low. OE# Output Enable To gate the data output buffers. WE# Write Enable To control the Write operations. VDD Power Supply To provide power supply voltage: VSS Ground NC No Connection 3.0-3.6V for SST39LF512/010/020/040 2.7-3.6V for SST39VF512/010/020/040 Unconnected pins. T2.1 1150 1. AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040 TABLE 3: Operation Modes Selection Mode CE# OE# WE# DQ Address Read VIL VIL VIH DOUT AIN Program VIL VIH VIL DIN AIN Erase VIL VIH VIL X1 Sector address, XXH for Chip-Erase Standby VIH X X High Z X X VIL X High Z/ DOUT X X X VIH High Z/ DOUT X VIL VIL VIH Write Inhibit Product Identification Software Mode See Table 4 T3.4 1150 1. X can be VIL or VIH, but no other value. ©2010 Silicon Storage Technology, Inc. S71150-14-000 6 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet TABLE 4: Software Command Sequence Command Sequence 1st Bus Write Cycle Addr1 Data 2nd Bus Write Cycle Addr1 Data 3rd Bus Write Cycle Addr1 4th Bus Write Cycle Data Addr1 Data Data 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data Addr1 Data Byte-Program 5555H AAH 2AAAH 55H 5555H A0H BA2 Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H SAX3 30H 5555H AAH 2AAAH 55H 5555H 10H Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H 2AAAH 55H 5555H F0H Software ID Exit6 XXH F0H Software ID Exit6 5555H AAH T4.2 1150 1. Address format A14-A0 (Hex), Address A15 can be VIL or VIH, but no other value, for the Command sequence for SST39LF/VF512. Addresses AMS-A15 can be VIL or VIH, but no other value, for the Command sequence. AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040 2. BA = Program Byte address 3. SAX for Sector-Erase; uses AMS-A12 address lines 4. The device does not remain in Software Product ID mode if powered down. 5. With AMS-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0, SST39LF/VF512 Device ID = D4H, is read with A0 = 1, SST39LF/VF010 Device ID = D5H, is read with A0 = 1, SST39LF/VF020 Device ID = D6H, is read with A0 = 1, SST39LF/VF040 Device ID = D7H, is read with A0 = 1. 6. Both Software ID Exit operations are equivalent Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Voltage on A9 Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 13.2V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .260°C for 10 seconds Output Short Circuit Current2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA 1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions. Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information. 2. Outputs shorted for no more than one second. No more than one output shorted at a time. Operating Range for SST39LF512/010/020/040 Range Commercial Ambient Temp VDD 0°C to +70°C 3.0-3.6V AC Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Output Load CL = 30 pF for SST39LF512/010/020/040 CL = 100 pF for SST39VF512/010/020/040 Operating Range for SST39VF512/010/020/040 Range Commercial Industrial Ambient Temp VDD 0°C to +70°C 2.7-3.6V -40°C to +85°C 2.7-3.6V See Figures 15 and 16 ©2010 Silicon Storage Technology, Inc. S71150-14-000 7 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet TABLE 5: DC Operating Characteristics -VDD = 3.0-3.6V for SST39LF512/010/020/040 and 2.7-3.6V for SST39VF512/010/020/0401 Limits Symbol Parameter IDD Power Supply Current Min Max Units Test Conditions Address input=VILT/VIHT, at f=1/TRC Min VDD=VDD Max Read2 20 mA CE#=VIL, OE#=WE#=VIH, all I/Os open Program and Erase3 30 mA CE#=WE#=VIL, OE#=VIH ISB Standby VDD Current 15 µA CE#=VIHC, VDD=VDD Max ILI Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max ILO Output Leakage Current 10 µA VOUT=GND to VDD, VDD=VDD Max VIL Input Low Voltage 0.8 V VDD=VDD Min VIH Input High Voltage 0.7VDD V VDD=VDD Max VIHC Input High Voltage (CMOS) VDD-0.3 V VDD=VDD Max VOL Output Low Voltage VOH Output High Voltage 0.2 VDD-0.2 V IOL=100 µA, VDD=VDD Min V IOH=-100 µA, VDD=VDD Min T5.7 1150 1. Typical conditions for the Active Current shown on the front data sheet page are average values at 25°C (room temperature), and VDD = 3V for VF devices. Not 100% tested. 2. Values are for 70 ns conditions. See the Multi-Purpose Flash Power Rating application note for further information. 3. 30 mA max for Erase operations in the industrial temperature range. TABLE 6: Recommended System Power-up Timings Symbol Parameter Minimum Units TPU-READ1 Power-up to Read Operation 100 µs Power-up to Program/Erase Operation 100 µs TPU-WRITE 1 T6.1 1150 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 7: Capacitance (Ta = 25°C, f=1 Mhz, other pins open) Parameter CI/O 1 CIN1 Description Test Condition Maximum I/O Pin Capacitance VI/O = 0V 12 pF Input Capacitance VIN = 0V 6 pF T7.0 1150 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: Reliability Characteristics Symbol Parameter Minimum Specification Units Test Method NEND1,2 Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78 T8.3 1150 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. NEND endurance rating is qualified as a 10,000 cycle minimum for the whole device. A sector- or block-level rating would result in a higher minimum specification. ©2010 Silicon Storage Technology, Inc. S71150-14-000 8 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet AC CHARACTERISTICS TABLE 9: Read Cycle Timing Parameters - VDD = 3.0-3.6V for SST39LF512/010/020/040 and 2.7-3.6V for SST39VF512/010/020/040 SST39LF512-45 SST39LF010-45 SST39LF020-45 SST39LF040-45 SST39LF020-55 SST39LF040-55 Min Min Symbol Parameter Max 45 SST39VF512-70 SST39VF010-70 SST39VF020-70 SST39VF040-70 Max Min 55 Max Units TRC Read Cycle Time TCE Chip Enable Access Time TAA Address Access Time 45 55 70 ns TOE Output Enable Access Time 30 30 35 ns TCLZ1 CE# Low to Active Output 0 0 0 ns TOLZ1 OE# Low to Active Output 0 0 0 ns 45 70 55 ns 70 ns 1 CE# High to High-Z Output 15 15 25 ns TOHZ1 OE# High to High-Z Output 15 15 25 ns TOH1 Output Hold from Address Change TCHZ 0 0 0 ns T9.2 1150 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: Program/Erase Cycle Timing Parameters Symbol Parameter TBP Byte-Program Time TAS Address Setup Time 0 ns TAH Address Hold Time 30 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns TCPH1 CE# Pulse Width High 30 ns TDS Data Setup Time 40 ns TDH1 Data Hold Time 0 ns 1 Min Max Units 20 µs Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TSCE Chip-Erase 100 ms TIDA T10.1 1150 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2010 Silicon Storage Technology, Inc. S71150-14-000 9 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet TRC TAA ADDRESS AMS-0 TCE CE# TOE OE# TOHZ TOLZ VIH WE# TCLZ DQ7-0 Note: TOH HIGH-Z TCHZ DATA VALID HIGH-Z DATA VALID 1150 F03.0 AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 FIGURE 6: Read Cycle Timing Diagram INTERNAL PROGRAM OPERATION STARTS TBP 5555 ADDRESS AMS-0 2AAA 5555 ADDR TAH TDH TWP WE# TAS TDS TWPH OE# TCH CE# TCS DQ7-0 Note: AA 55 A0 DATA SW0 SW1 SW2 BYTE (ADDR/DATA) 1150 F04.0 AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 FIGURE 7: WE# Controlled Program Cycle Timing Diagram ©2010 Silicon Storage Technology, Inc. S71150-14-000 10 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet INTERNAL PROGRAM OPERATION STARTS TBP 5555 ADDRESS AMS-0 2AAA 5555 ADDR TAH TDH TCP CE# TAS TDS TCPH OE# TCH WE# TCS DQ7-0 Note: AA 55 A0 DATA SW0 SW1 SW2 BYTE (ADDR/DATA) 1150 F05.0 AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 FIGURE 8: CE# Controlled Program Cycle Timing Diagram ADDRESS AMS-0 TCE CE# TOEH TOES OE# TOE WE# D DQ7 Note: D# D# AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 D 1150 F06.0 FIGURE 9: Data# Polling Timing Diagram ©2010 Silicon Storage Technology, Inc. S71150-14-000 11 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet ADDRESS AMS-0 TCE CE# TOEH TOES TOE OE# WE# DQ6 TWO READ CYCLES Note: WITH SAME OUTPUTS AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020 and A18 for SST39LF/VF040 1150 F07.0 FIGURE 10: Toggle Bit Timing Diagram TSE SIX-BYTE CODE FOR SECTOR-ERASE 5555 ADDRESS AMS-0 2AAA 5555 5555 2AAA SAX CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 30 SW0 SW1 SW2 SW3 SW4 SW5 1150 F08.0 Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are interchageable as long as minmum timings are met. (See Table 10) SAX = Sector Address AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040 FIGURE 11: WE# Controlled Sector-Erase Timing Diagram ©2010 Silicon Storage Technology, Inc. S71150-14-000 12 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESS AMS-0 5555 2AAA 5555 5555 2AAA 5555 CE# OE# TWP WE# DQ7-0 AA 55 80 AA 55 10 SW0 SW1 SW2 SW3 SW4 SW5 1150 F17.0 Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are interchageable as long as minmum timings are met. (See Table 10) AMS = Most significant address AMS = A15 for SST39LF/VF512, A16 for SST39LF/VF010, A17 for SST39LF/VF020, and A18 for SST39LF/VF040 FIGURE 12: WE# Controlled Chip-Erase Timing Diagram Three-byte Sequence for Software ID Entry ADDRESS A14-0 5555 2AAA 5555 0000 0001 CE# OE# TIDA TWP WE# TWPH DQ7-0 TAA AA 55 90 SW0 SW1 SW2 BF Device ID 1150 F09.2 Note: Device ID = D4H for SST39LF/VF512, D5H for SST39LF/VF010, D6H for SST39LF/VF020, and D7H for SST39LF/VF040. FIGURE 13: Software ID Entry and Read ©2010 Silicon Storage Technology, Inc. S71150-14-000 13 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 ADDRESS A14-0 2AAA AA DQ7-0 5555 55 F0 TIDA CE# OE# TWP WE# TWHP SW0 SW1 SW2 1150 F10.0 FIGURE 14: Software ID Exit and Reset VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 1150 F12.1 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 15: AC Input/Output Reference Waveforms TO TESTER TO DUT CL 1150 F11.1 FIGURE 16: A Test Load Example ©2010 Silicon Storage Technology, Inc. S71150-14-000 14 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Start Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 1150 F13.1 FIGURE 17: Byte-Program Algorithm ©2010 Silicon Storage Technology, Inc. S71150-14-000 15 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Internal Timer Toggle Bit Data# Polling Byte-Program/ Erase Initiated Byte-Program/ Erase Initiated Byte-Program/ Erase Initiated Read byte Read DQ7 Wait TBP, TSCE, or TSE Read same byte Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 1150 F14.0 FIGURE 18: Wait Options ©2010 Silicon Storage Technology, Inc. S71150-14-000 16 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Software ID Entry Command Sequence Software ID Exit & Reset Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: F0H Address: XXH Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Wait TIDA Load data: 90H Address: 5555H Load data: F0H Address: 5555H Return to normal operation Wait TIDA Wait TIDA Read Software ID Return to normal operation 1150 F15.2 FIGURE 19: Software ID Command Flowcharts ©2010 Silicon Storage Technology, Inc. S71150-14-000 17 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Chip-Erase Command Sequence Sector-Erase Command Sequence Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 80H Address: 5555H Load data: 80H Address: 5555H Load data: AAH Address: 5555H Load data: AAH Address: 5555H Load data: 55H Address: 2AAAH Load data: 55H Address: 2AAAH Load data: 10H Address: 5555H Load data: 30H Address: SAX Wait TSCE Wait TSE Chip erased to FFH Sector erased to FFH 1150 F16.1 FIGURE 20: Erase Command Sequence ©2010 Silicon Storage Technology, Inc. S71150-14-000 18 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet PRODUCT ORDERING INFORMATION SST 39 XX LF 040 XX XXXX - 45 - XXX - 4C XX NH - XXX E X Environmental Attribute E1 = non-Pb Package Modifier H = 32 leads K = 48 balls M = 34 balls (54 possible positions) Package Type B3 = TFBGA (0.8mm pitch, 6mm x 8mm) N = PLCC M = WFBGA (0.5mm pitch, 4mm x 6mm) W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0°C to +70°C I = Industrial = -40°C to +85°C Minimum Endurance 4 = 10,000 cycles Read Access Speed 45 = 45 ns 55 = 55 ns 70 = 70 ns Device Density 040 = 4 Mbit 020 = 2 Mbit 010 = 1 Mbit 512 = 512 Kbit Voltage L = 3.0-3.6V V = 2.7-3.6V Product Series 39 = Multi-Purpose Flash 1. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are RoHS compliant. ©2010 Silicon Storage Technology, Inc. S71150-14-000 19 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet Valid combinations for SST39LF512 SST39LF512-45-4C-NHE SST39LF512-45-4C-WHE Valid combinations for SST39VF512 SST39VF512-70-4C-NHE SST39VF512-70-4C-WHE SST39VF512-70-4I-NHE SST39VF512-70-4I-WHE Valid combinations for SST39LF010 SST39LF010-45-4C-NHE SST39LF010-45-4C-WHE SST39LF010-45-4C-B3KE SST39LF010-45-4C-MME Valid combinations for SST39VF010 SST39VF010-70-4C-NHE SST39VF010-70-4C-WHE SST39VF010-70-4C-B3KE SST39VF010-70-4I-NHE SST39VF010-70-4I-WHE SST39VF010-70-4I-B3KE Valid combinations for SST39LF020 SST39LF020-45-4C-NHE SST39LF020-45-4C-WHE SST39LF020-55-4C-NHE SST39LF020-55-4C-WHE SST39LF020-45-4C-B3KE SST39LF020-45-4C-MME Valid combinations for SST39VF020 SST39VF020-70-4C-NHE SST39VF020-70-4C-WHE SST39VF020-70-4C-B3KE SST39VF020-70-4I-NHE SST39VF020-70-4I-WHE SST39VF020-70-4I-B3KE Valid combinations for SST39LF040 SST39LF040-45-4C-NHE SST39LF040-45-4C-WHE SST39LF040-55-4C-NHE SST39LF040-55-4C-WHE SST39LF040-45-4C-B3KE Valid combinations for SST39VF040 SST39VF040-70-4C-NHE SST39VF040-70-4C-WHE SST39VF040-70-4C-B3KE SST39VF040-70-4I-NHE SST39VF040-70-4I-WHE SST39VF040-70-4I-B3KE Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2010 Silicon Storage Technology, Inc. S71150-14-000 20 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet PACKAGING DIAGRAMS TOP VIEW SIDE VIEW .495 .485 .453 .447 Optional Pin #1 Identifier .048 .042 2 1 32 .112 .106 .020 R. MAX. .029 x 30˚ .023 .040 R. .030 .042 .048 .595 .553 .585 .547 BOTTOM VIEW .021 .013 .400 .530 BSC .490 .032 .026 .050 BSC .015 Min. .095 .075 .050 BSC .032 .026 .140 .125 Note: 1. Complies with JEDEC publication 95 MS-016 AE dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in inches (max/min). 3. Dimensions do not include mold flash. Maximum allowable mold flash is .008 inches. 4. Coplanarity: 4 mils. 32-plcc-NH-3 FIGURE 21: 32-lead Plastic Lead Chip Carrier (PLCC) SST Package Code: NH TOP VIEW BOTTOM VIEW 8.00 ± 0.20 5.60 0.45 ± 0.05 (48X) 0.80 6 6 5 5 4.00 4 4 6.00 ± 0.20 3 3 2 2 1 1 0.80 A B C D E F G H A1 CORNER SIDE VIEW H G F E D C B A A1 CORNER 1.10 ± 0.10 0.12 SEATING PLANE 1mm 0.35 ± 0.05 Note: 1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.12 mm 4. Ball opening size is 0.38 mm (± 0.05 mm) 48-tfbga-B3K-6x8-450mic-4 FIGURE 22: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm SST Package Code: B3K ©2010 Silicon Storage Technology, Inc. S71150-14-000 21 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet 1.05 0.95 Pin # 1 Identifier 0.50 BSC 8.10 7.90 0.27 0.17 0.15 0.05 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0˚- 5˚ 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 32-tsop-WH-7 FIGURE 23: 32-lead Thin Small Outline Package (TSOP) 8mm x 14mm SST Package Code: WH ©2010 Silicon Storage Technology, Inc. S71150-14-000 22 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet TOP VIEW BOTTOM VIEW 6.00 ± 0.08 4.00 0.50 6 5 4 3 2 1 4.00 ± 0.08 0.50 J H G F E D C B A A1 INDICATOR4 A1 CORNER DETAIL 6 5 4 3 2 1 2.50 A B C D E F G H J 0.32 ± 0.05 (34X) 0.63 ± 0.10 SIDE VIEW 0.08 SEATING PLANE 0.20 ± 0.06 Note: 1mm 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-225, this specific package is not registered. 2. All linear dimensions are in millimeters. 3. Coplanarity: 0.08 mm 4. No ball is present in position A1; a gold-colored indicator is present. 34-wfbga-MM-4x6-32mic-1 5. Ball opening size is 0.29 mm (± 0.05 mm) FIGURE 24: 34-ball Very-very-thin-profile, Fine-pitch Ball Grid Array (WFBGA) 4mm x 6mm x .63mm SST Package Code: MM ©2010 Silicon Storage Technology, Inc. S71150-14-000 23 01/10 512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash SST39LF512 / SST39LF010 / SST39LF020 / SST39LF040 SST39VF512 / SST39VF010 / SST39VF020 / SST39VF040 Data Sheet TABLE 11: Revision History Number Description Date 01 • 2000 Data Book Feb 2000 02 • Changed speed from 45 ns to 55 ns for the SST39LF020 and SST39LF040 Aug 2000 03 • 2002 Data Book: Reintroduced the 45 ns parts for the SST39LF020 and SST39LF040 Feb 2002 04 • • Added the B3K package for the 2 Mbit devices Added footnote in Table 5 to indicate IDD Write is 30 mA max for Erase operations in the Industrial temperature range. 05 • Changes to Table 5 on page 8 – Added footnote for MPF power usage and Typical conditions – Clarified the Test Conditions for Power Supply Current and Read parameters – Clarified IDD Write to be Program and Erase – Corrected IDD Program and Erase from 20 mA to 30 mA • Part number changes - see page 20 for additional information Oct 2002 Mar 2003 06 • Added new “MM” Micro-Package MPNs for 1M and 2M LF parts- see page 20 Oct 2003 07 • • • 2004 Data Book Added non-Pb MPNs and removed footnote (See page 20) Updated B3K and MM package diagrams Nov 2003 08 • • • • • Added RoHS Compliant statement. Added 4 MBit to Figure 4. Revised Absolute Max Stress Ratings for Surface Mount Solder Reflow Temperature Removed SST39VFxxx-90 Timing Parameters from Figure 9. Added Footnote and removed Read Access Speed 90 = 90 to Product Ordering Information. Removed 90 part numbers Valid Combinations lists Dec 2005 • 09 • Edited page Valid Combinations on page 21. Changed 39LF040-70-4C-B3KE to 39LF040-45-4C-B3KE Jan 2006 10 • Removed leaded parts Nov 2008 11 • Added package YME Feb 2009 12 • Revised “Product Ordering Information” on page 19 Apr 2009 13 • Changed endurance from 10,000 to 100,000 in Product Description, page 1 Sep 2009 14 • EOL of SST39LF010-45-4C-YME. Replacement part is SST39LF010-45-4C-MME in this document. Removed all references to the YME package. Jan 2010 • Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2010 Silicon Storage Technology, Inc. S71150-14-000 24 01/10