SST SST39VF800-90-4C-EK

8 Megabit (512K x 16-Bit) Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
FEATURES:
• Organized as 512 K X 16
• Latched Address and Data
• Single 2.7-3.6V Read and Write Operations
• Fast Sector Erase and Word Program:
- Sector Erase Time: 18 ms (typical)
- Block Erase Time: 18 ms (typical)
- Chip Erase Time: 70 ms (typical)
- Word Program time: 14 µs (typical)
- Chip Rewrite Time: 8 seconds (typical)
• Automatic Write Timing
- Internal VPP Generation
• End of Write Detection
- Toggle Bit
- Data# Polling
• CMOS I/O Compatibility
• VDDQ Power Supply to Support 5V I/O
for SST39VF800Q
- VDDQ not available on SST39VF800
• Superior Reliability
- Endurance: 100,000 Cycles (typical)
- Greater than 100 years Data Retention
• Low Power Consumption:
- Active Current: 15 mA (typical)
- Standby Current: 3 µA (typical)
- Auto Low Power Mode: 3 µA (typical)
• Small Sector Erase Capability (256 sectors)
- Uniform 2 KWord sectors
• Block Erase Capability (16 blocks)
- Uniform 32 KWord blocks
• Fast Read Access Time:
- 70 and 90 ns
PRODUCT DESCRIPTION
The SST39VF800Q/VF800 devices are 512K x 16
CMOS Multi-Purpose Flash (MPF) manufactured with
SST’s proprietary, high performance CMOS SuperFlash
technology. The split-gate cell design and thick oxide
tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST39VF800Q/VF800 write (Program or Erase)
with a 2.7-3.6V power supply. The SST39VF800Q/
VF800 conform to JEDEC standard pinouts for x16
memories.
Featuring high performance word program, the
SST39VF800Q/VF800 devices provide a typical word
program time of 14 µsec. The entire memory can typically be erased and programmed word-by-word in 8
seconds, when using interface features such as Toggle
Bit or Data# Polling to indicate the completion of Program
operation. To protect against inadvertent write, the
SST39VF800Q/VF800 have on-chip hardware and software data protection schemes. Designed, manufactured, and tested for a wide spectrum of applications, the
SST39VF800Q/VF800 are offered with a guaranteed
endurance of 10,000 cycles. Data retention is rated at
greater than 100 years.
The SST39VF800Q/VF800 devices are suited for applications that require convenient and economical updating
of program, configuration, or data memory. For all system applications, the SST39VF800Q/VF800 significantly improve performance and reliability, while lowering power consumption. The SST39VF800Q/VF800 in-
• JEDEC Standard
- Flash EEPROM Pinouts and command sets
• Packages Available
- 48-Pin TSOP (12mm x 20mm)
- 6 x 8 Ball TFBGA
herently use less energy during Erase and Program than
alternative flash technologies. The total energy consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed
during any Erase or Program operation is less than
alternative flash technologies. The SST39VF800Q/
VF800 also improve flexibility while lowering the cost for
program, data, and configuration storage applications.
The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/
Program cycles that have occurred. Therefore the system software or hardware does not have to be modified
or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with
accumulated Erase/Program cycles.
To meet high density, surface mount requirements, the
SST39VF800Q/VF800 are offered in 48-pin TSOP and
48-pin TFBGA packages. See Figures 1 and 2 for
pinouts.
Device Operation
Commands are used to initiate the memory operation
functions of the device. Commands are written to the
device using standard microprocessor write sequences.
A command is written by asserting WE# low while
keeping CE# low. The address bus is latched on the
falling edge of WE# or CE#, whichever occurs last. The
data bus is latched on the rising edge of WE# or CE#,
whichever occurs first.
© 1999 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc.
343-04 2/99
These specifications are subject to change without notice.
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8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
The SST39VF800Q/VF800 also have the Auto Low
Power mode which puts the device in a near standby mode
after data has been accessed with a valid read operation.
This reduces the IDD active read current from typically 15
mA to typically 3 µA. The Auto Low Power mode reduces
the typical IDD active read current to the range of 1 mA/MHz
of read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transition used to initiate another read cycle, with no access time
penalty.
byte command sequence with Block Erase command
(50H) and block address (BA) in the last bus cycle. The
address lines A15-A18 are used to determine the block
address. The sector or block address is latched on the
falling edge of the sixth WE# pulse, while the command
(30H or 50H) is latched on the rising edge of the sixth WE#
pulse. The internal Erase operation begins after the sixth
WE# pulse. The end of Erase operation can be determined
using either Data# Polling or Toggle Bit methods. See
Figures 9 and 10 for timing waveforms. Any commands
issued during the Sector or Block Erase operation are
ignored.
Read
The Read operation of the SST39VF800Q/VF800 is controlled by CE# and OE#, both have to be low for the system
to obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when either CE# or OE# is high.
Refer to the Read cycle timing diagram for further details
(Figure 3).
Chip Erase Operation
The SST39VF800Q/VF800 provide a Chip Erase operation, which allows the user to erase the entire memory array
to the “1” state. This is useful when the entire device must
be quickly erased.
The Chip Erase operation is initiated by executing a sixbyte command sequence with Chip Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid read is Toggle Bit or Data# Polling.
See Table 4 for the command sequence, Figure 8 for timing
diagram, and Figure 19 for the flowchart. Any commands
issued during the Chip Erase operation are ignored.
Word Program Operation
The SST39VF800Q/VF800 are programmed on a wordby-word basis. The Program operation consists of three
steps. The first step is the three-byte load sequence for
Software Data Protection. The second step is to load word
address and word data. During the Word Program operation, the addresses are latched on the falling edge of either
CE# or WE#, whichever occurs last. The data is latched on
the rising edge of either CE# or WE#, whichever occurs
first. The third step is the internal Program operation which
is initiated after the rising edge of the fourth WE# or CE#,
whichever occurs first. The Program operation, once initiated, will be completed within 20 µs. See Figures 4 and 5
for WE# and CE# controlled Program operation timing
diagrams and Figure 16 for flowcharts. During the Program operation, the only valid reads are Data# Polling and
Toggle Bit. During the internal Program operation, the host
is free to perform additional tasks. Any commands issued
during the internal Program operation are ignored.
Write Operation Status Detection
The SST39VF800Q/VF800 provide two software means
to detect the completion of a write (Program or Erase)
cycle, in order to optimize the system write cycle time. The
software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The end of write detection
mode is enabled after the rising edge of WE#, which
initiates the internal program or erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to
conflict with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an
additional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the rejection is valid.
Sector/Block Erase Operation
The Sector/Block Erase operation allows the system to
erase the device on a sector-by-sector (or block-by-block)
basis. The SST39VF800Q/VF800 offer both small Sector
Erase and Block Erase mode. The sector architecture is
based on uniform sector size of 2 KWord. The Block Erase
mode is based on uniform block size of 32 KWord. The
Sector Erase operation is initiated by executing a six-bytecommand sequence with Sector Erase command (30H)
and sector address (SA) in the last bus cycle. The address
lines A11-A18 are used to determine the sector address.
The Block Erase operation is initiated by executing a six© 1999 Silicon Storage Technology, Inc.
Data# Polling (DQ7)
When the SST39VF800Q/VF800 are in the internal Program operation, any attempt to read DQ7 will produce the
complement of the true data. Once the Program operation
is completed, DQ7 will produce true data. The device is
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343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
Common Flash Memory Interface (CFI)
The SST39VF800Q/VF800 also contain the CFI information to describe the characteristics of the device. In order to
enter the CFI Query mode, the system must write threebyte sequence, same as product ID entry command with
98H (CFI Query command) to address 5555H in the last
byte sequence. Once the device enters the CFI Query
mode, the system can read CFI data at the addresses given
in tables 5 through 7. The system must write the CFI Exit
command to return to Read mode from the CFI Query
mode.
then ready for the next operation. During internal Erase
operation, any attempt to read DQ7 will produce a ‘0’. Once
the internal Erase operation is completed, DQ7 will produce a ‘1’. The Data# Polling is valid after the rising edge
of fourth WE# (or CE#) pulse for Program operation. For
Sector, Block or Chip Erase, the Data# Polling is valid after
the rising edge of sixth WE# (or CE#) pulse. See Figure 6
for Data# Polling timing diagram and Figure 17 for a
flowchart.
Toggle Bit (DQ6)
During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1’s
and 0’s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next operation. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector,
Block or Chip Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle
Bit timing diagram and Figure 17 for a flowchart.
Product Identification
The Product Identification mode identifies the devices as
the SST39VF800Q, SST39VF800 and manufacturer as
SST. This mode may be accessed by hardware or software
operations. The hardware operation is typically used by a
programmer to identify the correct algorithm for the
SST39VF800Q/VF800. Users may wish to use the Software Product Identification operation to identify the part
(i.e., using the device code) when using multiple manufacturers in the same socket. For details, see Table 3 for
hardware operation or Table 4 for software operation,
Figure 11 for the Software ID Entry and Read timing
diagram and Figure 18 for the ID Entry command sequence
flowchart.
TABLE 1: PRODUCT IDENTIFICATION TABLE
Data Protection
The SST39VF800Q/VF800 provide both hardware and
software features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Data
Manufacturer’s Code
0000H
00BFH
Device Code
0001H
2781H
343 PGM T1.0
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read operation.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/CFI
Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command codes,
Figure 13 for timing waveform and Figure 18 for a flowchart.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39VF800Q/VF800 provide the JEDEC approved
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. The SST39VF800Q/VF800 devices
are shipped with the software data protection permanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid commands will abort the device to read mode within TRC. The
contents of DQ15-DQ8 are “Don’t Care” during any SDP
command sequence.
© 1999 Silicon Storage Technology, Inc.
Address
VDDQ - I/O Power Supply
This feature is available only on the SST39VF800Q. This
pin functions as power supply pin for input/output buffers. It
should be tied to VDD (2.7-3.6V) in a 3.0V-only system. It
should be tied to a 5.0V±10% (4.5-5.5V) power supply in a
mixed voltage system environment where flash memory
has to be interfaced with 5V system chips. The VDDQ pin is
not offered on the SST39VF800, instead it is a No Connect
pin.
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8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
FUNCTIONAL BLOCK DIAGRAM
8,388,608 bit
EEPROM
Cell Array
X-Decoder
A18 - A0
Address Buffer & Latches
Y-Decoder
CE#
I/O Buffers and Data Latches
Control Logic
OE#
WE#
DQ15 - DQ0 VDDQ
343 ILL B1.0
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Standard Pinout
Top View
Die Up
SST39VF800Q
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
NC
NC
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
VDDQ
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Standard Pinout
Top View
Die Up
SST39VF800
343 ILL1.0
A16
NC
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VDD
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
343 ILL1a.0
FIGURE 1: PIN ASSIGNMENTS FOR 48-PIN TSOP PACKAGES
A
B
C
D
E
F
A
B
C
D
E
F
TOP
VIEW
TOP
VIEW
1
1
A3
A7
NC
WE#
A9
A13
2
A4
A17
NC
NC
A8
A12
3
A2
A6
A18
NC
A10
A14
A1
A5
NC
NC
A11
A15
NC
WE#
A9
A13
A4
A17
NC
NC
A8
A12
A2
A6
A18
NC
A10
A14
A0
DQ0
DQ2 DQ5 DQ7
A16
A1
A5
NC
NC
A11
A15
A0
DQ0
DQ2 DQ5 DQ7
A16
CE# DQ8 DQ10 DQ12 DQ14
NC
4
5
5
6
8
A7
3
4
7
A3
2
6
CE# DQ8 DQ10 DQ12 DQ14 VDDQ
7
OE# DQ9 DQ11 VDD DQ13 DQ15
VSS DQ1
DQ3 DQ4 DQ6
8
VSS
OE# DQ9 DQ11 VDD DQ13 DQ15
VSS DQ1
SST39VF800Q
DQ3 DQ4 DQ6
VSS
SST39VF800
343 ILL2.3
343 ILL2a.2
FIGURE 2: PIN ASSIGNMENTS FOR 48-BALL TFBGA
© 1999 Silicon Storage Technology, Inc.
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343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
A18-A0
Address Inputs
DQ15-DQ0
Data Input/output
CE#
OE#
WE#
VDD
VDDQ
Chip Enable
Output Enable
Write Enable
Power Supply
I/O Power Supply
Vss
NC
Functions
To provide memory addresses. During sector erase A18-A11 address lines
will select the sector. During block erase A18-A15 address lines will select
the block.
To output data during read cycles and receive input data during write
cycles. Data is internally latched during a write cycle. The outputs are in
tri-state when OE# or CE# is high.
To activate the device when CE# is low.
To gate the data output buffers.
To control the write operations.
To provide 3-volt supply (2.7-3.6V)
Supplies power for input/output buffers. It should be either tied to VDD
(2.7 - 3.6V) for 3V I/O or to a 5.0V (4.5 - 5.5V) power supply to
support 5V I/O. (Not offered on SST39VF800 device, instead it is a NC)
Ground
No Connection
Unconnected pins.
343 PGM T2.0
TABLE 3: OPERATION MODES SELECTION
Mode
CE#
OE#
Read
VIL
VIL
Program
VIL
VIH
Erase
VIL
VIH
Standby
Write Inhibit
Product Identification
Hardware Mode
Software Mode
1
2
3
4
5
6
7
WE#
VIH
VIL
VIL
A9
AIN
AIN
X
DQ
DOUT
DIN
X
VIH
X
X
X
VIL
X
X
X
VIH
X
X
X
High Z
High Z/ DOUT
High Z/ DOUT
VIL
VIL
VIH
VH
Manufacturer Code (00BF)
Device Code (2781)
VIL
VIL
VIH
AIN
Address
AIN
AIN
Sector or block address,
XXh for chip erase
X
X
X
A18 - A1 = VIL, A0 = VIL
A18 - A1 = VIL, A0 = VIH
See Table 4
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343 PGM T3.0
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© 1999 Silicon Storage Technology, Inc.
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343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
Word Program
Sector Erase
Block Erase
Chip Erase
Software ID Entry
CFI Query Entry
Software ID Exit/
CFI Exit
Software ID Exit/
CFI Exit
1st Bus
Write Cycle
Addr(1) Data
2nd Bus
Write Cycle
Addr(1) Data
3rd Bus
Write Cycle
Addr(1) Data
4th Bus
Write Cycle
Addr(1) Data
5th Bus
Write Cycle
Addr(1) Data
6th Bus
Write Cycle
Addr(1) Data
5555H
5555H
5555H
5555H
5555H
5555H
XXH
AAH
AAH
AAH
AAH
AAH
AAH
F0H
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
2AAAH
55H
55H
55H
55H
55H
55H
5555H
5555H
5555H
5555H
5555H
5555H
A0H
80H
80H
80H
90H
98H
WA(3)
5555H
5555H
5555H
2AAAH
2AAAH
2AAAH
SAx(2)
BAx(2)
5555H
5555H
AAH
2AAAH
55H
5555H
F0H
Data
AAH
AAH
AAH
55H
55H
55H
30H
50H
10H
343 PGM T4.0
Notes:
(1)
(2)
(3)
(4)
(5)
Address format A14-A0 (Hex), Addresses A15, A16, A17 and A18 are “Don’t Care” for Command sequence.
SAx for Sector Erase; uses A18-A11 address lines
BAx, for Block Erase; uses A18-A15 address lines
WA = Program word address
Both Software ID Exit operations are equivalent
DQ15 - DQ8 are “Don’t Care” for Command sequence
Notes for Software ID Entry Command Sequence
1. With A18 -A1 =0; SST Manufacturer Code = 00BFH, is read with A0 = 0,
SST39VF800Q/VF800 Device Code = 2781H, is read with A0 = 1.
2. The device does not remain in Software Product ID Mode if powered down.
TABLE 5: CFI QUERY IDENTIFICATION STRING1
Address
Data
Data
10H
0051H
11H
0052H
Query Unique ASCII string “QRY”
12H
0059H
13H
0001H
Primary OEM command set
14H
0007H
15H
0000H
Address for Primary Extended Table
16H
0000H
17H
0000H
Alternate OEM command set (00H = none exists)
18H
0000H
19H
0000H
Address for Alternate OEM extended Table (00H = none exits)
1AH
0000H
Note 1: Refer to CFI publication 100 for more details.
© 1999 Silicon Storage Technology, Inc.
343 PGM T5.1
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8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
TABLE 6: SYSTEM INTERFACE INFORMATION
Address
Data
Data
1BH
0027H
VDD Min. (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: millivolts
1CH
0036H
VDD Max. (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: millivolts
1DH
0000H
VPP min. (00H = no VPP pin)
1EH
0000H
VPP max. (00H = no VPP pin)
1FH
0004H
Typical time out for Word Program 2N µs (24 = 16 µs)
20H
0000H
Typical time out for min. size buffer program 2N µs (00H = not supported)
21H
0004H
Typical time out for individual Sector/Block Erase 2N ms (24 = 16 ms)
22H
0006H
Typical time out for Chip Erase 2N ms (26 = 64 ms)
23H
24H
25H
0001H
0000H
0001H
26H
0001H
1
2
3
4
Maximum time out for Word Program 2N times typical (21 x 24 = 32 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector/Block Erase 2N times typical
(21 x 24 = 32 ms)
Maximum time out for Chip Erase 2N times typical (21 x 26 = 128 ms)
5
6
343 PGM T6.2
7
TABLE 7: DEVICE GEOMETRY INFORMATION
Address
Data
Data
27H
0014H
Device size = 2N Bytes (14H = 20; 220 = 1M Bytes)
28H
0001H
Flash Device Interface description; 0001H = x16-only asynchronous interface
29H
0000H
2AH
0000H
Maximum number of byte in multi-byte write = 2N (00H = not supported)
2BH
0000H
2CH
0002H
Number of Erase Sector/Block sizes supported by device
2DH
00FFH
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
2EH
0000H
y = 255 + 1 = 256 sectors (00FFH = 255)
2FH
0010H
30H
0000H
z = 16 x 256 Bytes = 4 KBytes/sector (0010H = 16)
31H
000FH
Block Information (y + 1 = Number of blocks; z x 256B = block size)
32H
0000H
y = 15 + 1 = 16 blocks (000FH = 15)
33H
0000H
34H
0001H
z = 256 x 256 Bytes = 64 KBytes/block (0100H = 256)
343 PGM T7.2
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© 1999 Silicon Storage Technology, Inc.
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343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress
Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias ................................................................................................................. -55°C to +125°C
Storage Temperature ...................................................................................................................... -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential ...................................................................... -0.5V to VDDQ (2) + 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential .................................................. -1.0V to VDDQ (2) + 1.0V
Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) ........................................................................................... 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C
Output Short Circuit Current(1) ................................................................................................................................................................. 50 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
(2) The absolute maximum stress ratings for SST39VF800 are referenced to V .
DD
OPERATING RANGE
Range
Ambient Temp
Commercial
0 °C to +70 °C
Industrial
-40 °C to +85 °C
VDD
2.7 - 3.6V
2.7 - 3.6V
VDDQ
VDD or 4.5 - 5.5V
VDD or 4.5 - 5.5V
AC CONDITIONS OF TEST
Input Rise/Fall Time ......... 10 ns
Output Load ..................... CL = 100 pF
See Figures 14 and 15
© 1999 Silicon Storage Technology, Inc.
8
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
TABLE 8: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V AND VDDQ = VDD OR 4.5V - 5.5V
Limits
Symbol Parameter
Min
Max
Units
Test Conditions
IDD
ISB
IALP
ILI
ILO
VIL
VILC
VIH
VIHC
VOL
VOH
VH
IH
Power Supply Current
Read
Program and Erase
Standby VDD Current
Auto Low Power Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input Low Voltage (CMOS)
0.3
Input High Voltage
2.0
Input High Voltage (CMOS) VDD-0.3
Output Low Voltage
Output High Voltage
2.4
Supervoltage for A9 pin
11.4
Supervoltage Current
for A9 pin
20
25
10
10
1
1
0.8
0.4
12.6
200
1
CE#=OE#=VIL,WE#=VIH , all I/Os open,
Address input = VIL/VIH, at f=1/TRC Min.
CE#=WE#=VIL, OE#=VIH, VDD=VDD Max.
CE#=VIHC, VDD = VDD Max.
CE#=VIHC, VDD = VDD Max.
VIN =GND to VDD, VDD = VDD Max.
VOUT =GND to VDD, VDD = VDD Max.
VDD = VDD Min.
VDD = VDD Max.
VDD = VDD Max.
VDD = VDD Max.
IOL = 100 µA, VDD = VDD Min.
IOH = -100 µA, VDD = VDD Min.
CE# = OE# =VIL, WE# = VIH
CE# = OE# = VIL, WE# = VIH, A9 = VH Max.
mA
mA
µA
µA
µA
µA
V
V
V
V
V
V
V
µA
2
3
4
5
6
7
343 PGM T9.1
TABLE 9: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
TPU-READ(1)
TPU-WRITE(1)
Power-up to Read Operation
Power-up to Program/Erase
Operation
Minimum
Units
100
100
µs
µs
8
9
343 PGM T10.0
TABLE 10: CAPACITANCE (Ta = 25 °C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
(1)
CI/O
CIN
(1)
Maximum
I/O Pin Capacitance
VI/O = 0V
12 pF
Input Capacitance
VIN = 0V
6 pF
11
343 PGM T11.1
Note: (1) This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
(1)
NEND
TDR(1)
VZAP_HBM(1)
VZAP_MM(1)
ILTH(1)
Endurance
Data Retention
ESD Susceptibility
Human Body Model
ESD Susceptibility
Machine Model
Latch Up
Units
Test Method
10,000
100
1000
Cycles
Years
Volts
JEDEC Standard A117
JEDEC Standard A103
JEDEC Standard A114
200
Volts
JEDEC Standard A115
100 + IDD
mA
14
15
16
JEDEC Standard 78
Note: (1) This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
9
12
13
343 PGM T12.1
© 1999 Silicon Storage Technology, Inc.
10
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
AC CHARACTERISTICS
TABLE 12: SST39VF800Q/VF800 READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
SST39VF800Q/VF800-70 SST39VF800Q/VF800-90
Symbol
Parameter
Min
Max
Min
Max
TRC
Read Cycle time
70
90
TCE
Chip Enable Access Time
70
90
TAA
Address Access Time
70
90
TOE
Output Enable Access Time
30
40
(1)
TCLZ
CE# Low to Active Output
0
0
(1)
TOLZ
OE# Low to Active Output
0
0
TCHZ(1)
CE# High to High-Z Output
20
30
(1)
TOHZ
OE# High to High-Z Output
20
30
(1)
TOH
Output Hold from Address Change
0
0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
343 PGM T13.0
TABLE 13: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
Parameter
TBP
Word Program time
TAS
Address Setup Time
TAH
Address Hold Time
TCS
WE# and CE# Setup Time
TCH
WE# and CE# Hold Time
TOES
OE# High Setup Time
TOEH
OE# High Hold Time
TCP
CE# Pulse Width
TWP
WE# Pulse Width
TWPH (1)
WE# Pulse Width High
TCPH (1)
CE# Pulse Width High
TDS
Data Setup Time
TDH (1)
Data Hold Time
TIDA (1)
Software ID Access and Exit Time
TSE
Sector Erase
TBE
Block Erase
TSCE
Chip Erase
Min
Max
20
0
30
0
0
0
10
40
40
30
30
30
0
150
25
25
100
Units
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
343 PGM T14.1
Note 1: This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
© 1999 Silicon Storage Technology, Inc.
10
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
1
TAA
TRC
2
ADDRESS A18-0
TCE
CE#
3
TOE
OE#
4
TOHZ
TOLZ
VIH
WE#
TCLZ
HIGH-Z
DQ15-0
DATA VALID
5
TCHZ
TOH
HIGH-Z
DATA VALID
6
343 ILL3.0
7
FIGURE 3: READ CYCLE TIMING DIAGRAM
8
9
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
TAH
ADDRESS A18-0
2AAA
5555
10
ADDR
TDH
TWP
11
WE#
TAS
TDS
TWPH
12
OE#
TCH
13
CE#
TCS
DQ15-0
XXAA
SW0
XX55
XXA0
SW1
SW2
14
DATA
WORD
(ADDR/DATA)
343 ILL4.0
15
16
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
© 1999 Silicon Storage Technology, Inc.
11
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
INTERNAL PROGRAM OPERATION STARTS
TBP
5555
TAH
ADDRESS A18-0
2AAA
5555
ADDR
TDH
TCP
CE#
TAS
TDS
TCPH
OE#
TCH
WE#
TCS
DQ15-0
XXAA
XX55
XXA0
SW0
SW1
SW2
DATA
WORD
(ADDR/DATA)
343 ILL5.0
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A18-0
TCE
CE#
TOES
TOEH
OE#
TOE
WE#
DQ7
DATA
DATA#
DATA#
DATA
343 ILL6.1
FIGURE 6: DATA# POLLING TIMING DIAGRAM
© 1999 Silicon Storage Technology, Inc.
12
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
1
ADDRESS A18-0
2
TCE
CE#
TOES
TOE
TOEH
3
OE#
4
WE#
5
DQ6
6
TWO READ CYCLES
WITH SAME OUTPUTS
343 ILL7.1
7
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
8
9
TSCE
SIX-BYTE CODE FOR CHIP ERASE
ADDRESS A18-0
5555
2AAA
5555
5555
2AAA
10
5555
11
CE#
12
OE#
TWP
13
WE#
DQ7-0
AA
55
80
AA
55
10
SW0
SW1
SW2
SW3
SW4
SW5
14
343 ILL8.0
15
Note: The device also supports CE# controlled chip erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 13)
16
FIGURE 8: WE# CONTROLLED CHIP ERASE TIMING DIAGRAM
© 1999 Silicon Storage Technology, Inc.
13
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
TBE
SIX-BYTE CODE FOR BLOCK ERASE
5555
ADDRESS A18-0
2AAA
5555
5555
2AAA
BAX
CE#
OE#
TWP
WE#
DQ7-0
AA
55
80
AA
55
50
SW0
SW1
SW2
SW3
SW4
SW5
343 ILL17.0
Note: The device also supports CE# controlled block erase operation. The WE# and CE# signals are
interchangeable as long as minimum timings are met. (See Table 13)
BAX = Block Address
FIGURE 9: WE# CONTROLLED BLOCK ERASE TIMING DIAGRAM
TSE
SIX-BYTE CODE FOR SECTOR ERASE
5555
ADDRESS A18-0
2AAA
5555
5555
2AAA
SAX
CE#
OE#
TWP
WE#
DQ7-0
AA
55
80
AA
55
30
SW0
SW1
SW2
SW3
SW4
SW5
343 ILL18.0
Note: The device also supports CE# controlled sector erase operation. The WE# and CE# signals
are interchangeable as long as minimum timings are met. (See Table 13)
SAX = Sector Address
FIGURE 10: WE# CONTROLLED SECTOR ERASE TIMING DIAGRAM
© 1999 Silicon Storage Technology, Inc.
14
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
1
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
5555
ADDRESS A14-0
2AAA
5555
0000
2
0001
CE#
3
OE#
4
TIDA
TWP
5
WE#
TWPH
DQ15-0
XXAA
SW0
XX55
TAA
XX90
SW1
00BF
6
2781
SW2
343 ILL9.1
7
8
FIGURE 11: SOFTWARE ID ENTRY AND READ
9
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A14-0
5555
2AAA
10
5555
11
CE#
12
OE#
TIDA
TWP
13
WE#
TWPH
DQ15-0
XXAA
SW0
XX55
SW1
14
TAA
XX98
15
SW2
343 ILL20.1
16
FIGURE 12: CFI QUERY ENTRY AND READ
© 1999 Silicon Storage Technology, Inc.
15
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
ADDRESS A14-0
DQ7-0
5555
2AAA
AA
5555
55
F0
TIDA
CE#
OE#
TWP
WE#
T WHP
SW0
SW1
SW2
343 ILL10.0
FIGURE 13: SOFTWARE ID EXIT/CFI EXIT
© 1999 Silicon Storage Technology, Inc.
16
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
VIHT
VHT
INPUT
1
VHT
REFERENCE POINTS
OUTPUT
VLT
VLT
2
VILT
343 ILL11.0
AC test inputs are driven at VIHT (2.4 V) for a logic “1” and VILT (0.4 V) for a logic “0”. Measurement reference points for
inputs and outputs are VHT (2.0 V) and VLT (0.8 V). Inputs rise and fall times (10% ↔ 90%) are <10 ns.
Note: VHT–VHIGH Test
VLT–VLOW Test
VIHT–VINPUT HIGH Test
VILT–VINPUT LOW Test
3
4
5
FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS
6
7
TEST LOAD EXAMPLE
8
VDD
TO TESTER
9
RL HIGH
10
TO DUT
11
CL
RL LOW
12
13
343 ILL12.0
14
FIGURE 15: A TEST LOAD EXAMPLE
15
16
© 1999 Silicon Storage Technology, Inc.
17
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
Start
Write data: AA
Address: 5555
Write data: 55
Address: 2AAA
Write data: A0
Address: 5555
Load Word
Address/Word
Data
Wait for end of
Program (TBP,
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
343 ILL13.1
FIGURE 16: WORD PROGRAM ALGORITHM
© 1999 Silicon Storage Technology, Inc.
18
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
Internal Timer
Toggle Bit
Data# Polling
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
1
2
3
4
Read DQ7
Read word
Wait TBP,
TSCE, TSE
or TBE
5
Read same
word
Program/Erase
Completed
No
Is DQ7 =
true data?
6
Yes
7
No
Does DQ6
match?
Program/Erase
Completed
8
Yes
9
Program/Erase
Completed
343 ILL14.1
10
11
12
13
FIGURE 17: WAIT OPTIONS
14
15
16
© 1999 Silicon Storage Technology, Inc.
19
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
CFI Query Entry
Software Product ID Entry
Command Sequence
Command Sequence
Software ID Exit/CFI Exit
Command Sequence
Write data: XXAA
Address: 5555
Write data: XXAA
Address: 5555
Write data: XXAA
Address: 5555
Write data: XXF0
Address: XX
Write data: XX55
Address: 2AAA
Write data: XX55
Address: 2AAA
Write data: XX55
Address: 2AAA
Wait TIDA
Write data: XX98
Address: 5555
Write data: XX90
Address: 5555
Write data: XXF0
Address: 5555
Return to normal
operation
Wait TIDA
Wait TIDA
Wait TIDA
Read CFI data
Read Software ID
Return to normal
operation
343 ILL15.0
FIGURE 18: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS
© 1999 Silicon Storage Technology, Inc.
20
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
Chip Erase
Command Sequence
Sector Erase
Command Sequence
Block Erase
Command Sequence
1
Write data: XXAA
Address: 5555
Write data: XXAA
Address: 5555
Write data: XXAA
Address: 5555
2
3
Write data: XX55
Address: 2AAA
Write data: XX55
Address: 2AAA
Write data: XX55
Address: 2AAA
Write data: XX80
Address: 5555
Write data: XX80
Address: 5555
Write data: XX80
Address: 5555
4
5
6
Write data: XXAA
Address: 5555
Write data: XXAA
Address: 5555
Write data: XXAA
Address: 5555
Write data: XX55
Address: 2AAA
Write data: XX55
Address: 2AAA
Write data: XX55
Address: 2AAA
7
8
9
Write data: XX10
Address: 5555
Write data: XX30
Address: SAX
Write data: XX50
Address: BAX
10
11
Wait TSCE
Wait TSE
Wait TBE
Chip erased
to FFH
Sector erased
to FFH
Block erased
to FFH
12
13
14
343 ILL16.1
15
FIGURE 19: ERASE COMMAND SEQUENCE
16
© 1999 Silicon Storage Technology, Inc.
21
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
Device
SST39VF800Q
Speed Suffix1
Suffix2
- XXX XX XX
Package Modifier
K = 48 leads
Numeric = Die modifier
Package Type
E = TSOP (12mm x 20mm)
B = TFBGA (0.8 mm pitch; 8mm x 10mm)
U = Unencapsulated die
Temperature Range
C = Commercial = 0° to 70°C
I = Industrial = -40° to 85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns, 90 = 90 ns
Version
Q = VDDQ pin for I/O power supply
Voltage
V = 2.7-3.6V
SST39VF800Q Valid combinations
SST39VF800Q-70-4C-EK
SST39VF800Q-70-4C-BK
SST39VF800Q-90-4C-EK
SST39VF800Q-90-4C-BK
SST39VF800Q-70-4I-EK
SST39VF800Q-90-4I-EK
SST39VF800Q-70-4I-BK
SST39VF800Q-90-4I-BK
SST39VF800 Valid combinations
SST39VF800-70-4C-EK
SST39VF800-70-4C-BK
SST39VF800-90-4C-EK
SST39VF800-90-4C-BK
SST39VF800-70-4I-EK
SST39VF800-90-4I-EK
SST39VF800Q-90-4C-U1
SST39VF800-90-4C-U1
SST39VF800-70-4I-BK
SST39VF800-90-4I-BK
Example : Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
© 1999 Silicon Storage Technology, Inc.
22
343-04 2/99
8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
PACKAGING DIAGRAMS
1.10
0.90
1.05
0.95
PIN # 1 IDENT. DIA. 1.00
1
.50
BSC
2
.270
.170
3
12.20
11.80
4
5
0.15
0.05
18.50
18.30
6
0.70
0.50
Note:
20.20
19.80
7
1. Complies with JEDEC publication 95 MO-142 DD dimensions, although some dimensions may be more stringent.
2. All linear dimensions are in metric (min/max).
3. Coplanarity: 0.1 (±.05) mm.
48.TSOP-EK-ILL.0
8
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP)
SST PACKAGE CODE: EK
9
BOTTOM VIEW
TOP VIEW
PIN 1 CORNER
10
PIN 1 CORNER
0.30 ± 0.05 (48X)
1 2 3 4 5 6
6 5 4 3 2 1
B
B
C
C
D
E
F
5.60
0.80
A
10.00 ± 0.20
A
11
12
D
E
F
G
G
H
H
13
0.80
4.00
SIDE VIEW
14
0.15
8.00 ± 0.20
15
1.10 ± 0.10
0.21 ± 0.05
SEATING PLANE
48pn TFBGA.8x10-ILL.2
16
48-BALL THIN FINE-PITCH BALL GRID ARRAY (TFBGA)
SST PACKAGE CODE: BK
© 1999 Silicon Storage Technology, Inc.
23
343-04 2/99