ST ST3005 Speech Decoder/Encoder Notice: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. This is not a final specification. Some parameters are subject to change. 1. FEATURES n n n n n n n n n n n DSP based voice/audio processor Operation voltage – Core logic: 2.25V~2.7V – I/O pads: 3.0V~3.6V Voltage regulator for core logic Low Voltage Reset (LVR) _ 2.5V low voltage reset One PLL to generate high system frequency from a 4MHz source _ 12M~28MHz PLL output Triple clock sources _ Crystal...........................................................4MHz _ External input...… … … … … … … … … … … ......4MHz Low power down current _Typical current: 3uA One 16-bit programmable Timer One clocking output One external interrupt _ Edge/level trigger supported One 14-bit direct-drive DAC – Maximum current: 145mA n n n MCU interfaces _ Serial mode _ Parallel mode Two Serial PORT interfaces(SP) _ Programmable data length from 8-bit to 16-bit _ I2S, Left/Right Justified interfaces to external DAC/ADC Speech playback/recorder _ Low Bit Rate Compression (LBRC) _ 1.2K/1.6K/2.4Kbps@8KHz playback _ 1.6K/2.2K/[email protected] playback _ Middle Bit Rate Compression (MBRC) _ 5.4K/6.4Kbps@8KHz playback _ 7.4K/[email protected] playback _ High Bit Rate Compression (HBRC) _ 12K/16K/24Kbps@8KHz playback _ 16.5K/22K/[email protected] playback _ 24K/32K/48Kbps@16KHz playback _ 12k/16k/24kbps@8KHz encoder _ PCM playback _ Time stretch (half~double speed) 2. GENERAL DESCRIPTION The ST3005 is a highly integrated and cost-effective DSP based audio processor for various consumer applications. It consists of one powerful DSP for advanced voice decoder and encoder algorithms of natural speech with less memory. It provides low bit rate compression (LBRC) and middle bit rate (MBRC) for voice playback and high bit rate compression (HBRC) for audio or better voice quality. Both LBRC/MBRC and HBRC can playback simultaneously. For encoder, it has capability to compress PCM raw data from MCU and send back encoded data to MCU. ST3005 can adjust playback frequency (half~double speed) without pitch shifting. functional pins. Each pin can be programmed to input or output. One external interrupt pin can be requested by external devices. One internal 14bit DAC can provide significant volume equipping with internal amplifier. For particular application or recorder, two general audio interfaces are supported to interface with external DAC/ADC. Audio interface can be configured to I2S or Left/Right Justified compatible mode. There are serial and parallel interfaces for various connections with different MCUs. System clock comes from 4MHz crystal or external input. ST3005 has 32 I/Os and these can be either GPIO or Ver 0.8 1/11 2007-06-12 ST3005 2.1 Block Diagram Figure 2-1 Ver 0.8 ST3005 Block Diagram 2/11 2007-06-12 ST3005 3. SIGNAL DESCRIPTIONS Table 3-1 Function Group System control Special I/O GPIO External Interrupt Serial Port0/ DPA[4:0] Serial Port1/ DPA[12:8] MCU Interface Ver 0.8 Signal Function Description Pin Name Pin # I/O Description RESET PWD PWDA 1 1 1 I I O OSCXI 1 I OSXO ECLK 1 1 O I CMODE[1:0] 2 I TEST[2:0] SO[1:0]/ DPA[7,15] CLKO/ DPA[6] DAP[13,14], DPB[0:15] 3 I 2 O System reset, low active Power down, low active Power down acknowledge, high active Crystal input or R-oscillator input. If not used, it connects to GND Crystal output. If not used, it connects to GND External clock input. If not used, it connects to GND Clock source select 01=Crystal. ECLK connects to GND 1X=ECLK. OSCXI and OSXO connect to GND Test mode. TEST[2:0] connect to GND SO0/DPA[7], SO1/DPA[15] 1 O 18 I/O XREQ/DPA[5] 1 I TF0/DPA[0] RF0/DPA[1] TX0/DPA[2] RX0/DPA[3] SCLK0/DPA[4] TF1/DPA[8] RF1/DPA[9] TX1/DPA[10] RX1/DPA[11] SCLK1/DPA[12] 1 1 1 1 1 1 1 1 1 1 O I O I O O I O I O D[0]/SCL 1 I/O D[1]/SDI 1 I/O D[2]/SDO 1 I/O D[3:7] 5 I/O WR 1 I RD 1 I CS 1 I CMD 1 I Clock output/DPA[6] General I/O External interrupt/DPA[5] Transmit frame synchronization/DPA[0] Receive frame synchronization/DPA[1] Serial data transmit/DPA[2] Serial data receive/DPA[3] Serial clock/DPA[4] Transmit frame synchronization/DPA[8] Receive frame synchronization/DPA[9] Serial data transmit/DPA[10] Serial data receive/DPA[11] Serial clock/DPA[12] Parallel : Data bus Serial : Serial clock Parallel : Data bus Serial : Serial data input Parallel : Data bus Serial : Serial data output Parallel : Data bus Serial : Not used Parallel : Write enable, low active Serial : Not used Parallel : Read enable, low active Serial : Not used Parallel : Chip select, low active Serial : Chip select Parallel : Command/data select “H”: Data “L”: Command Serial : Not used 3/11 2007-06-12 ST3005 Power Regulator DAC Ver 0.8 REQ RDY 1 1 O O PMODE 1 I P/S 1 I VDD25 VSS25 VDD33 VSS33 REGVDD33 REGVSS33 PLLVDD25 PLLVSS25 PLLVDD25A PLLVSS25A DACVDD33A DACVSS33A DACOVDD33A DACOVSS33A VCCOUT VREF DACO DACOB VCM 2 2 2 2 1 1 1 1 1 1 1 1 2 2 1 1 2 2 1 I I I I I I I I I I I I I I O O O O O DSP wants to sent command to MCU, low active DSP permit MCU access data, low active, not used Parallel interface select 0: Parallel (default). Connecting to GND 1: Not used Parallel/serial interface select 0: Serial 1: Parallel 2.5V power 2.5V power ground 3.3V power 3.3V power ground Digital power input of regulator Digital power ground of regulator Digital power input of PLL Digital power ground of PLL Analog power input of PLL Analog power ground of PLL Analog power input of DAC Analog power ground of DAC Analog power input of DAC output stage Analog power ground of DAC output stage 2.5V output of regulator Voltage reference DAC direct drive pin(+) DAC direct drive pin(-) Common mode voltage reference 4/11 2007-06-12 ST3005 4. ELECTRICAL CHARACTERISTICS 4.1 Absolute Maximum Rations *Note: Stresses above those listed under “Absolute Maximum DC Supply Voltage: VDD33 ---------------- -0.3V to +4.5V Operating Ambient Temperature --------- -10°C to +60°C Storage Temperature ------------------------ -10°C to +125°C Ratings” may cause permanent damage to the device. All the ranges are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposed to the absolute maximum rating conditions for extended periods may affect device reliability. 4.2 DC Electrical Characteristics Table 4-1 DC Electrical Characteristics Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25°C, unless otherwise specified Parameter Symbol Min. Operating Voltage VDD33 3.0 Operating Voltage VDD25 2.25 Operating Current IOP1 30 Power Down Current IPD 3 Output driving Iod 16 mA Output sinking Ios 26 mA Input low voltage V IL 0.6 V Input high voltage VIH 1.3 V Pull-up resistor RPU 54 KΩ Pull-down resistor R PD 50 KΩ Low Voltage Reset Level VLVR Ver 0.8 2.4 Typ. 2.5 2.5 5/11 Max. Unit 3.6 V 2.7 V mA 4.5 2.6 Condition Run at 24MHz without speaker mA V 2007-06-12 ST3005 4.3 AC Electrical Characteristics Figure 4-1 Figure 4-2 Ver 0.8 Serial Interface Timing Diagram Parallel Interface Timing Diagram 6/11 2007-06-12 ST3005 Table 4-2 Timing parameters for 0 Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25°C Symbol Characteristic Min. st Rating Typ. Max. Unit tCSS tCYC CS low to 1 SCL rising SCL cycle time 100 200 nS nS tDS tDH Data valid prior SCL falling Data Hold time after SCL rising 0 10 nS nS tDD SDO output delay from SCL falling Table 4-3 10 nS Timing parameters for 0 Standard operation conditions: VDD33 = 3.3V, GND = 0V, TA = 25°C Symbol Characteristic Min. Rating Typ. Max. Unit tCH Cmd pin hold time 5 nS tCS tCYC Cmd pin setup time System cycle time 5 3.5D nS nS tCCLW tCCHW Write pulse width Enable H write width 0.5D 3D nS nS tCCLR tCCHR Read pulse width Enable H read width 0.5D 3D nS nS tDS tDH Write data setup time Write data hold time 0.5D 5 nS nS tACC tOH Read access time Read data disable time 25 4 nS nS Remark: D = time of one DSP system clock Ver 0.8 7/11 2007-06-12 ST3005 5. PAD DIAGRAM Ver 0.8 8/11 2007-06-12 ST3005 6. DEVICE INFORMATION 1. Substrate: GND PAD Symbol No. X Y PAD Symbol No. X Y PAD No. Symbol X Y P/S 720 3107.5 1 TF0 1616.23 62.5 31 DPB7 2977.5 2036.55 61 2 RF0 1716.23 62.5 32 DPB8 2977.5 2136.55 62 RESET 620 3107.5 DPB9 2977.5 2236.55 63 CMODE0 520 3107.5 3 TX0 1816.23 62.5 33 4 RX0 1916.23 62.5 34 DPB10 2977.5 2336.55 64 CMODE1 420 3107.5 2016.23 62.5 35 DPB11 2977.5 2436.55 65 OSCXI 320 3107.5 3107.5 5 SCLK0 6 XREQ 2116.23 62.5 36 DPB12 2977.5 2546.55 66 OSXO 210 7 CLKO 2216.23 62.5 37 DPB13 2977.5 2656.55 67 ECLK 100 3107.5 DPB14 2977.5 2766.55 68 VREF 62.5 2753.04 8 SO0 2316.23 62.5 38 9 TF1 2416.23 62.5 39 DPB15 2940 3107.5 69 VCCOUT 62.5 2643.04 VSS33 2830 3107.5 70 REGVDD33 62.5 2533.04 10 RF1 2516.23 62.5 40 11 TX1 2616.23 62.5 41 VDD33 2720 3107.5 71 REGVSS33 62.5 2433.04 PWDA 2620 3107.5 72 PLLVSS25 62.5 2257.04 12 RX1 2716.23 62.5 42 13 SCLK1 2826.23 62.5 43 PWD 2520 3107.5 73 PLLVDD25 62.5 2157.04 D7 2420 3107.5 74 PLLVSS25A 62.5 2057.04 14 DPA13 2936.23 62.5 44 15 DPA14 2977.5 406.55 45 D6 2320 3107.5 75 PLLVDD25A 62.5 1957.04 D5 2220 3107.5 76 DACVSS33A 62.5 1781.04 16 SO1 2977.5 516.55 46 17 VDD25 2977.5 626.55 47 D4 2120 3107.5 77 DACVDD33A 62.5 1681.04 18 VSS25 2977.5 736.55 48 D3 2020 3107.5 78 VCM 62.5 1581.04 SDO 1920 3107.5 79 DACOB 62.5 1481.04 DACOB 19 TEST2 2977.5 836.55 49 20 TEST1 2977.5 936.55 50 SDI 1820 3107.5 80 62.5 1381.04 SCL 1720 3107.5 81 DACOVSS33A 62.5 1281.04 21 TEST0 2977.5 1036.55 51 22 VSS33 2977.5 1136.55 52 VDD25 1620 3107.5 82 DACOVSS33A 62.51 1181.04 VSS25 1520 3107.5 83 DACOVDD33A 62.5 1081.04 23 VDD33 2977.5 1236.55 53 24 DPB0 2977.5 1336.55 54 CMD 1420 3107.5 84 DACOVDD33A 62.5 981.04 PMODE 1320 3107.5 85 DACO 62.5 881.04 86 DACO 62.5 781.04 25 DPB1 2977.5 1436.55 55 26 DPB2 2977.5 1536.55 56 REQ 1220 3107.5 RDY 1120 3107.5 27 DPB3 2977.5 1636.55 57 28 DPB4 2977.5 1736.55 58 WR 1020 3107.5 RD 920 3107.5 CS 820 3107.5 29 DPB5 2977.5 1836.55 59 30 DPB6 2977.5 1936.55 60 Ver 0.8 9/11 2007-06-12 ST3005 7. APPLICATION CIRCUIT Figure 7-1 Application Circuit Diagram Note: 1. 47uF capacitor must be close to DACOVDD33A and DACOVSS33A. 2. If any of OSCXI, OSXO, and ECLK is not used, it needs to connect to GND. 3. The cascade resistor and parallel capacitor on CMD, RD, WR, and CS pins can reduce noise interference. In general, resistor is short and capacitor is open. Please preserve the options on PCB. 4. R2 resistor can adjust headphone volume. Ver 0.8 10/11 2007-06-12 ST3005 8. REVISION REVISION DESCRIPTION 0.1 First release 1. Change PLL maximum output from 36MHz to 32MHz 2. Revise HBRC 11.025kHz playback bps value 3. Add 12k/16k/24kbps@8KHz encoder 4. A drawback of using R-oscillator clock is described 5. Add DC Electrical Characteristics 6. Remove VREF, CLICK, IREF capacitor 7. Revise R-oscillator voltage from VDD33 to VDD25, revise R resistor from 100kOhn to 97kOhm, remove 100pF capacitor 8. Wire SO1 and PWD pins 9. PMODE shorts to GND 10. Relocate RDY pin from MCU parallel and serial interface 1. Add MBRC 2. Modify DAC driving capacity 3. Change IREF to DACVDD33A, change CLICK to DACVSS33A 4. Rename DACVDD33A to DACOVDD33A, rename DACVSS33A to DACOVSS33A 1. TEST[2:0] wire to GND 2. WR, RD cascade 120 Ohm and parallel 10p capacitor 3. ECLK cascade 100 Ohm to low noise 4. Remove R-Oscillator function 1. System low voltage changes from 2.7V to 3.0V 2. The resistor in RD/WR changes from 120Ohm to 220Ohm 1. Change PLL output frequency from 32MH to 28MHz 2. Add inductor and capacitor before power input, revise regulator output capacitor, DACVDD33A and DACOVDD33A power come from battery, add 4MHz crystal label 1. Add CMODE, ECLK, TEST pins descriptions 2. Revise PMODE pin parallel interface select description 3. Revise output driving/sinking, input low/high, and input pull-up/pull-down resistor DC electrical characteristics 4. Revise Read access time from 10ns to 25ns 5. Remove external DAC/ADC block, DC2DC block. Add headphone jack and CMD pin cascade resistor and parallel capacitor. Revise DAC power circuit. Add note item 2 to 4 1. Revise parallel interface timing diagram(CWD pin change to CMD Pin) 2. Application circuit diagram Add parallel capacitor and cascade resistor circuit on CS pin 0.2 0.3 0.4 0.5 0.6 0.7 0.8 PAGE DATE 2005/03/15 1 1 1 1 1,5 10 10 10 10 10 1 1 2,4,8,9,10 2,4,8,9,10 1 10 10 1,3,10 1 10 1 10 2005/05/12 2005/06/28 2005/0705 2005/08/02 2005/09/05 3 4 5 7 10 6 10 2006/03/17 2006/04/25 The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix. Sitronix Technology Corp. reserves the right to change this document without prior notice and makes no warranty for any errors which may appear in this document. Sitronix products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where products failure could result in injury, or loss of life, or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. Ver 0.8 11/11 2007-06-12